first commit

43code.asm

@@ -0,0 +1,28 @@
+Code:
+	XDEF	Entry
+	XREF	__SEG_END_SSTACK
+Constants:		Section
+ARRAY		dc.b	$EB,$77,$7B,$7D,$B7,$BB,$BD,$D7,$DB,$DD,$E7,$ED,$7E,$BE,$DE,$EE,$00
+INDEX		ds.w	1
+val		ds.b	1
+
+Code:			Section
+Entry:
+		LDX	#ARRAY	;start X at begging of array
+		LDY	#ARRAY	;this will allow us to subtract and find the index
+Main:
+		LDAA	1,X+		;load the first byte into acc. A
+		CMPA	#$00		;the value was not found
+		BEQ	NotFound
+
+		CMPA	val		;check if A is equal to the value
+		BNE	Main		;repeat the loop if it is not
+
+		CMPA	val		;check if A is equal to the value
+		BEQ	Found
+
+Found:
+		TFR	X,D		;store the value of x in acc. D
+		SUBD	#ARRAY	;subtract the the value of the start of the array from D
+NotFound:
+		STAA	#$FF

4_1_2.txt

@@ -0,0 +1,51 @@
+	XDEF	Entry
+	XREF	__SEG_END_SSTACK
+
+Variables:		Section
+
+Constants:		Section
+SEQUENCE_1	dc.b 	$81,$42,$24,$18,$24,$42,$42,$00
+SEQUENCE_2	dc.b	$80,$40,$20,$10,$08,$04,$01,$01,$00
+DDR_S		equ	$24A
+DDR_T		equ
+PORT_S	equ	$248
+PORT_T	equ	$240
+
+Code:			Section
+Entry:
+		LDAA	#$FF		;load all 1’s to acc. A
+		STAA	DDR_S		;set all 1’s from acc. to Port S DDR (all outputs)
+
+		LDAA	#$00		;8-bit all 0’s in acc. A
+		STAA	DDR_T		;set all 0’s for Port T DDR (all inputs)
+
+;use register X to point to the index of SEQUENCE_1
+;use register Y to point to the index of SEQUENCE_2
+;use acc. A to output the LED’s at Port S
+;use acc. B to read the DIP switch at Port T
+
+Loop1:	;loop for SEQUENCE_1
+
+		LDX	#SEQUENCE_1	;load the address of the 1st seq. value to reg. X
+		LDAA	1,X+		;load the value at address X to acc. A, increment X
+		STAA	PORT_S	;output the value of acc. A to PORT_S
+
+		LDAB	PORT_T	;load the DIP switches to acc. B
+		CMPB	#$00		;check if the DIP switches are all off
+		BNE	Loop2		;branch to Loop2 if a switch is on
+
+		CMPA	#$00		;check if we are at the end of the array
+		BEQ	Loop1		;loop if we are at the last array value
+
+Loop2:	;loop for SEQUENCE_2
+
+		LDY	#SEQUENCE_2	;load the address of the 2nd seq. value to reg. Y
+		LDAA	1,Y+		;load the value at address Y to acc. A
+		STAA	PORT_S	;output acc. A to Port S
+
+		LDAB	PORT_T	;load the DIP switches to acc. B
+		CMPB	#$00		;check if the DIP switches are all off
+		BEQ	Loop1		;branch to Loop1 if all switches are off
+
+		CMPA	#$00		;check if we are at the end of the array
+		BEQ	Loop2		;continue from the beginning of SEQUENCE_2

5_1_1a.txt

@@ -0,0 +1,32 @@
+	XDEF	Entry
+	XREF	__SEG_END_SSTACK
+
+Variables:		Section
+VAR_1       dc.b	$EC
+
+Constants:	     Section
+DDR_S	    equ	  	$24A
+DDR_T	    equ   	$242
+PORT_T      equ     $240
+PORT_S      equ     $248
+
+Code:			Section
+Entry:
+			BSET		DDR_S,#$FF	;set all bits of DDR_S (output)
+			BSET		DDR_T,#$00	;clear all bits of DDR_T (input)
+
+			LDAA		#$00		;all 0's (off)
+			STAA		PORT_S		;turn off all LED's
+
+			LDAA		VAR_1		;read VAR_1 into acc. A
+			ANDA		#%11011111	;clear bit 6
+			ORAA		#%00001000	;set bit 4
+			STAA		VAR_1		;store again into VAR_1
+
+CheckDIP:
+			LDAB		PORT_T		;read the DIP switches into acc. B
+			ANDB		#%00000001	;mask all but switch bit 0
+			BEQ			CheckDIP	;check switches in a loop (exit loop if switch bit 0 is set)
+
+			LDAA		VAR_1		;read VAR_1 back into acc. A
+			STAA		PORT_S		;write acc. A (set to VAR_1) to LED's

5_1_1b.txt

@@ -0,0 +1,38 @@
+	XDEF	Entry
+	XREF	__SEG_END_SSTACK
+
+Variables:		Section
+VAR_1       dc.b	   $EC
+
+Constants:	     Section
+DDR_S	    equ	  	$24A
+DDR_T	    equ   	$242
+PORT_T      equ     $240
+PORT_S      equ     $248
+
+Code:			Section
+Entry:
+			BSET		DDR_S,#$FF	;set all bits of DDR_S (output)
+			BSET		DDR_T,#$00	;clear all bits of DDR_T (input)
+
+			LDAA		#$00		;all 0's (off)
+			STAA		PORT_S		;turn off all LED's
+
+			LDAA		VAR_1		;read VAR_1 into acc. A
+			ANDA		#%11011111	;clear bit 6
+			ORAA		#%00001000	;set bit 4
+			STAA		VAR_1		;store again into VAR_1
+
+CheckOff:
+			LDAB		PORT_T		;read the DIP switches into acc. B
+			ANDB		#%00000010	;mask all but switch bit 1
+			BEQ			CheckOff    ;check switch bit 1 in a loop (exit this loop if switch 1 is unset)
+
+CheckOn:
+			LDAB		PORT_T		;read the DIP switches into acc. B
+			ANDB		#%00000010	;mask all but switch bit 1
+			BNE			CheckOn     ;check switch bit 1 in a loop (exit this loop if switch 1 is set)
+
+			LDAB		PORT_T
+			BITB		#%00000010
+			BVS		    OffLoop

5_1_2.txt

@@ -0,0 +1,42 @@
+	XDEF	Entry
+	XREF	__SEG_END_SSTACK
+
+Variables:		Section
+
+Constants:	     Section
+DDR_S	    equ	  	$24A
+DDR_T	    equ   	$242
+PORT_T      equ     $240
+PORT_S      equ     $248
+
+;starts high -> goes low -> goes high -> light on
+;starts low -> goes high -> goes low -> goes high -> light on
+
+Code:			Section
+Entry:
+            BSET    DDR_S,#$FF              ;set all bits of DDR_S as output
+			BSET	DDR_T,#$00	            ;clear all bits of DDR_T (input)
+
+            BSET    PORT_S,#$00             ;turn off all LED's
+
+Check1:
+            ;if switch starts low
+            LDAA    #$00                    ;condition of switch started low
+            BRCLR   PORT_T,#$01,AwaitHigh      ;enter the high wait loop (switch started low)
+
+            ;if switch starts high
+            LDAA    #$01                    ;condition of switch started high
+                                            ;proceed to low check loop if started high
+
+AwaitLow:                                     ;loop until bit 0 is set low
+            BRSET   PORT_T,#$01,AwaitLow      ;repeats if bit 0 is high/on (stops looping if low)
+
+AwaitHigh:                                     ;loop until bit 0 is set high
+            BRCLR   PORT_T,#$01,AwaitHigh      ;repeats if bit 0 is low/off (stops looping if high)
+            ANDA    #$01                    ;checks if the switch started high
+            BEQ     AwaitLow                  ;if started low, wait for it to go high again
+
+Out:
+            BSET    PORT_S,#%01000000       ;turn on LED 6
+            NOP
+

5_2.txt

@@ -0,0 +1,63 @@
+	XDEF	Entry
+	XREF	__SEG_END_SSTACK
+
+; variable/data w
+MY_EXTENDED_RAM: SECTION
+FORWARD     dc.b    $0A,$12,$14,$0C,$00
+REVERSE     dc.b    $0C,$14,$12,$0A,$00
+PORT_P      equ     $258
+DDR_P       equ     $25A
+PORT_T      equ     $240
+DDR_T	    equ   	$242
+
+MY_CONSTANT_ROM: SECTION ; constant/definition section
+
+; code section
+MyCode:     SECTION
+main:
+_Startup:
+
+Entry:
+        LDAA    #$1E            ;load the proper DDR direction modes to acc. A
+        STAA    DDR_P           ;push the DDR direction modes into port P DDR
+        LDAA    #00             ;load port T DDR into acc. A
+        STAA    DDR_T           ;push direction to port T DDR
+
+Main:
+        BRSET   PORT_P,#%00000011,Main     ;do nothing if both bits are set
+        BRCLR   PORT_P,#%00000011,Main     ;do nothing if both bits are clear
+
+StartForward:
+        LDX     #FORWARD                        ;load the start of sequence of bytes to spin the motor into register X
+        BRA     Spin
+
+StartReverse:                           ;initialize the reverse loop
+        LDX     #REVERSE
+        BRA     Spin
+
+Spin:
+        LDAA    1,x+            ;load into A the first value of the array
+        CMPA    #00             ;check that we are not at the end of the array
+        BEQ     Main            ;if we are at the end of the array, reload the first array value
+        STAA    PORT_P          ;push the value in accumulator A to port P, spinning the motor one quarter turn
+
+        ;check fast or slow
+        ;branch to appropriate delay
+
+        ;check direction
+        ;branch to appropriate start direction
+
+
+ShortDelay:                     ;implement a 15 ms delay
+        LDY     #15000
+        BRA     DelayLoop
+
+LongDelay:
+        LDY     #60000          ;implement a 60 ms delay
+        BRA     DelayLoop
+
+DelayLoop:                      ;loop execution
+        DEY                     ;decrement our delay value by 1
+        BNE     DelayLoop       ;if we have not decreased our delay value to zero, continue
+                                ;decrementing our array value
+        BRA     Main            ;repeat the code which turns the motor

5_3.txt

@@ -0,0 +1,12 @@
+	XDEF	Entry
+	XREF	__SEG_END_SSTACK
+
+Variables:		Section
+
+Constants:	     Section
+DDR_U	    equ	  	$26A
+PSR_U       equ     $26D
+
+Code:			Section
+Entry:
+            BSET    DDR_U,#$F0

Final_Project/C_Layout.hwl

@@ -0,0 +1,20 @@
+OPEN source 0 0 60 39
+Source < attributes MARKS off
+OPEN assembly 60 0 40 31
+Assembly < attributes ADR on,CODE off,ABSADR on,SYMB off,TOPPC 0xF88C
+OPEN procedure 0 39 60 17
+Procedure < attributes VALUES on,TYPES off
+OPEN register 60 31 40 25
+Register < attributes FORMAT AUTO,COMPLEMENT None
+OPEN memory 60 56 40 22
+Memory < attributes FORMAT hex,COMPLEMENT None,WORD 1,ASC on,ADR on,ADDRESS 0x80
+OPEN data 0 56 60 22
+Data:1 < attributes SCOPE global,COMPLEMENT None,FORMAT Symb,MODE automatic,UPDATERATE 10,NAMEWIDTH 16
+OPEN data 0 78 60 22
+Data:2 < attributes SCOPE local,COMPLEMENT None,FORMAT Symb,MODE automatic,UPDATERATE 10,NAMEWIDTH 16
+OPEN command 60 78 40 22
+Command < attributes CACHESIZE 1000
+bckcolor 50331647
+font 'Courier New' 9 BLACK
+AUTOSIZE on
+ACTIVATE Data:2 Command Procedure Data:1 Source Register Assembly Memory

Final_Project/Full_Chip_Simulation.ini

@@ -0,0 +1,23 @@
+[Environment Variables]
+GENPATH={Project}Sources;{Compiler}lib\hc12c\src;{Compiler}lib\hc12c\include;{Compiler}lib\hc12c\lib;{Compiler}lib\xgatec\src;{Compiler}lib\xgatec\include;{Compiler}lib\xgatec\lib
+LIBPATH={Compiler}lib\hc12c\include;{Compiler}lib\xgatec\include
+OBJPATH={Project}bin
+TEXTPATH={Project}bin
+ABSPATH={Project}bin
+
+[HI-WAVE]
+Target=sim
+Layout=C_layout.hwl
+LoadDialogOptions=AUTOERASEANDFLASH RUNANDSTOPAFTERLOAD="main"
+CPU=HC12
+
+[Simulator]
+CMDFILE0=CMDFILE STARTUP ON ".\cmd\Full_Chip_Simulation_startup.cmd"
+
+[Simulator HC12]
+CMDFILE0=CMDFILE RESET ON ".\cmd\Full_Chip_Simulation_reset.cmd"
+CMDFILE1=CMDFILE PRELOAD ON ".\cmd\Full_Chip_Simulation_preload.cmd"
+CMDFILE2=CMDFILE POSTLOAD ON ".\cmd\Full_Chip_Simulation_postload.cmd"
+CMDFILE3=CMDFILE SETCPU ON ".\cmd\Full_Chip_Simulation_setcpu.cmd"
+HCS12_SUPPORT=1
+FCS=MC9S12E128

Final_Project/P&E_Multilink_CyclonePro.ini

@@ -0,0 +1,107 @@
+
+[HI-WAVE]
+Target=icd12
+Layout=C_layout.hwl
+LoadDialogOptions=AUTOERASEANDFLASH NORUNAFTERLOAD 
+CPU=HC12
+MainFrame=2,3,-1,-1,-1,-1,228,354,1480,1093
+TOOLBAR=57600 57601 32795 0 57635 57634 57637 0 57671 57669 0 32777 32776 32782 32780 32781 32778 0 32806
+AEFWarningDialog=FALSE
+
+
+
+
+[ICD12]
+CMDFILE0=CMDFILE STARTUP ON ".\cmd\P&E_Multilink_CyclonePro_startup.cmd"
+CMDFILE1=CMDFILE RESET ON ".\cmd\P&E_Multilink_CyclonePro_reset.cmd"
+CMDFILE2=CMDFILE PRELOAD ON ".\cmd\P&E_Multilink_CyclonePro_preload.cmd"
+CMDFILE3=CMDFILE POSTLOAD ON ".\cmd\P&E_Multilink_CyclonePro_postload.cmd"
+CMDFILE4=CMDFILE VPPON ON ".\cmd\P&E_Multilink_CyclonePro_vppon.cmd"
+CMDFILE5=CMDFILE VPPOFF ON ".\cmd\P&E_Multilink_CyclonePro_vppoff.cmd"
+CMDFILE6=CMDFILE UNSECURE ON ".\cmd\P&E_Multilink_CyclonePro_erase_unsecure_hcs12.cmd"
+MCUID=0x03D0
+COMSETTINGS=SETCOMM DRIVER NOPROTOCOL NOPERIODICAL
+SETCLKSW=0
+HOTPLUGGING=0
+DETECTRUNNING=0
+RESYNCONCOPRESET=0
+BDMAutoSpeed=0
+BDMClockSpeed=29
+HIGHIODELAYCONSTFORPLL=40
+
+
+
+
+
+
+
+
+[HC12MultilinkCyclonePro_GDI_SETTINGS]
+CMDFILE0=CMDFILE STARTUP ON ".\cmd\P&E_Multilink_CyclonePro_startup.cmd"
+CMDFILE1=CMDFILE RESET ON ".\cmd\P&E_Multilink_CyclonePro_reset.cmd"
+CMDFILE2=CMDFILE PRELOAD ON ".\cmd\P&E_Multilink_CyclonePro_preload.cmd"
+CMDFILE3=CMDFILE POSTLOAD ON ".\cmd\P&E_Multilink_CyclonePro_postload.cmd"
+CMDFILE4=CMDFILE VPPON ON ".\cmd\P&E_Multilink_CyclonePro_vppon.cmd"
+CMDFILE5=CMDFILE VPPOFF ON ".\cmd\P&E_Multilink_CyclonePro_vppoff.cmd"
+CMDFILE6=CMDFILE UNSECURE ON ".\cmd\P&E_Multilink_CyclonePro_erase_unsecure_hcs12.cmd"
+MCUID=0x03D0
+CHIPSECURE=CHIPSECURE SETUP 0xFF0F 0x3 0x2
+DBG_S12_0=DBG GENERAL DISARM_ON PROTECT_OFF ANALYZE_ON STEPATRUN_ON
+DBG_S12_1=DBG PREDEFINED SELECT 0
+DBG_S12_2=DBG PREDEFINED DBGENGINE END STOP 0x0 DATAMATCH_HIGH NORMAL
+DBG_S12_3=DBG USER 0x0 0x0 0x0 0x0
+NV_PARAMETER_FILE=C:\Program Files (x86)\Freescale\CWS12v5.1\prog\FPP\mcu03D0.fpp
+NV_SAVE_WSP=0
+NV_AUTO_ID=1
+
+
+
+
+
+
+
+
+
+[STARTUP]
+IO_DELAY_SET=1
+frequency_has_changed_old_io_delay_cnt=29
+CPUTARGETTYPE=0
+USE_CYCLONEPRO_RELAYS=1
+CyclonePro_poweroffonexit=0
+CyclonePro_currentvoltage=255
+CyclonePro_PowerDownDelay=250
+CyclonePro_PowerUpDelay=250
+IO_DELAY_CNT=29
+PCI_DELAY=0
+RESET_DELAY=0
+PORT=21
+interface_selection=1
+SHOWDIALOG=0
+
+
+[PORT]
+IP=
+
+
+[Recent Applications File List]
+File0=C:\Users\ahagyous\Desktop\Lab 6-2\Start_C_ASM\bin\Project.abs
+File1=H:\ece488\test1\Speaker\Start_C_ASM\Start_C_ASM\bin\Project.abs
+File2=
+File3=
+LoadFlags0=AUTOERASEANDFLASH RUNAFTERLOAD
+LoadFlags1=AUTOERASEANDFLASH RUNANDSTOPAFTERLOAD="main"
+LoadFlags2=
+LoadFlags3=
+
+
+[Recent Layout File List]
+File0=C_layout.hwl
+File1=
+File2=
+File3=
+[Environment Variables]
+GENPATH={Project}Sources;{Compiler}lib\hc12c\src;{Compiler}lib\hc12c\include;{Compiler}lib\hc12c\lib;{Compiler}lib\xgatec\src;{Compiler}lib\xgatec\include;{Compiler}lib\xgatec\lib
+OBJPATH={Project}bin
+TEXTPATH={Project}bin
+ABSPATH={Project}bin
+LIBPATH={Compiler}lib\hc12c\include;{Compiler}lib\xgatec\include

Final_Project/P&E_Multilink_USB.ini

@@ -0,0 +1,82 @@
+[STARTUP]
+CPUTARGETTYPE=0
+USE_CYCLONEPRO_RELAYS=0
+PORT=21
+interface_selection=1
+SHOWDIALOG=0
+IO_DELAY_SET=1
+frequency_has_changed_old_io_delay_cnt=29
+CyclonePro_poweroffonexit=0
+CyclonePro_currentvoltage=255
+CyclonePro_PowerDownDelay=250
+CyclonePro_PowerUpDelay=250
+IO_DELAY_CNT=29
+PCI_DELAY=0
+RESET_DELAY=0
+
+
+
+
+
+
+
+
+
+
+[Environment Variables]
+GENPATH={Project}Sources;{Compiler}lib\hc12c\src;{Compiler}lib\hc12c\include;{Compiler}lib\hc12c\lib;{Compiler}lib\xgatec\src;{Compiler}lib\xgatec\include;{Compiler}lib\xgatec\lib
+LIBPATH={Compiler}lib\hc12c\include;{Compiler}lib\xgatec\include
+OBJPATH={Project}bin
+TEXTPATH={Project}bin
+ABSPATH={Project}bin
+
+[HI-WAVE]
+Target=icd12
+Layout=C_layout.hwl
+LoadDialogOptions=AUTOERASEANDFLASH RUNANDSTOPAFTERLOAD="main"
+CPU=HC12
+MainFrame=2,3,-1,-1,-1,-1,104,104,1304,953
+TOOLBAR=57600 57601 32795 0 57635 57634 57637 0 57671 57669 0 32777 32776 32782 32780 32781 32778 0 32806
+AEFWarningDialog=FALSE
+
+
+
+
+[HC12MultilinkCyclonePro_GDI_SETTINGS]
+CMDFILE0=CMDFILE STARTUP ON ".\cmd\P&E_Multilink_USB_startup.cmd"
+CMDFILE1=CMDFILE RESET ON ".\cmd\P&E_Multilink_USB_reset.cmd"
+CMDFILE2=CMDFILE PRELOAD ON ".\cmd\P&E_Multilink_USB_preload.cmd"
+CMDFILE3=CMDFILE POSTLOAD ON ".\cmd\P&E_Multilink_USB_postload.cmd"
+CMDFILE4=CMDFILE VPPON ON ".\cmd\P&E_Multilink_USB_vppon.cmd"
+CMDFILE5=CMDFILE VPPOFF ON ".\cmd\P&E_Multilink_USB_vppoff.cmd"
+CMDFILE6=CMDFILE UNSECURE ON ".\cmd\P&E_Multilink_USB_erase_unsecure_hcs12.cmd"
+MCUID=0x03D0
+CHIPSECURE=CHIPSECURE SETUP 0xFF0F 0x3 0x2
+DBG_S12_0=DBG GENERAL DISARM_ON PROTECT_OFF ANALYZE_ON STEPATRUN_ON
+DBG_S12_1=DBG PREDEFINED SELECT 0
+DBG_S12_2=DBG PREDEFINED DBGENGINE END STOP 0x0 DATAMATCH_HIGH NORMAL
+DBG_S12_3=DBG USER 0x0 0x0 0x0 0x0
+NV_PARAMETER_FILE=C:\Program Files (x86)\Freescale\CWS12v5.1\prog\FPP\mcu03D0.fpp
+NV_SAVE_WSP=0
+NV_AUTO_ID=1
+
+
+
+
+
+
+
+
+
+[ICD12]
+COMSETTINGS=SETCOMM DRIVER NOPROTOCOL NOPERIODICAL
+SETCLKSW=0
+HOTPLUGGING=0
+DETECTRUNNING=0
+RESYNCONCOPRESET=0
+BDMAutoSpeed=0
+BDMClockSpeed=29
+HIGHIODELAYCONSTFORPLL=40
+
+[PORT]
+IP=

Final_Project/Sources/IRQ_ISR.asm

@@ -0,0 +1,5 @@
+              XDEF      IRQ_ISR
+
+IRQ_ISR:      
+
+

Final_Project/Sources/SendsChr.c

@@ -0,0 +1,22 @@
+#include <hidef.h>                  /* common defines and macros */
+#include "derivative.h"             /* derivative-specific definitions */
+#include "funct.h"
+
+int tone=0;							//value to hold the tone to be generated
+int tone_count=0;					//counter to test the tone to be generated
+
+void SendsChr(char NewTone, int dummy)
+{
+	dummy++;						//increment the dummy value to supress the warning
+	tone=NewTone;					//set the tone passed on the stack
+}
+
+void PlayTone(void)
+{
+	tone_count++;					//increment tone counter
+	if(tone_count>=tone)			//if the tone count is equal to or higher than the tone
+	{
+		tone_count=0;			   //reset the counter
+		PTT = PTT ^ 0x20;		   //toggle the speaker bit.
+	}
+}

Final_Project/Sources/circulation.asm

@@ -0,0 +1,92 @@
+ 	XDEF	Circulation
+	XREF	__SEG_END_SSTACK,show_temperature,display_string,disp,dc_on,pw_set,PORT_T,PORT_S
+	
+Circulation: ;push register and accumulator values for retention                   
+            PSHA
+            PSHB
+            PSHD
+            PSHX
+            PSHY
+            
+
+           ;bail if the password is not set
+           LDAA   pw_set
+           CMPA   #$FF
+           LBNE   Return
+            
+           ;
+           ;run the motor and stuff like that here
+           ;(the motor should run whether or not
+           ;the temperature is displayed) 
+           ;
+           LDAA   dc_on
+           CMPA   #$FF
+           BNE    PulseOff
+
+PulseOn:
+            BSET  PORT_T,#$8       ;set bit 3 of Port T
+            ;MOVB  #$0F,PORT_S
+            BRA   PrintTemperature ;exit the interrupt routine
+
+PulseOff:
+            BCLR  PORT_T,#$8       ;clear bit 3 of Port T
+            ;MOVB  #$F0,PORT_S
+            BRA   PrintTemperature ;exit the interrupt 
+             
+PrintTemperature:
+
+           ;check if the temperature should show
+           LDAA  show_temperature
+           CMPA  #$00
+           LBEQ   Return
+           
+          ;print the temperature
+           movb #'T',disp
+           movb #'e',disp+1
+           movb #'m',disp+2
+           movb #'p',disp+3
+           movb #'e',disp+4
+           movb #'r',disp+5
+           movb #'a',disp+6
+           movb #'t',disp+7
+           movb #'u',disp+8
+           movb #'r',disp+9
+           movb #'e',disp+10
+           movb #':',disp+11
+           movb #' ',disp+12
+           movb #' ',disp+13
+           movb #' ',disp+14
+           movb #' ',disp+15
+           ;next line
+           movb #'X',disp+16
+           movb #'Y',disp+17
+           movb #'Z',disp+18
+           movb #' ',disp+19
+           movb #'d',disp+20
+           movb #'e',disp+21
+           movb #'g',disp+22
+           movb #'r',disp+23
+           movb #'e',disp+24
+           movb #'e',disp+25
+           movb #'s',disp+26
+           movb #' ',disp+27
+           movb #' ',disp+28
+           movb #' ',disp+29
+           movb #' ',disp+30
+           movb #' ',disp+31
+           movb #0,disp+32    ;string terminator, acts like '\0'
+           
+           LDD   #disp         ;both of these steps are necessary to
+           jsr  display_string ;print to the LCD screen          
+    
+Return:     ;restore registers and accumulators
+           PULY
+           PULX
+           PULD
+           PULB
+           PULA
+           
+           RTS
+   
+	
+	

Final_Project/Sources/datapage.c

@@ -0,0 +1,1970 @@
+/******************************************************************************
+  FILE        : datapage.c
+  PURPOSE     : paged data access runtime routines
+  MACHINE     : Freescale 68HC12 (Target)
+  LANGUAGE    : ANSI-C
+  HISTORY     : 21.7.96 first version created
+******************************************************************************/
+
+#include "hidef.h"
+
+#include "non_bank.sgm"
+#include "runtime.sgm"
+
+
+
+#ifndef __HCS12X__ /* it's different for the HCS12X. See the text below at the #else // __HCS12X__ */
+
+/*
+   According to the -Cp option of the compiler the
+   __DPAGE__, __PPAGE__ and __EPAGE__ macros are defined.
+   If none of them is given as argument, then no page accesses should occur and
+   this runtime routine should not be used !
+   To be on the save side, the runtime routines are created anyway.
+   If some of the -Cp options are given an adapted versions which only covers the
+   needed cases is produced.
+*/
+
+/* if no compiler option -Cp is given, it is assumed that all possible are given : */
+
+/* Compile with option -DHCS12 to activate this code */
+#if defined(HCS12) || defined(_HCS12) || defined(__HCS12__) /* HCS12 family has PPAGE register only at 0x30 */
+#define PPAGE_ADDR (0x30+REGISTER_BASE)
+#ifndef __PPAGE__ /* may be set already by option -CPPPAGE */
+#define __PPAGE__
+#endif
+/* Compile with option -DDG128 to activate this code */
+#elif defined DG128 /* HC912DG128 derivative has PPAGE register only at 0xFF */
+#define PPAGE_ADDR (0xFF+REGISTER_BASE)
+#ifndef __PPAGE__ /* may be set already by option -CPPPAGE */
+#define __PPAGE__
+#endif
+#elif defined(HC812A4)
+/* all setting default to A4 already */
+#endif
+
+
+#if !defined(__EPAGE__) && !defined(__PPAGE__) && !defined(__DPAGE__)
+/* as default use all page registers */
+#define __DPAGE__
+#define __EPAGE__
+#define __PPAGE__
+#endif
+
+/* modify the following defines to your memory configuration */
+
+#define EPAGE_LOW_BOUND   0x400u
+#define EPAGE_HIGH_BOUND  0x7ffu
+
+#define DPAGE_LOW_BOUND   0x7000u
+#define DPAGE_HIGH_BOUND  0x7fffu
+
+#define PPAGE_LOW_BOUND   (DPAGE_HIGH_BOUND+1)
+#define PPAGE_HIGH_BOUND  0xBFFFu
+
+#define REGISTER_BASE      0x0u
+#ifndef DPAGE_ADDR
+#define DPAGE_ADDR        (0x34u+REGISTER_BASE)
+#endif
+#ifndef EPAGE_ADDR
+#define EPAGE_ADDR        (0x36u+REGISTER_BASE)
+#endif
+#ifndef PPAGE_ADDR
+#define PPAGE_ADDR        (0x35u+REGISTER_BASE)
+#endif
+
+/*
+  The following parts about the defines are assumed in the code of _GET_PAGE_REG :
+  - the memory region controlled by DPAGE is above the area controlled by the EPAGE and
+    below the area controlled by the PPAGE.
+  - the lower bound of the PPAGE area is equal to be the higher bound of the DPAGE area + 1
+*/
+#if EPAGE_LOW_BOUND >= EPAGE_HIGH_BOUND || EPAGE_HIGH_BOUND >= DPAGE_LOW_BOUND || DPAGE_LOW_BOUND >= DPAGE_HIGH_BOUND || DPAGE_HIGH_BOUND >= PPAGE_LOW_BOUND || PPAGE_LOW_BOUND >= PPAGE_HIGH_BOUND
+#error /* please adapt _GET_PAGE_REG for this non default page configuration */
+#endif
+
+#if DPAGE_HIGH_BOUND+1 != PPAGE_LOW_BOUND
+#error /* please adapt _GET_PAGE_REG for this non default page configuration */
+#endif
+
+
+/* this module does either control if any access is in the bounds of the specified page or */
+/* ,if only one page is specified, just use this page. */
+/* This behavior is controlled by the define USE_SEVERAL_PAGES. */
+/* If !USE_SEVERAL_PAGES does increase the performance significantly */
+/* NOTE : When !USE_SEVERAL_PAGES, the page is also set for accesses outside of the area controlled */
+/*        by this single page. But this is should not cause problems because the page is restored to the old value before any other access could occur */
+
+#if !defined(__DPAGE__) && !defined(__EPAGE__) && !defined(__PPAGE__)
+/* no page at all is specified */
+/* only specifying the right pages will speed up these functions a lot */
+#define USE_SEVERAL_PAGES 1
+#elif defined(__DPAGE__) && defined(__EPAGE__) || defined(__DPAGE__) && defined(__PPAGE__) || defined(__EPAGE__) && defined(__PPAGE__)
+/* more than one page register is used */
+#define USE_SEVERAL_PAGES 1
+#else
+
+#define USE_SEVERAL_PAGES 0
+
+#if defined(__DPAGE__) /* check which pages are used  */
+#define PAGE_ADDR PPAGE_ADDR
+#elif defined(__EPAGE__)
+#define PAGE_ADDR EPAGE_ADDR
+#elif defined(__PPAGE__)
+#define PAGE_ADDR PPAGE_ADDR
+#else /* we do not know which page, decide it at runtime */
+#error /* must not happen */
+#endif
+
+#endif
+
+
+#if USE_SEVERAL_PAGES /* only needed for several pages support */
+/*--------------------------- _GET_PAGE_REG --------------------------------
+  Runtime routine to detect the right register depending on the 16 bit offset part
+  of an address.
+  This function is only used by the functions below.
+
+  Depending on the compiler options -Cp different versions of _GET_PAGE_REG are produced.
+
+  Arguments :
+  - Y : offset part of an address
+
+  Result :
+  if address Y is controlled by a page register :
+  - X : address of page register if Y is controlled by an page register
+  - Zero flag cleared
+  - all other registers remain unchanged
+
+  if address Y is not controlled by a page register :
+  - Zero flag is set
+  - all registers remain unchanged
+
+  --------------------------- _GET_PAGE_REG ----------------------------------*/
+
+#if defined(__DPAGE__)
+
+#ifdef __cplusplus
+extern "C"
+#endif
+#pragma NO_ENTRY
+#pragma NO_EXIT
+#pragma NO_FRAME
+
+static void NEAR _GET_PAGE_REG(void) { /*lint -esym(528, _GET_PAGE_REG) used in asm code */
+  __asm {
+L_DPAGE:
+        CPY     #DPAGE_LOW_BOUND  ;// test of lower bound of DPAGE
+#if defined(__EPAGE__)
+        BLO     L_EPAGE           ;// EPAGE accesses are possible
+#else
+        BLO     L_NOPAGE          ;// no paged memory below accesses
+#endif
+        CPY     #DPAGE_HIGH_BOUND ;// test of higher bound DPAGE/lower bound PPAGE
+#if defined(__PPAGE__)
+        BHI     L_PPAGE           ;// EPAGE accesses are possible
+#else
+        BHI     L_NOPAGE          ;// no paged memory above accesses
+#endif
+FOUND_DPAGE:
+        LDX     #DPAGE_ADDR       ;// load page register address and clear zero flag
+        RTS
+
+#if defined(__PPAGE__)
+L_PPAGE:
+        CPY     #PPAGE_HIGH_BOUND ;// test of higher bound of PPAGE
+        BHI     L_NOPAGE
+FOUND_PPAGE:
+        LDX     #PPAGE_ADDR       ;// load page register address and clear zero flag
+        RTS
+#endif
+
+#if defined(__EPAGE__)
+L_EPAGE:
+        CPY     #EPAGE_LOW_BOUND  ;// test of lower bound of EPAGE
+        BLO     L_NOPAGE
+        CPY     #EPAGE_HIGH_BOUND ;// test of higher bound of EPAGE
+        BHI     L_NOPAGE
+
+FOUND_EPAGE:
+        LDX     #EPAGE_ADDR       ;// load page register address and clear zero flag
+        RTS
+#endif
+
+L_NOPAGE:
+        ORCC    #0x04             ;// sets zero flag
+        RTS
+  }
+}
+
+#else /* !defined(__DPAGE__) */
+
+#if defined( __PPAGE__ )
+
+#ifdef __cplusplus
+extern "C"
+#endif
+#pragma NO_ENTRY
+#pragma NO_EXIT
+#pragma NO_FRAME
+
+static void NEAR _GET_PAGE_REG(void) {	/*lint -esym(528, _GET_PAGE_REG) used in asm code */
+  __asm {
+L_PPAGE:
+        CPY     #PPAGE_LOW_BOUND  ;// test of lower bound of PPAGE
+#if defined( __EPAGE__ )
+        BLO     L_EPAGE
+#else
+        BLO     L_NOPAGE          ;// no paged memory below
+#endif
+        CPY     #PPAGE_HIGH_BOUND ;// test of higher bound PPAGE
+        BHI     L_NOPAGE
+FOUND_PPAGE:
+        LDX     #PPAGE_ADDR       ;// load page register address and clear zero flag
+        RTS
+#if defined( __EPAGE__ )
+L_EPAGE:
+        CPY     #EPAGE_LOW_BOUND  ;// test of lower bound of EPAGE
+        BLO     L_NOPAGE
+        CPY     #EPAGE_HIGH_BOUND ;// test of higher bound of EPAGE
+        BHI     L_NOPAGE
+FOUND_EPAGE:
+        LDX     #EPAGE_ADDR       ;// load page register address and clear zero flag
+        RTS
+#endif
+
+L_NOPAGE:                         ;// not in any allowed page area
+                                  ;// its a far access to a non paged variable
+        ORCC #0x04                ;// sets zero flag
+        RTS
+  }
+}
+
+#else /* !defined(__DPAGE__ ) && !defined( __PPAGE__) */
+#if defined(__EPAGE__)
+
+#ifdef __cplusplus
+extern "C"
+#endif
+#pragma NO_ENTRY
+#pragma NO_EXIT
+#pragma NO_FRAME
+
+static void NEAR _GET_PAGE_REG(void) { /*lint -esym(528, _GET_PAGE_REG) used in asm code */
+  __asm {
+L_EPAGE:
+        CPY     #EPAGE_LOW_BOUND  ;// test of lower bound of EPAGE
+        BLO     L_NOPAGE
+        CPY     #EPAGE_HIGH_BOUND ;// test of higher bound of EPAGE
+        BHI     L_NOPAGE
+FOUND_EPAGE:
+        LDX     #EPAGE_ADDR       ;// load page register address and clear zero flag
+        RTS
+
+L_NOPAGE:                         ;// not in any allowed page area
+                                  ;// its a far access to a non paged variable
+        ORCC    #0x04             ;// sets zero flag
+        RTS
+  }
+}
+
+#endif /*  defined(__EPAGE__) */
+#endif /*  defined(__PPAGE__) */
+#endif /*  defined(__DPAGE__) */
+
+#endif /* USE_SEVERAL_PAGES */
+
+/*--------------------------- _SET_PAGE --------------------------------
+  Runtime routine to set the right page register. This routine is used if the compiler
+  does not know the right page register, i.e. if the option -Cp is used for more than
+  one page register or if the runtime option is used for one of the -Cp options.
+
+  Arguments :
+  - offset part of an address in the Y register
+  - page part of an address in the B register
+
+  Result :
+  - page part written into the correct page register.
+  - the old page register content is destroyed
+  - all processor registers remains unchanged
+  --------------------------- _SET_PAGE ----------------------------------*/
+
+#ifdef __cplusplus
+extern "C"
+#endif
+#pragma NO_ENTRY
+#pragma NO_EXIT
+#pragma NO_FRAME
+
+void NEAR _SET_PAGE(void) {
+#if USE_SEVERAL_PAGES
+  __asm {
+        PSHX                      ;// save X register
+        __PIC_JSR(_GET_PAGE_REG)
+        BEQ     L_NOPAGE
+        STAB    0,X               ;// set page register
+L_NOPAGE:
+        PULX                      ;// restore X register
+        RTS
+  }
+#else /* USE_SEVERAL_PAGES */
+  __asm {
+        STAB    PAGE_ADDR         ;// set page register
+        RTS
+  }
+#endif /* USE_SEVERAL_PAGES */
+}
+
+/*--------------------------- _LOAD_FAR_8 --------------------------------
+  This runtime routine is used to access paged memory via a runtime function.
+  It may also be used if the compiler option -Cp is not used with the runtime argument.
+
+  Arguments :
+  - offset part of an address in the Y register
+  - page part of an address in the B register
+
+  Result :
+  - value to be read in the B register
+  - all other registers remains unchanged
+  - all page register still contain the same value
+  --------------------------- _LOAD_FAR_8 ----------------------------------*/
+
+#ifdef __cplusplus
+extern "C"
+#endif
+#pragma NO_ENTRY
+#pragma NO_EXIT
+#pragma NO_FRAME
+
+void NEAR _LOAD_FAR_8(void) {
+#if USE_SEVERAL_PAGES
+  __asm {
+        PSHX                      ;// save X register
+        __PIC_JSR(_GET_PAGE_REG)
+        BEQ     L_NOPAGE
+        PSHA                      ;// save A register
+        LDAA    0,X               ;// save page register
+        STAB    0,X               ;// set page register
+        LDAB    0,Y               ;// actual load, overwrites page
+        STAA    0,X               ;// restore page register
+        PULA                      ;// restore A register
+        PULX                      ;// restore X register
+        RTS
+L_NOPAGE:
+        LDAB    0,Y               ;// actual load, overwrites page
+        PULX                      ;// restore X register
+        RTS
+  }
+#else /* USE_SEVERAL_PAGES */
+  __asm {
+        PSHA                      ;// save A register
+        LDAA    PAGE_ADDR         ;// save page register
+        STAB    PAGE_ADDR         ;// set page register
+        LDAB    0,Y               ;// actual load, overwrites page
+        STAA    PAGE_ADDR         ;// restore page register
+        PULA                      ;// restore A register
+        RTS
+  }
+#endif /* USE_SEVERAL_PAGES */
+}
+
+/*--------------------------- _LOAD_FAR_16 --------------------------------
+  This runtime routine is used to access paged memory via a runtime function.
+  It may also be used if the compiler  option -Cp is not used with the runtime argument.
+
+  Arguments :
+  - offset part of an address in the Y register
+  - page part of an address in the B register
+
+  Result :
+  - value to be read in the Y register
+  - all other registers remains unchanged
+  - all page register still contain the same value
+  --------------------------- _LOAD_FAR_16 ----------------------------------*/
+
+#ifdef __cplusplus
+extern "C"
+#endif
+#pragma NO_ENTRY
+#pragma NO_EXIT
+#pragma NO_FRAME
+
+void NEAR _LOAD_FAR_16(void) {
+#if USE_SEVERAL_PAGES
+  __asm {
+        PSHX                      ;// save X register
+        __PIC_JSR(_GET_PAGE_REG)
+        BEQ     L_NOPAGE
+        PSHA                      ;// save A register
+        LDAA    0,X               ;// save page register
+        STAB    0,X               ;// set page register
+        LDY     0,Y               ;// actual load, overwrites address
+        STAA    0,X               ;// restore page register
+        PULA                      ;// restore A register
+        PULX                      ;// restore X register
+        RTS
+L_NOPAGE:
+        LDY     0,Y               ;// actual load, overwrites address
+        PULX                      ;// restore X register
+        RTS
+  }
+#else /* USE_SEVERAL_PAGES */
+  __asm {
+        PSHA                      ;// save A register
+        LDAA    PAGE_ADDR         ;// save page register
+        STAB    PAGE_ADDR         ;// set page register
+        LDY     0,Y               ;// actual load, overwrites address
+        STAA    PAGE_ADDR         ;// restore page register
+        PULA                      ;// restore A register
+        RTS
+  }
+#endif /* USE_SEVERAL_PAGES */
+}
+/*--------------------------- _LOAD_FAR_24 --------------------------------
+  This runtime routine is used to access paged memory via a runtime function.
+  It may also be used if the compiler  option -Cp is not used with the runtime argument.
+
+  Arguments :
+  - offset part of an address in the Y register
+  - page part of an address in the B register
+
+  Result :
+  - value to be read in the Y:B registers
+  - all other registers remains unchanged
+  - all page register still contain the same value
+  --------------------------- _LOAD_FAR_24 ----------------------------------*/
+
+#ifdef __cplusplus
+extern "C"
+#endif
+#pragma NO_ENTRY
+#pragma NO_EXIT
+#pragma NO_FRAME
+
+void NEAR _LOAD_FAR_24(void) {
+#if USE_SEVERAL_PAGES
+  __asm {
+        PSHX                      ;// save X register
+        __PIC_JSR(_GET_PAGE_REG)
+        BEQ     L_NOPAGE
+        PSHA                      ;// save A register
+        LDAA    0,X               ;// save page register
+        STAB    0,X               ;// set page register
+        LDAB    0,Y               ;// actual load, overwrites page of address
+        LDY     1,Y               ;// actual load, overwrites offset of address
+        STAA    0,X               ;// restore page register
+        PULA                      ;// restore A register
+        PULX                      ;// restore X register
+        RTS
+L_NOPAGE:
+        LDAB    0,Y               ;// actual load, overwrites page of address
+        LDY     1,Y               ;// actual load, overwrites offset of address
+        PULX                      ;// restore X register
+        RTS
+  }
+#else /* USE_SEVERAL_PAGES */
+  __asm {
+        PSHA                      ;// save A register
+        LDAA    PAGE_ADDR         ;// save page register
+        STAB    PAGE_ADDR         ;// set page register
+        LDAB    0,Y               ;// actual load, overwrites page of address
+        LDY     1,Y               ;// actual load, overwrites offset of address
+        STAA    PAGE_ADDR         ;// restore page register
+        PULA                      ;// restore A register
+        RTS
+  }
+#endif /* USE_SEVERAL_PAGES */
+
+}
+
+/*--------------------------- _LOAD_FAR_32 --------------------------------
+  This runtime routine is used to access paged memory via a runtime function.
+  It may also be used if the compiler  option -Cp is not used with the runtime argument.
+
+  Arguments :
+  - offset part of an address in the Y register
+  - page part of an address in the B register
+
+  Result :
+  - low 16 bit of value to be read in the D registers
+  - high 16 bit of value to be read in the Y registers
+  - all other registers remains unchanged
+  - all page register still contain the same value
+  --------------------------- _LOAD_FAR_32 ----------------------------------*/
+
+#ifdef __cplusplus
+extern "C"
+#endif
+#pragma NO_ENTRY
+#pragma NO_EXIT
+#pragma NO_FRAME
+
+void NEAR _LOAD_FAR_32(void) {
+#if USE_SEVERAL_PAGES
+  __asm {
+        PSHX                      ;// save X register
+        __PIC_JSR(_GET_PAGE_REG)
+        BEQ     L_NOPAGE
+        LDAA    0,X               ;// save page register
+        PSHA                      ;// put it onto the stack
+        STAB    0,X               ;// set page register
+        LDD     2,Y               ;// actual load, low word
+        LDY     0,Y               ;// actual load, high word
+        MOVB    1,SP+,0,X         ;// restore page register
+        PULX                      ;// restore X register
+        RTS
+L_NOPAGE:
+        LDD     2,Y               ;// actual load, low word
+        LDY     0,Y               ;// actual load, high word
+        PULX                      ;// restore X register
+        RTS
+  }
+#else /* USE_SEVERAL_PAGES */
+  __asm {
+        LDAA    PAGE_ADDR         ;// save page register
+        PSHA                      ;// put it onto the stack
+        STAB    PAGE_ADDR         ;// set page register
+        LDD     2,Y               ;// actual load, low word
+        LDY     0,Y               ;// actual load, high word
+        MOVB    1,SP+,PAGE_ADDR   ;// restore page register
+        RTS
+  }
+#endif /* USE_SEVERAL_PAGES */
+}
+
+/*--------------------------- _STORE_FAR_8 --------------------------------
+  This runtime routine is used to access paged memory via a runtime function.
+  It may also be used if the compiler  option -Cp is not used with the runtime argument.
+
+  Arguments :
+  - offset part of an address in the Y register
+  - page part of an address in the B register
+  - value to be stored in the B register
+
+  Result :
+  - value stored at the address
+  - all registers remains unchanged
+  - all page register still contain the same value
+  --------------------------- _STORE_FAR_8 ----------------------------------*/
+
+#ifdef __cplusplus
+extern "C"
+#endif
+#pragma NO_ENTRY
+#pragma NO_EXIT
+#pragma NO_FRAME
+
+void NEAR _STORE_FAR_8(void) {
+#if USE_SEVERAL_PAGES
+  __asm {
+        PSHX                      ;// save X register
+        __PIC_JSR(_GET_PAGE_REG)
+        BEQ     L_NOPAGE
+        PSHB                      ;// save B register
+        LDAB    0,X               ;// save page register
+        MOVB    0,SP, 0,X         ;// set page register
+        STAA    0,Y               ;// store the value passed in A
+        STAB    0,X               ;// restore page register
+        PULB                      ;// restore B register
+        PULX                      ;// restore X register
+        RTS
+L_NOPAGE:
+        STAA    0,Y               ;// store the value passed in A
+        PULX                      ;// restore X register
+        RTS
+  }
+#else /* USE_SEVERAL_PAGES */
+  __asm {
+        PSHB                      ;// save A register
+        LDAB    PAGE_ADDR         ;// save page register
+        MOVB    0,SP,PAGE_ADDR    ;// set page register
+        STAA    0,Y               ;// store the value passed in A
+        STAB    PAGE_ADDR         ;// restore page register
+        PULB                      ;// restore B register
+        RTS
+  }
+#endif /* USE_SEVERAL_PAGES */
+}
+
+/*--------------------------- _STORE_FAR_16 --------------------------------
+  This runtime routine is used to access paged memory via a runtime function.
+  It may also be used if the compiler  option -Cp is not used with the runtime argument.
+
+  Arguments :
+  - offset part of an address in the Y register
+  - page part of an address in the B register
+  - value to be stored in the X register
+
+  Result :
+  - value stored at the address
+  - all registers remains unchanged
+  - all page register still contain the same value
+  --------------------------- _STORE_FAR_16 ----------------------------------*/
+
+#ifdef __cplusplus
+extern "C"
+#endif
+#pragma NO_ENTRY
+#pragma NO_EXIT
+#pragma NO_FRAME
+
+void NEAR _STORE_FAR_16(void) {
+#if USE_SEVERAL_PAGES
+  __asm {
+        PSHX                      ;// save X register
+        __PIC_JSR(_GET_PAGE_REG)
+        BEQ     L_NOPAGE
+
+        PSHA
+        LDAA    0,X               ;// save page register
+        STAB    0,X               ;// set page register
+        MOVW    1,SP,0,Y          ;// store the value passed in X
+        STAA    0,X               ;// restore page register
+        PULA                      ;// restore A register
+        PULX                      ;// restore X register
+        RTS
+
+L_NOPAGE:
+        STX 0,Y                   ;// store the value passed in X
+        PULX                      ;// restore X register
+        RTS
+  }
+#else /* USE_SEVERAL_PAGES */
+  __asm {
+        PSHA                      ;// save A register
+        LDAA    PAGE_ADDR         ;// save page register
+        STAB    PAGE_ADDR         ;// set page register
+        STX     0,Y               ;// store the value passed in X
+        STAA    PAGE_ADDR         ;// restore page register
+        PULA                      ;// restore A register
+        RTS
+  }
+#endif /* USE_SEVERAL_PAGES */
+}
+/*--------------------------- _STORE_FAR_24 --------------------------------
+  This runtime routine is used to access paged memory via a runtime function.
+  It may also be used if the compiler  option -Cp is not used with the runtime argument.
+
+  Arguments :
+  - offset part of an address in the Y register
+  - page part of an address in the B register
+  - value to be stored in the X:A registers (X : low 16 bit, A : high 8 bit)
+
+  Result :
+  - value stored at the address
+  - all registers remains unchanged
+  - all page register still contain the same value
+  --------------------------- _STORE_FAR_24 ----------------------------------*/
+
+#ifdef __cplusplus
+extern "C"
+#endif
+#pragma NO_ENTRY
+#pragma NO_EXIT
+#pragma NO_FRAME
+
+void NEAR _STORE_FAR_24(void) {
+#if USE_SEVERAL_PAGES
+  __asm {
+        PSHX                      ;// save X register
+        __PIC_JSR(_GET_PAGE_REG)
+        BEQ     L_NOPAGE
+
+        PSHA
+        LDAA    0,X               ;// save page register
+        STAB    0,X               ;// set page register
+        MOVW    1,SP, 1,Y         ;// store the value passed in X
+        MOVB    0,SP, 0,Y         ;// store the value passed in A
+        STAA    0,X               ;// restore page register
+        PULA                      ;// restore A register
+        PULX                      ;// restore X register
+        RTS
+
+L_NOPAGE:
+        STX     1,Y               ;// store the value passed in X
+        STAA    0,Y               ;// store the value passed in X
+        PULX                      ;// restore X register
+        RTS
+  }
+#else /* USE_SEVERAL_PAGES */
+  __asm {
+        PSHA                      ;// save A register
+        LDAA    PAGE_ADDR         ;// save page register
+        STAB    PAGE_ADDR         ;// set page register
+        MOVB    0,SP, 0,Y         ;// store the value passed in A
+        STX     1,Y               ;// store the value passed in X
+        STAA    PAGE_ADDR         ;// restore page register
+        PULA                      ;// restore A register
+        RTS
+  }
+#endif /* USE_SEVERAL_PAGES */
+}
+/*--------------------------- _STORE_FAR_32 --------------------------------
+  This runtime routine is used to access paged memory via a runtime function.
+  It may also be used if the compiler  option -Cp is not used with the runtime argument.
+
+  Arguments :
+  - offset part of an address in the Y register
+  - page part of an address is on the stack at 3,SP (just below the return address)
+  - value to be stored in the X:D registers (D : low 16 bit, X : high 16 bit)
+
+  Result :
+  - value stored at the address
+  - all registers remains unchanged
+  - the page part is removed from the stack
+  - all page register still contain the same value
+  --------------------------- _STORE_FAR_32 ----------------------------------*/
+
+#ifdef __cplusplus
+extern "C"
+#endif
+#pragma NO_ENTRY
+#pragma NO_EXIT
+#pragma NO_FRAME
+
+void NEAR _STORE_FAR_32(void) {
+#if USE_SEVERAL_PAGES
+  __asm {
+        PSHX                      ;// save X register
+        __PIC_JSR(_GET_PAGE_REG)
+        BEQ     L_NOPAGE
+
+        PSHD
+        LDAA    0,X               ;// save page register
+        MOVB    6,SP, 0,X         ;// set page register
+        MOVW    2,SP, 0,Y         ;// store the value passed in X (high word)
+        MOVW    0,SP, 2,Y         ;// store the value passed in D (low word)
+        STAA    0,X               ;// restore page register
+        PULD                      ;// restore A register
+        BRA     done
+
+L_NOPAGE:
+        MOVW    0,SP, 0,Y         ;// store the value passed in X (high word)
+        STD           2,Y         ;// store the value passed in D (low word)
+done:
+        PULX                      ;// restore X register
+        MOVW    0,SP, 1,+SP       ;// move return address
+        RTS
+  }
+#else /* USE_SEVERAL_PAGES */
+  __asm {
+        PSHD                      ;// save D register
+        LDAA    PAGE_ADDR         ;// save page register
+        LDAB    4,SP              ;// load page part of address
+        STAB    PAGE_ADDR         ;// set page register
+        STX     0,Y               ;// store the value passed in X
+        MOVW    0,SP, 2,Y         ;// store the value passed in D (low word)
+        STAA    PAGE_ADDR         ;// restore page register
+        PULD                      ;// restore D register
+        MOVW    0,SP, 1,+SP       ;// move return address
+        RTS
+  }
+#endif /* USE_SEVERAL_PAGES */
+}
+
+/*--------------------------- _FAR_COPY_RC --------------------------------
+  This runtime routine is used to access paged memory via a runtime function.
+  It may also be used if the compiler  option -Cp is not used with the runtime argument.
+
+  Arguments :
+  - offset part of the source int the X register
+  - page part of the source in the A register
+  - offset part of the dest int the Y register
+  - page part of the dest in the B register
+  - number of bytes to be copied is defined by the next 2 bytes after the return address.
+
+  Result :
+  - memory area copied
+  - no registers are saved, i.e. all registers may be destroyed
+  - all page register still contain the same value as before the call
+  - the function returns after the constant defining the number of bytes to be copied
+
+
+  stack-structure at the loop-label:
+     0,SP : destination offset
+     2,SP : source page
+     3,SP : destination page
+     4,SP : source offset
+     6,SP : points to length to be copied. This function returns after the size
+
+  A usual call to this function looks like:
+
+  struct Huge src, dest;
+    ; ...
+    LDX  #src
+    LDAA #PAGE(src)
+    LDY  #dest
+    LDAB #PAGE(dest)
+    JSR  _FAR_COPY_RC
+    DC.W sizeof(struct Huge)
+    ; ...
+
+  --------------------------- _FAR_COPY_RC ----------------------------------*/
+
+#ifdef __cplusplus
+extern "C"
+#endif
+#pragma NO_ENTRY
+#pragma NO_EXIT
+#pragma NO_FRAME
+
+void NEAR _FAR_COPY_RC(void) {
+#if USE_SEVERAL_PAGES
+  __asm {
+        DEX                       ;// source addr-=1, because loop counter ends at 1
+        PSHX                      ;// save source offset
+        PSHD                      ;// save both pages
+        DEY                       ;// destination addr-=1, because loop counter ends at 1
+        PSHY                      ;// save destination offset
+        LDY     6,SP              ;// Load Return address
+        LDX     2,Y+              ;// Load Size to copy
+        STY     6,SP              ;// Store adjusted return address
+loop:
+        LDD     4,SP              ;// load source offset
+        LEAY    D,X               ;// calculate actual source address
+        LDAB    2,SP              ;// load source page
+        __PIC_JSR(_LOAD_FAR_8)    ;// load 1 source byte
+        PSHB                      ;// save value
+        LDD     0+1,SP            ;// load destination offset
+        LEAY    D,X               ;// calculate actual destination address
+        PULA                      ;// restore value
+        LDAB    3,SP              ;// load destination page
+        __PIC_JSR(_STORE_FAR_8)   ;// store one byte
+        DEX
+        BNE     loop
+        LEAS    6,SP              ;// release stack
+        _SRET                     ;// debug info only: This is the last instr of a function with a special return
+        RTS                       ;// return
+  }
+#else
+  __asm {
+        PSHD                      ;// store page registers
+        TFR     X,D
+        PSHY                      ;// temporary space
+        LDY     4,SP              ;// load return address
+        ADDD    2,Y+              ;// calculate source end address. Increment return address
+        STY     4,SP
+        PULY
+        PSHD                      ;// store src end address
+        LDAB    2,SP              ;// reload source page
+        LDAA    PAGE_ADDR         ;// save page register
+        PSHA
+loop:
+        STAB    PAGE_ADDR         ;// set source page
+        LDAA    1,X+              ;// load value
+        MOVB    4,SP, PAGE_ADDR   ;// set destination page
+        STAA    1,Y+
+        CPX     1,SP
+        BNE     loop
+
+        LDAA    5,SP+             ;// restore old page value and release stack
+        STAA    PAGE_ADDR         ;// store it into page register
+        _SRET                     ;// debug info only: This is the last instr of a function with a special return
+        RTS
+  }
+#endif
+}
+
+/*--------------------------- _FAR_COPY --------------------------------
+
+  The _FAR_COPY runtime routine was used to copied large memory blocks in previous compiler releases.
+  However this release now does use _FAR_COPY_RC instead. The only difference is how the size of 
+  the area to be copied is passed into the function. For _FAR_COPY the size is passed on the stack just
+  above the return address. _FAR_COPY_RC does expect the return address just after the JSR _FAR_COPY_RC call
+  in the code of the caller. This allows for denser code calling _FAR_COPY_RC but does also need a slightly
+  larger runtime routine and it is slightly slower.
+  The _FAR_COPY routine is here now mainly for compatibility with previous releases. 
+  The current compiler does not use it. 
+  
+--------------------------- _FAR_COPY ----------------------------------*/
+
+#ifdef __cplusplus
+extern "C"
+#endif
+#pragma NO_ENTRY
+#pragma NO_EXIT
+#pragma NO_FRAME
+
+void NEAR _FAR_COPY(void) {
+#if USE_SEVERAL_PAGES
+  __asm {
+        DEX                       ;// source addr-=1, because loop counter ends at 1
+        PSHX                      ;// save source offset
+        PSHD                      ;// save both pages
+        DEY                       ;// destination addr-=1, because loop counter ends at 1
+        PSHY                      ;// save destination offset
+        LDX     8,SP              ;// load counter, assuming counter > 0
+
+loop:
+        LDD     4,SP              ;// load source offset
+        LEAY    D,X               ;// calculate actual source address
+        LDAB    2,SP              ;// load source page
+        __PIC_JSR(_LOAD_FAR_8)    ;// load 1 source byte
+        PSHB                      ;// save value
+        LDD     0+1,SP            ;// load destination offset
+        LEAY    D,X               ;// calculate actual destination address
+        PULA                      ;// restore value
+        LDAB    3,SP              ;// load destination page
+        __PIC_JSR(_STORE_FAR_8)   ;// store one byte
+        DEX
+        BNE     loop
+        LDX     6,SP              ;// load return address
+        LEAS    10,SP             ;// release stack
+        JMP     0,X               ;// return
+  }
+#else
+  __asm {
+        PSHD                      ;// store page registers
+        TFR     X,D
+        ADDD    4,SP              ;// calculate source end address
+        STD     4,SP
+        PULB                      ;// reload source page
+        LDAA    PAGE_ADDR         ;// save page register
+        PSHA
+loop:
+        STAB    PAGE_ADDR         ;// set source page
+        LDAA    1,X+              ;// load value
+        MOVB    1,SP, PAGE_ADDR   ;// set destination page
+        STAA    1,Y+
+        CPX     4,SP
+        BNE     loop
+
+        LDAA    2,SP+             ;// restore old page value and release stack
+        STAA    PAGE_ADDR         ;// store it into page register
+        LDX     4,SP+             ;// release stack and load return address
+        JMP     0,X               ;// return
+  }
+#endif
+}
+
+#else  /* __HCS12X__  */
+
+/*
+  The HCS12X knows two different kind of addresses:
+    - Logical addresses. E.g.
+       MOVB #page(var),RPAGE
+       INC var
+
+    - Global addresses E.g.
+       MOVB #page(var),GPAGE
+       GLDAA var
+       INCA
+       GSTAA var
+
+  Global addresses are used with G-Load's and G-Store's, logical addresses are used for all the other instructions
+  and occasions. As HC12's or HCS12's do not have the G-Load and G-Store instructions,
+  global addresses are not used with these processor families.
+  They are only used with HCS12X chips (and maybe future ones deriving from a HCS12X).
+
+  Logical and Global addresses can point to the same object, however the global and logical address of an object
+  are different for most objects (actually for all except the registers from 0 to 0x7FF).
+  Therefore the compiler needs to transform in between them.
+
+  HCS12X Pointer types:
+
+    The following are logical addresses:
+    - all 16 bit pointers
+       - "char* __near": always.
+       - "char *" in the small and banked memory model
+    - 24 bit dpage, epage, ppage or rpage pointers (*1) (note: the first HCS12X compilers may not support these pointer types)
+       - "char *__dpage": Note this type only exists for
+                          orthogonality with the HC12 A4 chip which has a DPAGE reg.
+                          It does not apply to the HCS12X.
+       - "char *__epage": 24 bit pointer using the EPAGE register
+       - "char *__ppage": 24 bit pointer using the PPAGE register.
+                          As the PPAGE is also used for BANKED code,
+                          using this pointer type is only legal from non banked code.
+       - "char *__rpage": 24 bit pointer using the RPAGE register
+
+
+    The following are global addresses:
+       "char*": in the large memory model (only HCS12X)
+       "char* __far": always for HCS12X.
+
+   (*1): For the HC12 and HCS12 "char* __far" and "char*" in the large memory model are also logical.
+
+   Some notes for the HC12/HCS12 programmers.
+
+   The address of a far object for a HC12 and for a HCS12X is different, even if they are at the same place in the memory map.
+   For the HC12, a far address is using the logical addresses, for the HCS12X however, far addresses are using global addresses.
+   This does cause troubles for the unaware!
+   
+   The conversion routines implemented in this file support the special HCS12XE RAM mapping (when RAMHM is set).
+   To enable this mapping compile this file with the "-MapRAM" compiler option.
+
+  HCS12X Logical Memory map
+
+    Logical Addresses           Used for                shadowed at           page register     Global Address
+
+    0x000000 .. 0x0007FF        Peripheral Registers                          Not Paged         0x000000
+    0x??0800 .. 0x??0BFF        Paged EEPROM                                  EPAGE (@0x17)     0x100000+EPAGE*0x0400
+    0x000C00 .. 0x000FFF        Non Paged EEPROM        0xFF0800..0xFF0FFF    Not Paged         0x13FC00
+    0x??1000 .. 0x??1FFF        Paged RAM                                     RPAGE (@0x16)     0x000000+RPAGE*0x1000
+    0x002000 .. 0x003FFF        Non Paged RAM           0xFE1000..0xFF1FFF    Not Paged         0x0FE000
+    0x004000 .. 0x007FFF        Non Paged FLASH         0xFC8000..0xFCBFFF    Not Paged         0x7F4000
+    0x??8000 .. 0x00BFFF        Paged FLASH                                   PPAGE (@0x30)     0x400000+PPAGE*0x4000
+    0x00C000 .. 0x00FFFF        Non Paged FLASH         0xFF8000..0xFFBFFF    Not Paged         0x7FC000
+
+    NA: Not Applicable
+
+  HCS12X Global Memory map
+
+    Global Addresses            Used for                Logical mapped at
+
+    0x000000 .. 0x0007FF        Peripheral Registers    0x000000 .. 0x0007FF
+    0x000800 .. 0x000FFF        DMA registers           Not mapped
+    0x001000 .. 0x0FFFFF        RAM                     0x??1000 .. 0x??1FFF
+    0x0FE000 .. 0x0FFFFF        RAM, Log non paged      0x002000 .. 0x003FFF
+    0x100000 .. 0x13FFFF        EEPROM                  0x??0800 .. 0x??0BFF
+    0x13FC00 .. 0x13FFFF        EEPROM  non paged       0x000C00 .. 0x000FFF
+    0x140000 .. 0x3FFFFF        External Space          Not mapped
+    0x400000 .. 0x7FFFFF        FLASH                   0x??8000 .. 0x??BFFF
+    0x7F4000 .. 0x7F7FFF        FLASH, Log non paged    0x004000 .. 0x007FFF
+    0x7FC000 .. 0x7FFFFF        FLASH, Log non paged    0x00C000 .. 0x00FFFF
+
+  HCS12XE Logical Memory map (with RAMHM set) 
+
+    Logical Addresses           Used for                shadowed at           page register     Global Address
+
+    0x000000 .. 0x0007FF        Peripheral Registers                          Not Paged         0x000000
+    0x??0800 .. 0x??0BFF        Paged EEPROM                                  EPAGE             0x100000+EPAGE*0x0400
+    0x000C00 .. 0x000FFF        Non Paged EEPROM        0xFF0800..0xFF0FFF    Not Paged         0x13FC00
+    0x??1000 .. 0x??1FFF        Paged RAM                                     RPAGE             0x000000+RPAGE*0x1000
+    0x002000 .. 0x003FFF        Non Paged RAM           0xFA1000..0xFB1FFF    Not Paged         0x0FA000
+    0x004000 .. 0x007FFF        Non Paged RAM           0xFC1000..0xFF1FFF    Not Paged         0x0FC000
+    0x??8000 .. 0x00BFFF        Paged FLASH                                   PPAGE             0x400000+PPAGE*0x4000
+    0x00C000 .. 0x00FFFF        Non Paged FLASH         0xFF8000..0xFFBFFF    Not Paged         0x7FC000
+
+    NA: Not Applicable
+
+  HCS12X Global Memory map (with RAMHM set) 
+
+    Global Addresses            Used for                Logical mapped at
+
+    0x000000 .. 0x0007FF        Peripheral Registers    0x000000 .. 0x0007FF
+    0x000800 .. 0x000FFF        DMA registers           Not mapped
+    0x001000 .. 0x0FFFFF        RAM                     0x??1000 .. 0x??1FFF
+    0x0FA000 .. 0x0FFFFF        RAM, Log non paged      0x002000 .. 0x007FFF
+    0x100000 .. 0x13FFFF        EEPROM                  0x??0800 .. 0x??0BFF
+    0x13FC00 .. 0x13FFFF        EEPROM  non paged       0x000C00 .. 0x000FFF
+    0x140000 .. 0x3FFFFF        External Space          Not mapped
+    0x400000 .. 0x7FFFFF        FLASH                   0x??8000 .. 0x??BFFF
+    0x7F4000 .. 0x7F7FFF        FLASH, Log non paged    Not mapped
+    0x7FC000 .. 0x7FFFFF        FLASH, Log non paged    0x00C000 .. 0x00FFFF
+
+
+  How to read this table:
+    For logical addresses, the lower 16 bits of the address do determine in which area the address is,
+    if this address is paged, then this entry also controls and which of the EPAGE, PPAGE or RPAGE
+    page register is controlling the bits 16 to 23 of the address.
+    For global addresses, the bits 16 to 23 have to be in the GPAGE register and the lower 16 bits
+    have to be used with the special G load or store instructions (e.g. GLDAA).
+    As example the logical address 0x123456 is invalid. Because its lower bits 0x3456 are in a
+    non paged area, so the page 0x12 does not exist.
+    The address 0xFE1020 however does exist. To access it, the RPAGE has to contain 0xFE and the
+    offset 0x1020 has to be used.
+
+      ORG $7000
+        MOVB #0xFE, 0x16 ; RPAGE
+        LDAA 0x1020      ; reads at the logical address 0xFE1020
+
+    Because the last two RAM pages are also accessible directly from 0x2000 to 0x3FFF, the
+    following shorter code does read the same memory location:
+
+      ORG $7000
+        LDAA 0x2020      ; reads at the logical address 0x2020
+                         ;   which maps to the same memory as 0xFE1020
+
+    This memory location also has a global address. For logical 0xFE1020 the global address is 0x0FE020.
+    So the following code does once more access the same memory location:
+
+      ORG $7000
+        MOVB #0x0F, 0x10 ; GPAGE
+        GLDAA 0xE020     ; reads at the global address 0x0FE020
+                         ;   which maps to the same memory as the logical addr. 0xFE1020
+
+    Therefore every memory location for the HCS12X has up to 3 different addresses.
+    Up to two logical and one global.
+    Notes.
+      - Not every address has a logical equivalent. The external space is only available in the global address space.
+
+      - The PPAGE must only be set if the code is outside of the 0x8000 to 0xBFFF range.
+        If not, the next code fetch will be from the new wrong PPAGE value.
+
+      - Inside of the paged area, the highest pages are allocated first. So all HCS12X's do have the FF pages
+        (if they have this memory type at all).
+
+      - For RPAGE, the value 0 is illegal. Otherwise the global addresses would overlap with the registers.
+
+*/
+
+#if __OPTION_ACTIVE__("-MapRAM")
+#define __HCS12XE_RAMHM_SET__
+#endif
+
+/*--------------------------- pointer conversion operations -------------------------------*/
+
+/*--------------------------- _CONV_GLOBAL_TO_LOGICAL --------------------------------
+  Convert 24 bit logical to 24 bit global pointer
+    ("char*__far" to "char*__gpage")
+
+  Arguments :
+  - B : page part of global address
+  - X : 16 offset part of global address
+
+  Postcondition :
+  - B == page of returned logical address
+  - X == offset of returned logical address
+  - Y remains unchanged
+  - A remains unchanged
+*/
+/*--------------------------- Convert 24 bit global to 24 bit logical pointer ----------------------------------*/
+
+/* B:X = Logical(B:X) */
+#ifdef __cplusplus
+extern "C"
+#endif
+
+#pragma NO_FRAME
+#pragma NO_ENTRY
+#pragma NO_EXIT
+
+void NEAR _CONV_GLOBAL_TO_LOGICAL(void) {
+  __asm {
+        CMPB    #0x40             ;// flash (0x400000..0x7FFFFF) or not?
+        BLO     Below400000
+// from 0x400000 to 0x7FFFFF
+        CMPB    #0x7F             ;// check for Unpaged areas 0x7FC000..0x7FFFFF and 0x7F4000..0x7F7FFF
+        BNE     PAGED_FLASH_AREA
+#ifndef __HCS12XE_RAMHM_SET__
+        BITX    #0x4000
+        BEQ     PAGED_FLASH_AREA
+#else
+        CPX    #0xC000
+        BLO     PAGED_FLASH_AREA
+#endif
+// from 0x7F4000 to 0x7F7FFF or 0x7FC000 to 0x7FFFFF
+                                  ;// Note: offset in X is already OK.
+        CLRB                      ;// logical page == 0
+        RTS
+PAGED_FLASH_AREA:                 ;// paged flash. Map to 0x8000..0xBFFF
+// from 0x400000 to 0x7F3FFF  or 0x7F8000 to 0x7FBFFF
+        LSLX                      ; // shift 24 bit address 2 bits to the left to get correct page in B
+        ROLB
+        LSLX
+        ROLB
+        LSRX                      ; // shift back to get offset from 0x8000 to 0xBFFF
+        SEC
+        RORX
+        RTS                       ;// done
+
+Below400000:
+// from 0x000000 to 0x3FFFFF
+#if 0 /* How should we handle mapping to External Space. There is no logical equivalent. This is an error case! */
+        CMPB    #0x14             ;// check if above 0x140000. If so, its in the external space
+        BLO     Below140000
+        ERROR   !!!!              ;// this mapping is not possible! What should we do?
+        RTS
+Below140000:
+// from 0x000000 to 0x13FFFF
+#endif
+        CMPB    #0x10             ;// if >= 0x100000 it's EEPROM
+        BLO     Below100000
+// from 0x100000 to 0x13FFFF (or 0x3FFFFF)
+        CMPB    #0x13             ;// check if its is in the non paged EEPROM area at 0x13FC00..0x13FFFF
+        BLO     Below13FC00
+        CPX     #0xFC00
+        BLO     Below13FC00
+// from 0x13FC00 to 0x13FFFF (or 0x3FFFFF)
+        LEAX    0x1000,X          ;// same as SUBX #0xF000 // map from 0xFC00 to 0x0C00
+        CLRB
+        RTS
+Below13FC00:
+// from 0x100000 to 0x13FBFF
+        PSHA
+        TFR     XH,A              ;// calculate logical page
+        EXG     A,B
+        LSRD
+        LSRD
+        PULA
+        ANDX    #0x03FF
+        LEAX    0x0800,X          ;// same as ORX  #0x0800
+        RTS
+
+Below100000:
+// from 0x000000 to 0x0FFFFF
+        TSTB
+        BNE     RAM_AREA
+        CPX     #0x1000
+        BLO     Below001000
+RAM_AREA:
+// from 0x001000 to 0x0FFFFF
+        CMPB    #0x0F
+        BNE     PagedRAM_AREA
+#ifndef __HCS12XE_RAMHM_SET__
+        CPX     #0xE000
+        BLO     PagedRAM_AREA
+// from 0x0FE000 to 0x0FFFFF
+        SUBX    #(0xE000-0x2000)  ;// map 0xE000 to 0x2000
+#else
+        CPX     #0xA000
+        BLO     PagedRAM_AREA
+// from 0x0FA000 to 0x0FFFFF
+        SUBX    #(0xA000-0x2000)  ;// map 0xA000 to 0x2000 
+#endif
+        CLRB                      ;// Page is 0
+        RTS
+PagedRAM_AREA:
+// from 0x001000 to 0x0FDFFF
+        PSHA
+        TFR     XH, A             ;// calculate logical page
+        EXG     A,B
+        LSRD
+        LSRD
+        LSRD
+        LSRD
+        PULA
+
+        ANDX    #0x0FFF
+        LEAX    0x1000,X          ;// same as ORX #0x1000
+        RTS
+
+Below001000:
+// from 0x000000 to 0x000FFF
+#if 0
+        CMPA    #0x08
+        BLO     Below000800
+// from 0x000800 to 0x000FFF
+    // ??? DMA Regs?
+        RTS
+Below000800:
+// from 0x000000 to 0x0007FF
+#endif
+        CLRB
+        RTS
+  }
+}
+
+/*--------------------------- _CONV_GLOBAL_TO_NEAR --------------------------------
+  Convert 24 bit global to 16 bit logical pointer
+    ("char*__far" to "char*")
+
+  Arguments :
+  - B : page part of global address
+  - X : 16 offset part of global address
+
+  Postcondition :
+  - B is undefined
+  - A remains unchanged
+  - X == offset of returned logical address
+  - Y remains unchanged
+*/
+/*--------------------------- Convert 24 bit global to 16 bit logical pointer ----------------------------------*/
+
+/* X = Logical(B:X) */
+
+#ifdef __cplusplus
+extern "C"
+#endif
+
+#define _REUSE_CONV_GLOBAL_TO_LOGICAL 1
+
+#pragma NO_FRAME
+#pragma NO_ENTRY
+#pragma NO_EXIT
+
+void NEAR _CONV_GLOBAL_TO_NEAR(void){
+#if _REUSE_CONV_GLOBAL_TO_LOGICAL  /* do we want an optimized version? */
+  __asm JMP _CONV_GLOBAL_TO_LOGICAL;  /* offset for NEAR is same as for LOGICAL. */
+#else
+  __asm {
+        CMPB    #0x40             ;// flash (0x400000..0x7FFFFF) or not?
+        BLO     Below400000
+// from 0x400000 to 0x7FFFFF
+#ifndef __HCS12XE_RAMHM_SET__
+        CMPB    #0x7F             ;// check for Unpaged areas 0x7FC000..0x7FFFFF and 0x7F4000..0x7F7FFF
+        BNE     PAGED_FLASH_AREA
+        CPX     #0x4000
+        BLO     PAGED_FLASH_AREA
+// from 0x7F4000 to 0x7FFFFF
+#else
+        CMPB    #0x7F             ;// check for Unpaged area 0x7FC000..0x7FFFFF
+        BNE     PAGED_FLASH_AREA
+        CPX     #0xC000           
+        BLO     PAGED_FLASH_AREA
+// from 0x7FC000 to 0x7FFFFF      
+#endif
+                                  ;// note non PAGED flash areas or paged area 0x7F8000..0x7FBFFF which are mapping all correctly
+        RTS
+PAGED_FLASH_AREA:                 ;// paged flash. Map to 0x8000..0xBFFF
+// from 0x400000 to 0x7F3FFF
+        ANDX    #0x3F00           ;// cut to 0.. 0x3FFF
+        LEAX    0x8000,X          ;// same as ORX  #0x8000     ;// move to 0x8000..0xBFFF
+        RTS                       ;// done
+
+Below400000:
+// from 0x000000 to 0x3FFFFF
+#if 0 /* How should we handle mapping to External Space. There is no logical equivalent. This is an error case! */
+        CMPB    #0x14             ;// check if above 0x140000. If so, its in the external space
+        BLO     Below140000
+        ERROR !!!!                ;// this mapping is not possible! What should we do?
+        RTS
+Below140000:
+// from 0x000000 to 0x13FFFF
+#endif
+        CMPB    #0x10             ;// if >= 0x100000 it's EEPROM
+        BLO     Below100000
+// from 0x100000 to 0x13FFFF (or 0x3FFFFF)
+        CMPB    #0x13             ;// check if its is in the non paged EEPROM area at 0x13FC00..0x13FFFF
+        BNE     Below13FC00
+        CPX     #0xFC00
+        BLO     Below13FC00
+// from 0x13FC00 to 0x13FFFF (or 0x3FFFFF)
+        SUBX    #0xF000           ;// map from 0xFC00 to 0x0C00
+        RTS
+Below13FC00:
+// from 0x100000 to 0x13FBFF
+        ANDX    #0x03FF
+        LEAX    0x800,X           ;// same as ORX  #0x0800
+        RTS
+
+Below100000:
+// from 0x000000 to 0x0FFFFF
+        TBNE    B,RAM_AREA
+        CPX     #0x1000
+        BLO     Below001000
+RAM_AREA:
+// from 0x001000 to 0x0FFFFF
+        CMPB    #0x0F
+        BNE     PagedRAM_AREA
+#ifndef __HCS12XE_RAMHM_SET__
+        CPX     #0xE000
+        BLO     PagedRAM_AREA
+// from 0x0FE000 to 0x0FFFFF
+        SUBX    #(0xE000-0x2000)  ;// map 0xE000 to 0x2000
+#else
+        CPX     #0xA000
+        BLO     PagedRAM_AREA
+// from 0x0FA000 to 0x0FFFFF
+        SUBX    #(0xA000-0x2000)  ;// map 0xA000 to 0x2000
+#endif
+        RTS
+PagedRAM_AREA:
+// from 0x001000 to 0x0FDFFF (0x001000 to 0x0F9FFF if HCS12XE RAM mapping is enabled) 
+        ANDX    #0x0FFF
+        LEAX    0x1000,X          ;// same as ORX #0x1000
+        RTS
+
+Below001000:
+// from 0x000000 to 0x000FFF
+        RTS
+  }
+#endif
+}
+
+/*--------------------------- _CONV_NEAR_TO_GLOBAL --------------------------------
+  Convert 16 bit logical to 24 bit global pointer
+    ("char*__near" to "char*__far")
+
+  Arguments :
+  - X : 16 bit near pointer
+
+  Postcondition :
+  - B == page of returned global address
+  - X == offset of returned global address
+  - Y remains unchanged
+  - A is unspecified
+*/
+/*--------------------------- Convert 16 bit logical to 24 bit global pointer ----------------------------------*/
+
+/* B:X = Global(X) */
+
+#ifdef __cplusplus
+extern "C"
+#endif
+
+#pragma NO_FRAME
+#pragma NO_ENTRY
+#pragma NO_EXIT
+
+void NEAR _CONV_NEAR_TO_GLOBAL(void){
+  __asm {
+    // syntax:
+    //  input 16 bit offset is bit15..bit0
+    //  ppage values: ppage7..ppage0
+    //  epage values: epage7..epage0
+    //  dpage values: dpage7..dpage0
+    //  rpage values: rpage7..rpage0
+        PSHX                      ;// D contains bit15..bit0
+        TFR     X,D               ;// D is cheaper to shift
+        LSLD                      ;// D contains 0 bit14..bit0, C contains bit15
+        BCC     Below8000         ;// bit15 == 0?
+        // from 0x8000 to 0xFFFF
+        LSLD                      ;// D contains 00 bit13..bit0, C contains bit14
+        BCC     BelowC000
+        LDAB    #0x7F
+        PULX
+        RTS                       ;// returns 0b0111 1111 11 bit13...bit0
+BelowC000:                      ;// from 0x8000 to 0xBFFF
+        TFR     D,X
+        LDAB    __PPAGE_ADR__
+        SEC
+        RORB
+        RORX
+        LSRB
+        RORX
+        LEAS    2,SP
+        RTS                       ;// returns 0b01 ppage7..ppage0 bit13...bit0
+Below8000:
+        LSLD                      ;// D contains 00 bit13..bit0, C contains bit14
+        BCC     Below4000
+        // from 0x4000 to 0x7FFF
+        PULX
+#ifndef __HCS12XE_RAMHM_SET__
+        LDAB    #0x7F
+#else
+        LEAX    (0xC000-0x4000),X
+        LDAB    #0x0F             
+#endif
+        RTS                       ;// returns 0b0111 1111 01 bit13...bit0
+
+Below4000:
+        LSLD                      ;// D contains 000 bit12..bit0, C contains bit13
+        BCC     Below2000
+        // from 0x2000 to 0x3FFF
+        PULX
+#ifndef __HCS12XE_RAMHM_SET__
+        LEAX    (0xE000-0x2000),X
+#else
+        LEAX    (0xA000-0x2000),X
+#endif
+        LDAB    #0x0F
+        RTS                       ;// returns 0b0000 1111 111 bit12...bit0
+
+Below2000:
+        LSLD                      ;// D contains 0000 bit11..bit0, C contains bit12
+        BCC     Below1000
+        // from 0x1000 to 0x1FFF
+        LDAB    __RPAGE_ADR__
+        LDAA    #0x10
+        MUL
+        EORB    0,SP
+        EORB    #0x10             ;// clear 1 bit
+        STAB    0,SP
+        TFR     A,B
+        PULX
+        RTS
+
+Below1000:
+        LSLD                      ;// D contains 0000 0 bit10..bit0, C contains bit11
+        BCC     Below0800
+        // from 0x0800 to 0x0FFF
+        LSLD                      ;// D contains 0000 00 bit9..bit0, C contains bit10
+        BCC     Below0C00
+    // from 0x0C00 to 0x0FFF
+        LDAB    #0x13
+        PULX
+        LEAX     0xF000,X
+        RTS                       ;// returns 0b0001 0011 1111 11 bit9...bit0
+Below0C00:
+    // from 0x0800 to 0x0BFF
+        LDAB    __EPAGE_ADR__
+        LDAA    #0x04
+        MUL
+        EORB    0,SP
+        EORB    #0x08
+        STAB    0,SP
+        TFR     A,B
+        ORAB    #0b00010000
+        PULX
+        RTS
+Below0800:
+        PULX
+        CLRB
+        RTS
+  }
+}
+
+/*--------------------------- _CONV_STACK_NEAR_TO_GLOBAL --------------------------------
+  Convert 16 bit logical of address on the stack 24 bit global pointer
+    ("char*__near" to "char*__far")
+
+  Arguments :
+  - X : 16 bit near pointer
+
+  Postcondition :
+  - B == page of returned global address
+  - X == offset of returned global address
+  - Y remains unchanged
+  - A is unspecified
+*/
+/*--------------------------- Convert 16 bit logical stack address to 24 bit global pointer ----------------------------------*/
+
+/* B:X = Global(D) */
+
+#ifdef __cplusplus
+extern "C"
+#endif
+
+#pragma NO_FRAME
+#pragma NO_ENTRY
+#pragma NO_EXIT
+
+void NEAR _CONV_STACK_NEAR_TO_GLOBAL(void){
+  __asm {
+    // syntax:
+    //  input 16 bit offset is bit15..bit0
+    //  ppage values: ppage7..ppage0
+    //  epage values: epage7..epage0
+    //  dpage values: dpage7..dpage0
+    //  rpage values: rpage7..rpage0
+    // stack must be between $1000 and $3FFF.
+    // actually placing the stack at $1000 implies that the RPAGE register is not set (and correctly initialized)
+        CPX     #0x2000
+        BLO     PAGED_RAM
+    // Map 0x2000 to 0x0FE000 (0x0FA000 for HCS12XE RAM mapping is enabled)
+        LDAB    #0x0F
+#ifndef __HCS12XE_RAMHM_SET__
+        LEAX    (0xE000-0x2000),X ;// LEAX is one cycle faster than ADDX #
+#else
+        LEAX    (0xA000-0x2000),X ;// LEAX is one cycle faster than ADDX #
+#endif
+        RTS
+PAGED_RAM:
+        PSHX
+        LDAB    __RPAGE_ADR__
+        LDAA    #0x20
+        MUL
+        EORB    0,SP
+        EORB    #0x10             ;// clear 1 bit
+        STAB    0,SP
+        TFR     A,B
+        PULX
+        RTS
+  }
+}
+
+
+
+/*--------------------------- _CONV_LOGICAL_TO_GLOBAL --------------------------------
+  Convert 24 bit global to 24 bit logical pointer
+    ("char*__far" to "char*__gpage")
+
+  Arguments :
+  - B : page part of logical address
+  - X : 16 offset part of logical address
+
+  Postcondition :
+  - B == page of returned global address
+  - X == offset of returned global address
+  - Y remains unchanged
+  - A remains unchanged
+*/
+/*--------------------------- Convert 24 bit logical to 24 bit global pointer ----------------------------------*/
+
+/* B:X = Logical(B:X) */
+
+#ifdef __cplusplus
+extern "C"
+#endif
+
+#pragma NO_FRAME
+#pragma NO_ENTRY
+#pragma NO_EXIT
+
+void NEAR _CONV_LOGICAL_TO_GLOBAL(void) {
+
+  __asm {
+        // syntax:
+        //  input 16 bit offset is bit15..bit0
+        //  ppage values: ppage7..ppage0
+        //  epage values: epage7..epage0
+        //  dpage values: dpage7..dpage0
+        //  rpage values: rpage7..rpage0
+        PSHA                      ;// save A across this routine.
+        PSHX                      ;// D contains bit15..bit0
+        PSHB                      ;// store page
+        TFR     X,D               ;// D is cheaper to shift
+        LSLD                      ;// D contains 0 bit14..bit0, C contains bit15
+        BCC     Below8000         ;// bit15 == 0?
+    // from 0x8000 to 0xFFFF
+        LSLD                      ;// D contains 00 bit13..bit0, C contains bit14
+        BCC     BelowC000
+        PULB                      ;// cleanup stack
+        LDAB    #0x7F
+        PULX
+        PULA
+        RTS                       ;// returns 0b0111 1111 11 bit13...bit0
+BelowC000:                      ;// from 0x8000 to 0xBFFF
+        TFR     D,X
+        PULB                      ;// cleanup stack
+        SEC
+        RORB
+        RORX
+        LSRB
+        RORX
+        LEAS    2,SP
+        PULA
+        RTS                       ;// returns 0b01 ppage7..ppage0 bit13...bit0
+Below8000:
+        LSLD                      ;// D contains 00 bit13..bit0, C contains bit14
+        BCC     Below4000
+                                  ;// from 0x4000 to 0x7FFF
+        PULB                      ;// cleanup stack
+        PULX
+#ifndef __HCS12XE_RAMHM_SET__
+        LDAB    #0x7F
+#else
+        LEAX    (0xC000-0x4000),X
+        LDAB    #0x0F
+#endif
+        PULA
+        RTS                       ;// returns 0b0111 1111 01 bit13...bit0
+
+Below4000:
+        LSLD                      ;// D contains 000 bit12..bit0, C contains bit13
+        BCC     Below2000
+    // from 0x2000 to 0x3FFF
+        PULB                      ;// cleanup stack
+        PULX
+#ifndef __HCS12XE_RAMHM_SET__
+        LEAX    (0xE000-0x2000),X
+#else
+        LEAX    (0xA000-0x2000),X 
+#endif
+        LDAB    #0x0F
+        PULA
+        RTS                       ;// returns 0b0000 1111 111 bit12...bit0
+
+Below2000:
+        LSLD                      ;// D contains 0000 bit11..bit0, C contains bit12
+        BCC     Below1000
+    // from 0x1000 to 0x1FFF
+        PULB
+        LDAA    #0x10
+        MUL
+        EORB    0,SP
+        EORB    #0x10             ;// clear 1 bit
+        STAB    0,SP
+        TFR     A,B
+        PULX
+        PULA
+        RTS
+
+Below1000:
+        LSLD                      ;// D contains 0000 0 bit10..bit0, C contains bit11
+        BCC     Below0800
+    // from 0x0800 to 0x0FFF
+        LSLD                      ;// D contains 0000 00 bit9..bit0, C contains bit10
+        BCC     Below0C00
+    // from 0x0C00 to 0x0FFF
+        PULB                      ;// cleanup stack
+        LDAB    #0x13
+        PULX
+        LEAX    0xF000,X
+        PULA
+        RTS                       ;// returns 0b0001 0011 1111 11 bit9...bit0
+Below0C00:
+    // from 0x0800 to 0x0BFF
+        PULB
+        LDAA    #0x04
+        MUL
+        EORB    0,SP
+        EORB    #0x08
+        STAB    0,SP
+        TFR     A,B
+        ORAB    #0b00010000
+        PULX
+        PULA
+        RTS
+Below0800:
+        PULB
+        PULX
+        PULA
+        CLRB
+        RTS
+  }
+}
+
+/*--------------------------- _FAR_COPY_RC HCS12X Routines --------------------------------
+  copy larger far memory blocks
+  There are the following memory block copy routines:
+      _COPY :                   16 bit logical copies.
+                                  Src and dest are both near. Note: implemented in rtshc12.c and not here.
+      _FAR_COPY_RC              HC12/HCS12 struct copy routine.
+                                  Expects HC12/HCS12 logical 24 bit address.
+                                  Note: Does not exist for the HCS12X.
+                                  The HC12/HCS12 implementation is implemented above.
+      _FAR_COPY_GLOBAL_GLOBAL_RC:
+      _FAR_COPY_GLOBAL_LOGICAL_RC:
+      _FAR_COPY_LOGICAL_GLOBAL_RC:
+      _FAR_COPY_LOGICAL_LOGICAL_RC:
+      _FAR_COPY_NEAR_GLOBAL_RC:
+      _FAR_COPY_NEAR_LOGICAL_RC:
+      _FAR_COPY_GLOBAL_NEAR_RC:
+      _FAR_COPY_LOGICAL_NEAR_RC:  HCS12X specific far copy routine. The name describes what the src/dest address format are.
+                                    All near src arguments are passed in X, all 24 bit src in X/B.
+                                    All near dest arguments are passed in Y, all 24 bit src in Y/A.
+                                    (Note: HC12 _FAR_COPY_RC is using X/A as src and Y/B as dest, so the register usage is not the same!)
+
+  Arguments :
+  - B:X : src address (for NEAR/_COPY: only X)
+  - A:Y : dest address (for NEAR/_COPY: only Y)
+  - number of bytes to be copied behind return address (for _COPY: in D register). The number of bytes is always > 0
+
+  Result :
+  - memory area copied
+  - no registers are saved, i.e. all registers may be destroyed
+  - for _COPY: D contains 0.
+  - for HCS12X _FAR_COPY_... routines: GPAGE state is unknown
+*/
+
+
+#ifdef __cplusplus
+extern "C"
+#endif
+#pragma NO_ENTRY
+#pragma NO_EXIT
+#pragma NO_FRAME
+
+void NEAR _FAR_COPY_GLOBAL_GLOBAL_RC(void) {
+  __asm {
+        PSHD
+        PSHY
+        LDY     4,SP              ;// load return address
+        LDD     2,Y+              ;// load size
+        STY     4,SP              ;// store return address
+        PULY
+        PSHD
+        LDAB    3,SP
+Loop:
+        STAB    __GPAGE_ADR__
+        GLDAA   1,X+
+        MOVB    2,SP,__GPAGE_ADR__
+        GSTAA   1,Y+
+        DECW    0,SP
+        BNE     Loop
+        LEAS    4,SP
+        _SRET                     ;// debug info only: This is the last instr of a function with a special return
+        RTS
+  }
+}
+
+#ifdef __cplusplus
+extern "C"
+#endif
+#pragma NO_ENTRY
+#pragma NO_EXIT
+#pragma NO_FRAME
+
+void NEAR _SET_PAGE_REG_HCS12X(void) {
+  // Sets the page contained in A to the register controlling the logical addr contained in X.
+  // saves the old page before and returns it in A together with the page address just below the return address.
+  // X/Y both remain valid.
+  __asm {
+        PSHX
+        // 0000..FFFF
+        CPX     #0x8000
+        BLO     _LO8000
+        LDX     #__PPAGE_ADR__
+        BRA      Handle
+_LO8000:
+        // 0000..7FFF
+        CPX     #0x1000
+        BLO     _LO1000
+        LDX     #__RPAGE_ADR__
+        BRA      Handle
+_LO1000:
+        LDX     #__EPAGE_ADR__
+Handle:
+        LDAA    0,X               ;// load old page register content
+        STAB    0,X               ;// set new page register
+        STX     4,SP
+        PULX
+        RTS
+  }
+}
+
+
+#ifdef __cplusplus
+extern "C"
+#endif
+#pragma NO_ENTRY
+#pragma NO_EXIT
+#pragma NO_FRAME
+
+void NEAR _FAR_COPY_GLOBAL_LOGICAL_RC(void) {
+  __asm {
+        STAB    __GPAGE_ADR__
+        EXG     X,Y
+        TFR     A,B
+        PSHY                      ;// space to store size
+        PSHX                      ;// allocate some space where _SET_PAGE_REG_HCS12X can return the page
+        LDY     4,SP              ;// load return address
+        LDX     2,Y+              ;// load size
+        STY     4,SP
+        LDY     2,SP              ;// restore dest pointer
+        STX     2,SP              ;// store size
+        LDX     0,SP              ;// reload src pointer
+        __PIC_JSR(_SET_PAGE_REG_HCS12X)
+
+Loop:   GLDAB   1,Y+
+        STAB    1,X+
+        DECW    2,SP
+        BNE     Loop
+
+        PULX                      ;// reload page register address
+        STAA    0,X               ;// restore old page content (necessary if it was PPAGE)
+        PULX                      ;// clean up stack
+        _SRET                     ;// debug info only: This is the last instr of a function with a special return
+        RTS
+  }
+}
+
+#ifdef __cplusplus
+extern "C"
+#endif
+#pragma NO_ENTRY
+#pragma NO_EXIT
+#pragma NO_FRAME
+
+void NEAR _FAR_COPY_LOGICAL_GLOBAL_RC(void) {
+  __asm {
+        STAA    __GPAGE_ADR__
+        PSHY                      ;// space to store size
+        PSHX                      ;// allocate some space where _SET_PAGE_REG_HCS12X can return the page
+        LDY     4,SP              ;// load return address
+        LDX     2,Y+              ;// load size
+        STY     4,SP
+        LDY     2,SP              ;// restore dest pointer
+        STX     2,SP              ;// store size
+        LDX     0,SP              ;// reload src pointer
+
+        __PIC_JSR(_SET_PAGE_REG_HCS12X)
+
+Loop:   LDAB    1,X+
+        GSTAB   1,Y+
+        DECW    2,SP
+        BNE     Loop
+
+        PULX
+        STAA    0,X               ;// restore old page content (necessary if it was PPAGE)
+        PULX                      ;// clean up stack
+        _SRET                     ;// debug info only: This is the last instr of a function with a special return
+        RTS
+  }
+}
+
+#ifdef __cplusplus
+extern "C"
+#endif
+#pragma NO_ENTRY
+#pragma NO_EXIT
+#pragma NO_FRAME
+
+void NEAR _FAR_COPY_LOGICAL_LOGICAL_RC(void) {
+  __asm {
+        PSHA
+        __PIC_JSR(_CONV_LOGICAL_TO_GLOBAL);
+        PULA
+        __PIC_JMP(_FAR_COPY_GLOBAL_LOGICAL_RC);
+  }
+}
+
+#ifdef __cplusplus
+extern "C"
+#endif
+#pragma NO_ENTRY
+#pragma NO_EXIT
+#pragma NO_FRAME
+
+void NEAR _FAR_COPY_NEAR_GLOBAL_RC(void) {
+  __asm {
+        CLRB
+        __PIC_JMP(_FAR_COPY_LOGICAL_GLOBAL_RC);
+  }
+}
+
+#ifdef __cplusplus
+extern "C"
+#endif
+#pragma NO_ENTRY
+#pragma NO_EXIT
+#pragma NO_FRAME
+
+void NEAR _FAR_COPY_NEAR_LOGICAL_RC(void) {
+  __asm {
+        PSHA
+        __PIC_JSR(_CONV_NEAR_TO_GLOBAL);
+        PULA
+        __PIC_JMP(_FAR_COPY_GLOBAL_LOGICAL_RC);
+  }
+}
+
+#ifdef __cplusplus
+extern "C"
+#endif
+#pragma NO_ENTRY
+#pragma NO_EXIT
+#pragma NO_FRAME
+
+void NEAR _FAR_COPY_GLOBAL_NEAR_RC(void) {
+  __asm {
+        CLRA                      /* near to logical (we may have to use another runtime if this gets non trivial as well :-( */
+        __PIC_JMP(_FAR_COPY_GLOBAL_LOGICAL_RC);
+  }
+}
+
+#ifdef __cplusplus
+extern "C"
+#endif
+#pragma NO_ENTRY
+#pragma NO_EXIT
+#pragma NO_FRAME
+
+void NEAR _FAR_COPY_LOGICAL_NEAR_RC(void) {
+  __asm {
+        EXG     A,B
+        EXG     X,Y
+        PSHA
+        __PIC_JSR(_CONV_NEAR_TO_GLOBAL);
+        PULA
+        EXG     A,B
+        EXG     X,Y
+        __PIC_JMP(_FAR_COPY_LOGICAL_GLOBAL_RC);
+  }
+}
+
+/* _FAR_COPY_LOGICAL_GLOBAL: is used by some old wizard generated projects. Not used by current setup anymore */
+
+#ifdef __cplusplus
+extern "C"
+#endif
+#pragma NO_ENTRY
+#pragma NO_EXIT
+#pragma NO_FRAME
+
+void NEAR _FAR_COPY_LOGICAL_GLOBAL(void) {
+  __asm {
+        STAA    __GPAGE_ADR__
+        PSHX                      ;// allocate some space where _SET_PAGE_REG_HCS12X can return the page
+        __PIC_JSR(_SET_PAGE_REG_HCS12X)
+
+Loop:   LDAB    1,X+
+        GSTAB   1,Y+
+        DECW    4,SP
+        BNE     Loop
+
+        PULX
+        STAA    0,X               ;// restore old page content (necessary if it was PPAGE)
+
+        LDX     4,SP+             ;// load return address and clean stack
+        JMP     0,X
+  }
+}
+
+
+#endif /* __HCS12X__  */
+
+
+/*----------------- end of code ------------------------------------------------*/

Final_Project/Sources/debounce.asm

@@ -0,0 +1,17 @@
+	XDEF	Debounce
+	XREF	__SEG_END_SSTACK	
+	
+Debounce:
+    PSHX          ;save X register                                  
+    LDX   #1000   ;1 ms delay
+    
+Loop:             ;delay loop
+    DEX
+    BNE   Loop
+    
+    PULX          ;restore X register
+    RTS           ;go back
+    
+   
+	
+	

Final_Project/Sources/derivative.h

@@ -0,0 +1,10 @@
+/*
+ * Note: This file is recreated by the project wizard whenever the MCU is
+ *       changed and should not be edited by hand
+ */
+
+/* Include the derivative-specific header file */
+#include <mc9s12e128.h>
+
+#pragma LINK_INFO DERIVATIVE "mc9s12e128"
+

Final_Project/Sources/derivative.inc

@@ -0,0 +1,10 @@
+
+ ; Note: This file is recreated by the project wizard whenever the MCU is
+ ;       changed and should not be edited by hand
+ ;
+
+			; include derivative specific macros
+            INCLUDE 'mc9s12e128.inc'
+
+		
+

Final_Project/Sources/eventloop.asm

@@ -0,0 +1,328 @@
+  ;export symbols
+	XDEF  RTI_ISR
+		
+	XREF	__SEG_END_SSTACK,disp,CRGFLG,read_pot
+	;clock
+	XREF  display_time,wall_timer
+  ;password
+  XREF  pw_set,pw_reset,pw_required
+  ;keypad
+  XREF  pressed_key,pressed_num
+  ;menu
+  XREF  menu_timer,menu_option_num,menu_active,menu_selection
+  ;circulation
+  XREF  dc_on,circulation_count,fan_speed
+  ;temperature
+  XREF  show_temperature,toast_timer
+  ;watering
+  XREF  is_watering,watering_timer,sprinkler_event,sprinkler_timer
+  ;wall clock
+  XREF  second_passed,ms_counter
+  ;debug
+  XREF  word_out
+   
+RTI_ISR:
+
+EventLoop:
+            ;***************** NOTE ****************
+            ; the menu timer is a general timer for
+            ; what to display
+            ;***************************************
+
+            ; ========= wall clock ==========
+            ;the event loop is configured (in main.asm) to run every 4 milliseconds
+            LDD   ms_counter        ;counts the milliseconds for the wall clock
+            ADDD  #04               ;add 4 milleseconds evey time the event loop runs (effectively the count starts at 4)
+            STD   ms_counter        ;store the ms_counter in memory (mostly for debugging)
+            CPD   #1004             ;check if one second has passed (accounting for the start at 4)
+            BLE   LessThanSec       ;less than one second has passed, continue to other functions
+            ;one second has passed
+            MOVB  #$FF,second_passed  ;this flag is set here and cleared in wall.asm
+            CLR   ms_counter
+            
+LessThanSec:;less than one second has passwed (do not fire a second passed event)              
+            ;don't do anything (except track the time) if the password is not set
+            LDAA  pw_set
+            CMPA  #$FF
+            LBNE   Return
+            
+            ;========= circualtion ===========
+            ;circulation is always happening (if the password is set)
+            ;the motor should spin as soon as the password is set
+            JSR 	read_pot            ;read the value of the pot into D
+            STD   word_out
+            LDX   #8		              ;load the bottom part of the divide (forget what it's called)
+                                      ;dividing 128 pot val. by 8 wields 16 different speeds possible                                  
+            IDIV                      ;value 1 through 16 is now in X
+            XGDX                      ;put the value in D
+            STAB  fan_speed           ;the lower byte of D is the fan speed, higher value for faster speed
+            
+            ;counter is in A
+            LDAA  circulation_count
+            INCA  
+            STAA  circulation_count
+            
+            ;from lab 6.3
+            ;here, fan speed has replaced the pressed value
+            CMPA  fan_speed           ;compare the counter to the fan speed
+            LBGT  FanOff              ;turn the fan off (low PWM)
+FanOn:      ;if the PWM should be high
+            MOVB  #$FF,dc_on          ;set the PWM high
+            BRA   FanReset            ;skip setting the pulse low
+
+            ;LBLE  SpinDC              ;branch to the stepper spinner
+             
+FanOff:     ;turn off the motor's PWM (low cycle)
+            CLR   dc_on            
+
+FanReset:   ;check if the fan counter needsd to be reset            
+            ;acc. A still has the circulation count
+            CMPA  #15                 ;16 is the max value of fan_speed
+            LBLE  DidMotor            ;do not clear the count if the count is in line with the speed       
+            CLR   circulation_count
+
+DidMotor:   ;branch here if the motor PWM has been applied
+
+            ;exit if the password is resetting 
+            LDAA  pw_reset
+            CMPA  #$FF
+            LBEQ  Return
+            
+            ;exit if the password is required
+            ;LDAA  pw_required
+            ;CMPA  #$FF
+            ;LBEQ  Return  
+
+            ;======== menu ===============
+            ;delay the menu change
+            LDX   menu_timer
+            INX
+            STX   menu_timer
+           
+            ;the menu should change here
+            LDX   menu_timer
+            CPX   #300
+            LBGE   CycleMenu
+            
+            ;==========================
+            LDX   toast_timer
+            INX
+            STX   toast_timer
+            
+            LDX   toast_timer
+            CPX   #200
+            LBGE   HideTemperature
+
+            ;====== watering ============
+            ;delay the watering stop
+            LDX  watering_timer
+            INX
+            STX  watering_timer
+ 
+            ;run sprinker
+            LDAA  sprinkler_timer
+            INCA  
+            STAA  sprinkler_timer
+            
+            LDAA  sprinkler_timer
+            CMPA  #7
+            LBGE  Sprinkle
+           
+            ;watering stop
+            LDX  watering_timer
+            CPX  #500
+            LBGE  StopWatering
+            
+            ;======= wall clock display ========
+            
+            LDX   wall_timer
+            INX
+            STX   wall_timer
+            
+            LDX   wall_timer
+            CPX   #200
+            LBGE  HideTime
+            
+            ;======= menu options ===========
+            ;call these here so that the counters can increment
+            ;watering start
+            LDAA  pressed_num
+            CMPA  #$01
+            BEQ   StartWatering
+            
+            ;show temperature
+            LDAA  pressed_num
+            CMPA  #$02
+            LBEQ  DisplayTemperature
+            
+            ;show wall clock
+            LDAA  pressed_num
+            CMPA  #$03
+            LBEQ  DisplayTime
+            
+            ;set time and date
+            LDAA  pressed_num
+            CMPA  #$04
+            LBEQ  SetTime
+            
+            ;trigger password reset
+            LDAA  pressed_num
+            CMPA  #$05
+            LBEQ  ResetPassword
+                  
+            ;======= temperature ========
+            ;delay the temperature display stoppage
+            ;LDX   temp_timer
+            ;INX
+            ;STX   temp_timer
+            
+
+            ;hide temperature
+            ;LDX  watering_timer
+            ;CPX  #750
+            ;BEQ   HideTemperature
+                                  
+            ;
+            ; 
+            ;LDAA  pressed_num         ;input into A for comparison
+            ;==================== menu items ======================
+            ;CMPA  #$01
+            ;BEQ   WaterPlants
+            
+            ;CMPA  #$02                ;pressed_num is the selected menu option
+            ;BEQ   ShowTemperature     ;menu option 1 is temperature
+            ;======================================================
+            ;
+            ;
+            ;
+            
+            ;return by default
+            LBRA   Return
+
+CycleMenu:  
+            ;reset the timer (s) and go to the next menu option
+            MOVW  #$0000,menu_timer     ;reset menu timer
+
+            ;track the menu option (this resets to 1 in menu.asm)
+            LDAA  menu_option_num
+            INCA  
+            STAA  menu_option_num
+            
+            ;exit
+            LBRA   Return  
+            
+            
+StartWatering:
+            ;water for a certain amount of time
+            MOVW  #$0000,watering_timer ;reset the watering timer
+            MOVB  #$FF,is_watering      ;turn on the water
+            
+            ;hide the other options
+            MOVB  #$00,show_temperature
+            MOVB  #$00,display_time
+            
+            MOVB  #$FF,pressed_num      ;clear the pressed number value
+            MOVB  #$00,menu_active      ;turn off the menu (dispay watering...)
+
+            LBRA   Return               ;exit
+            
+StopWatering:
+            MOVW  #$0000,watering_timer ;reset the watering timer
+            
+            LDAA  is_watering            ;check that watering needs to be stopped
+            CMPA  #$00
+            LBEQ  Return
+            
+            MOVB  #$00,is_watering       ;turn off the water
+            MOVB  #$FF,menu_active       ;restore the menu display
+            LBRA   Return                ;exit
+
+Sprinkle:
+            ;the sprinkler timer controls the speed of the stepper motor
+            CLR   sprinkler_timer
+            
+            ;check that the watering state is active before firing an event
+            LDAA  is_watering
+            CMPA  #$FF
+            LBNE   Return
+            
+            ;instruct the watering subroutine to send a signal to the stepper motor
+            MOVB  #$FF,sprinkler_event
+
+            ;exit
+            LBRA   Return
+       
+       
+DisplayTemperature:
+            MOVW  #$0000,toast_timer    ;clear the temperature timer
+            
+            ;do not disrupt watering
+            LDAA  is_watering
+            CMPA  #$FF
+            BEQ   Return
+
+            ;hide the other options
+            MOVB  #$00,menu_active      ;hide the menu
+            MOVB  #$00,display_time     ;hide the time
+            
+            MOVB  #$FF,pressed_num      ;clear the pressed number value
+            MOVB  #$FF,show_temperature ;set the show temperature flag
+            
+            BRA   Return
+            
+HideTemperature:
+            MOVW  #$0000,toast_timer    ;clear the temperature timer
+            
+            LDAA  show_temperature      ;do nothing if temperature is not showing
+            CMPA  #$00
+            LBEQ  Return
+
+            MOVB  #$00,show_temperature ;clear the show temperature flag       
+            MOVB  #$FF,menu_active      ;restore the menu
+            BRA   Return
+            
+DisplayTime:
+            MOVW  #$0000,wall_timer     ;clear the clock display timer
+            
+            ;do not disrupt watering
+            LDAA  is_watering
+            CMPA  #$FF
+            BEQ   Return
+            
+            ;hide the other display options
+            MOVB  #$00,show_temperature ;hide the temperature
+            MOVB  #$00,menu_active      ;hide the menu
+            
+            MOVB  #$FF,display_time     ;set the time display flag
+            MOVB  #$FF,pressed_num      ;clear the pressed number
+            
+            BRA   Return
+            
+HideTime:
+
+            MOVW  #$0000,wall_timer     ;clear the clock display timer
+            
+            LDAA  display_time
+            CMPA  #$00
+            LBEQ  Return
+
+            MOVB  #$00,display_time    ;clear the time display flag
+            MOVB  #$FF,menu_active     ;re-activate the menu
+            
+            BRA   Return
+           
+SetTime:
+            MOVB  #$FF,pw_required
+            BRA   Return
+            
+ResetPassword:
+            MOVB  #$FF,pw_reset
+            BRA   Return                                   
+          
+Return:
+            BSET  CRGFLG,$80
+            RTI
+            
+
+  
+  

Final_Project/Sources/funct.h

@@ -0,0 +1,27 @@
+#ifndef FUNCT_H
+#define FUNCT_H
+#pragma CODE_SEG NON_BANKED
+#define LCDDATA       PTADHi
+#define LCDDATADDR    DDRADHi
+#define LCDCONTROLDDR DDRM
+#define ECLK          PTM_PTM4
+#define RW            PTM_PTM5
+#define RS            PTM_PTM6
+
+#define LINE1 0x80
+#define LINE2 0xc0
+
+void init_LCD(void);
+void display_string(char *);
+
+void read_pot(void);
+void Delay(unsigned int);
+
+void delay_ms(int);
+void epulse(void);
+void sendCommand(int);
+
+void SendsChr(char, int);
+void PlayTone(void);
+
+#endif

Final_Project/Sources/growlights.asm

@@ -0,0 +1,27 @@
+                                                     	XDEF	Growlights
+	XREF	__SEG_END_SSTACK,grow_lights,PORT_T,PORT_S	
+	
+Growlights: ;push register and accumulator values for retention                   
+            PSHA
+            PSHB
+            PSHD
+            PSHX
+            PSHY
+
+            ;simply read the switches at T and output to LED's at S
+            LDAA    PORT_T
+            ;bit 3 is for the MOTOR
+            ;ANDA    #%11110111
+            STAA    PORT_S
+    
+Return:     ;restore registers and accumulators
+            PULY
+            PULX
+            PULD
+            PULB
+            PULA
+            
+            RTS
+   
+	
+	

Final_Project/Sources/keypad.asm

@@ -0,0 +1,97 @@
+          	XDEF	Keypad
+	XREF	__SEG_END_SSTACK,Debounce,KVS,pressed_key,pressed_num,PORT_U,SEQUENCE,PORT_S,await_key_release,keypad_timeout,await_key_press
+	
+Variables:	    	Section
+
+Constants:	      Section
+
+Code:		  	Section
+Keypad:     ;push register and accumulator values for retention                   
+            PSHA
+            PSHB
+            PSHD
+            PSHX
+            PSHY
+            
+            ;do not go to the task at the end of the array
+            ;when first starting i.e. ckip ArrayEnd for now
+            BRA   InitSequence
+
+ArrayEnd:   ;check the flag to await or not (await for passwords)
+            LDAB  await_key_press
+            CMPB  #$00          ;await is false
+            BEQ   Return        ;don't do anything else (do not await a keypress)
+                                ;otherwise re-initialze the sequence
+InitSequence:
+            LDX   #SEQUENCE     ;load the sequence into the X register
+ReadKeypress:
+
+
+            ;check wether or not to await
+            LDAA  1,X+          ;load the value at address in reg X to A
+            CMPA  #$00          ;check the value of A to zero
+            BEQ   ArrayEnd      ;this is the end of the array
+            
+            ;
+            ;
+            ;
+            ;given in instructions
+            STAA  PORT_U        ;output to port U
+            JSR   Debounce      ;delay 1 ms
+            LDAA  PORT_U        ;read port U back into acc. A
+            STAA  pressed_key   ;save the value of acc. A into memory (the value of the KVS array)
+            
+            ANDA  #$0F          ;mask the upper nibble
+            CMPA  #$0F          ;check if masked A == #$0F (no key pressed)
+            BEQ   ReadKeypress  ;send the next item in the sequence
+                        
+            ;
+            ;
+            ;
+            ;skip the release wait if the variable is set
+            LDAA  await_key_release
+            CMPA  #$00
+            BEQ   InitLookup
+            
+AwaitRelease:                   ;a key is pressed
+            LDAA  PORT_U        ;read port U
+            ANDA  #$0F          ;mask the upper nibble
+            CMPA  #$0F          ;check if masked A == #$0F (no key pressed)
+            BNE   AwaitRelease  ;wait for the key to be released
+            
+            
+InitLookup:                     ;check for a match in the lookup table
+            LDY   #KVS          ;load the initital value of KVS array
+            LDAB  #$00          ;iteration counter
+Lookup:
+            LDAA  1,Y+          ;load a value from the lookup table into A
+            CMPA  pressed_key       ;compare the LUT value to the pressed key
+            BEQ   Found         ;pressed key reached/found within LUT
+            INCB                ;increment the counter
+            BRA   Lookup        ;check the value at the next index
+Found:
+            STAB  pressed_num   ;the index of the PRESSED value (the numeral of the pressed key) in the KVS/LUT from B -> memory  
+
+;AwaitPress:
+;            LDAB  await_key_press
+;            CMPB  #$FF
+;            BEQ   InitSequence            
+            
+Return:     
+            ;clear the keypad timeout
+            ;CLR   keypad_timeout
+            ;restore registers and accumulators
+            PULY
+            PULX
+            PULD
+            PULB
+            PULA
+            
+            RTS
+            
+            
+            
+            
+            
+                
+            

Final_Project/Sources/lcddisp.c

@@ -0,0 +1,107 @@
+#include "derivative.h"
+#include "funct.h"
+
+int data = 0; //used to determine if a command or data is being sent, sets RS
+
+#define LCDDATA       PTADHi
+#define LCDDATADDR    DDRADHi
+#define LCDCONTROLDDR DDRM
+#define ECLK          PTM_PTM4
+#define RW            PTM_PTM5
+#define RS            PTM_PTM6
+
+#define LINE1 0x80
+#define LINE2 0xc0
+
+void delay_ms(int delay) //Not a precise delay
+{
+	int x;
+	while (delay > 0)
+	{
+		for (x = 700; x > 0; x--);
+		delay--;
+	}
+}
+
+void init_LCD()
+{
+        LCDDATADDR = 0xFF; //Set PORT AD 8-15 as outputs, 
+        LCDDATA = 0x00; // Clear Port AD 8-15 I/O register 
+        LCDCONTROLDDR = LCDCONTROLDDR | 0x70; //Set bits 4, 5, and 6 of Port M as outputs (ECLK, RW, RS respectively)
+
+	delay_ms(5);
+
+        ECLK = 1;
+        delay_ms(50); //Small Start Delay
+  
+        //LCD Initialization
+        data = 0;
+	LCDDATA = 0x03;
+	epulse();
+	delay_ms(5);
+	epulse();
+	delay_ms(5);
+	epulse();
+	delay_ms(5);
+	
+        //Setup LCD Screen
+	sendCommand(0x3C); //Set Interface Length, 8-data lines, 2 display lines
+	sendCommand(0x10); //Turn off Display
+	sendCommand(0x01); //Clear Display
+	sendCommand(0x06); //Set Cursor Move direction, Auto-Increment cursor after each byte written, dont shift display
+	sendCommand(0x0c); //Display on, cursor off
+}
+
+
+void display_string(char* SendStr)
+{
+	unsigned char count=0;	
+
+	//return home
+	sendCommand(LINE1); //Start from the beginning of the LCD (Line 1)
+
+	while(*SendStr!=0)
+	{
+		
+		if(count == 16)
+		{
+			sendCommand(LINE2); //Switch to Line 2
+		}
+		++count;	
+		data = 1; //Send Character
+                LCDDATA = *SendStr;
+	        epulse();
+		++SendStr;
+	}
+}
+
+
+
+void Delay(unsigned int DelayCount)
+{
+	unsigned int i, j;
+
+	for(i = 0; i < DelayCount; i++)
+		for(j = 0; j < 2000; j++)
+			;
+}
+
+
+void epulse(void) //Pulse E Clock
+{
+	if (data) RS = 1;
+	else RS = 0;
+	delay_ms(1);
+
+	ECLK = 0;
+	delay_ms(1);
+	ECLK = 1;
+}
+
+
+void sendCommand( int byte )//Send a byte command to LCD
+{
+	data = 0; //Send Command
+	LCDDATA = byte;
+	epulse();	
+}

Final_Project/Sources/main.asm

@@ -0,0 +1,315 @@
+                                                                                                                                      ;**************************************************************
+;* This stationery serves as the framework for a              *
+;* user application. For a more comprehensive program that    *
+;* demonstrates the more advanced functionality of this       *
+;* processor, please see the demonstration applications       *
+;* located in the examples subdirectory of the                *
+;* Freescale CodeWarrior for the HC12 Program directory       *
+;**************************************************************
+; Include derivative-specific definitions
+            INCLUDE 'derivative.inc'
+            
+            XREF __SEG_END_SSTACK      ; symbol defined by the linker for the end of the stack
+            ; LCD References
+	          XREF  init_LCD
+
+; export symbols
+            ; we use export 'Entry' as symbol. This allows us to
+            ; reference 'Entry' either in the linker .prm file
+            ; or from C/C++ later on
+            XDEF  Entry,_Startup,disp,CRGFLG
+            
+            ;==================== variables =================================
+            ;password
+            XDEF  password,new_password,pw_prompt_shown,pw_check,pw_correct,pw_set,pw_incorrect,entered_password,pw_required
+            ;keypad
+            XDEF  pressed_key,pressed_num,await_key_release,await_key_press
+            ;menu
+            XDEF  menu_active,toast_timer,menu_option_num,menu_timer,display_timeout
+            ;watering (menu option 1)
+            XDEF  is_watering,watering_timer,sprinkler_event,sprinkler_timer,sprinkler_arr_i
+            ;temperature (menu option 2)
+            XDEF  show_temperature,fan_speed,circulation_count,dc_on
+            ;wall clock (menu option 3)
+            XDEF  current_year,current_month,current_day,current_hour,current_minute,current_second
+            XDEF  display_time,wall_timer,clock_event,second_passed,ms_counter
+            ;adjust clock (menu option 4)
+            XDEF  change_time
+            ;reset password (menu option 5)
+            XDEF  pw_reset
+            
+            ;================== constants =================================
+            ;ports and peripherals 
+            XDEF  PSR_U,PDR_U,PORT_U,DDR_T,PORT_T,DDR_P,PORT_P,DDR_S,PORT_S
+            ;keypad
+            XDEF  KVS,SEQUENCE
+            ;stepper motor
+            XDEF  SPRINKLER_ARR
+
+            ;===================== subroutines =============================
+            ; Potentiometer References
+            XREF  display_string
+            XREF  pot_value
+
+            ;subroutines
+            XREF  Password,Menu,Keypad,Water,Circulation,Wall,Growlights
+            
+            ;================= debugging ===================================
+            XDEF  word_out,byte_out
+            
+            
+            
+            
+; ================= general notes =====================
+; - routines should generally be asynchronous            
+; - need a way to marshall values into single characters
+;     like the pot. resistance display from lab
+; - use two seperate routines, one for each song
+; - set all the flags with the 1 ms RTI
+; - reading the password asychronously will be a
+;     pain in the ass, maybe skip that
+;     - think about the last lab and skipping the await
+;====================================================== 
+   
+   
+            
+;================ flow of the program =================
+; 1. Prompt for the password. Nothing will happen until the password is set.
+; 2. Acknowlege the password, wait, then show help, wait, then show menu
+; 3. Show help, wait (press 0 to show help)
+; 4. Show main menu, start air circulation, and start grow light control
+;======================================================
+
+
+
+;==================== main menu =======================
+; 1. water the plants
+; 2. show temperature (adjusts when the pot is turned)
+; 3. show time
+; 4. set time (passord protected)
+; 5. change password (password protected)
+;======================================================
+
+; variable/data section
+my_variable: SECTION
+disp            	ds.b    33        ;the character string to output to the LCD (given)
+
+;password variables
+password:         ds.b    8         ;the byte array that stores the password
+entered_password  ds.b    8         ;will be check against the password
+new_password      ds.b    8         ;overwrite the old password with a new one
+pw_prompt_shown   ds.b    1         ;only print the initial password prompt once
+pw_check          ds.b    1         ;require the password before continueing
+pw_correct        ds.b    1         ;check the correctness of the password
+pw_set            ds.b    1         ;flag to fire after the password has been entered
+pw_incorrect      ds.b    1         ;will determine if the password needs to be tried again
+pw_required       ds.b    1         ;flag to set if a password is required to enter a screen
+
+;keypad variables
+pressed_key       ds.b    1         ;the keypad value in the LUT
+pressed_num       ds.b    1         ;the numeral of the pressed key or the index of PRESSED in the LUT
+await_key_release ds.b    1         ;whether or not to await the keypad release
+await_key_press   ds.b    1
+
+;================== state variables =====================
+
+; Primary UI 
+menu_active       ds.b    1         ;show the main menu
+toast_timer       ds.w    1         ;(counter) used to delay the screen outputs so that the user can read them
+menu_option_num   ds.b    1         ;which menu option is displayed
+menu_timer        ds.w    1         ;timer to check the menu cycle
+display_timeout   ds.b    1         ;(flag) to go back to the menu when an input is made
+
+; menu item 1 (watering state)
+is_watering       ds.b    1         ;flag that sets the state to watering (spin the motor, play the tune, and
+                                    ;show "Watering in \nprogress..." on the LCD
+                                    ;also one or more LED's should illuminate
+                                    ;also the stepper motor should spin like a sprinkler
+                                    ;also this should only run for a period of time
+watering_timer    ds.w    1         ;(counter) to time the watering, stop after some time
+sprinkler_event   ds.b    1         ;event to fire to spin stepper motor like a sprinkler
+sprinkler_timer   ds.b    1         ;(counter) time delay for sprinkler
+sprinkler_arr_i   ds.b    1         ;sprinkler array index
+; menu item 2 (air circulation state, show temperature)
+show_temperature  ds.b    1         ;display the current temperature    
+fan_speed         ds.b    1         ;reads the potentiometer
+circulation_count ds.b    1         ;counter to spin the DC motor
+dc_on             ds.b    1         ;event pulse for DC motor
+
+; menu item 3 (display time)
+display_time      ds.b    1         ;show the time on the screen
+current_year      ds.w    1         ;what year is it 
+current_month     ds.b    1         ;what month is it (a number)
+current_day       ds.b    1         ;day of the month
+current_hour      ds.b    1         ;hour of the day (military time)
+current_minute    ds.b    1         ;...
+current_second    ds.b    1         ;...
+wall_timer        ds.w    1         ;timeout for the clock display
+clock_event       ds.b    1         ;event that will fire every 4 milliseconds
+ms_counter        ds.w    1         ;counter for the milliseconds
+second_passed     ds.b    1         ;event that fires when a second has passed
+setting_wall      ds.b    1         ;will flag when the clock is being set by the user
+
+; menu item 4 (change time)
+change_time       ds.b    1         ;the user has elected to change the date and the time
+                                    ;all or nothing on this; everything must be entered
+                                    
+; menu item 5 (change password)
+pw_reset          ds.b    1         ;flag to trigger that a password should be reset
+                                    ;this should be done in an async manner when prompted by the user
+                                    ;(in an emergency, this process should be synchronous)
+                                    ;in order to not stop the air or watering or grow lights
+
+; menu item 6 (plant seeds)
+
+
+
+; menu option 7 (show plot)
+               
+                                    
+                                    
+; debugging
+word_out          ds.w    1                                    
+byte_out          ds.b    1                                    
+;=============================== END state variables =====================================
+
+my_constant:  SECTION
+;ports
+DDR_U	      equ		  $26A
+PSR_U       equ     $26D
+PDR_U       equ     $26C
+PORT_U      equ     $268
+
+DDR_T       equ     $242  ;the DIP switches and DC motor
+PORT_T      equ     $240
+
+PORT_P    	equ   	$258         ;stepper motor
+DDR_P     	equ 	  $25A  
+
+DDR_S       equ     $24A   ;LED's
+PORT_S      equ     $248
+
+;keypad           ;key value pairs from 4.3
+KVS         dc.b  $EB,$77,$7B,$7D,$B7,$BB,$BD,$D7,$DB,$DD,$E7,$ED,$7E,$BE,$DE,$EE
+                  ;given sequence from lab instructions (with trailing zero)
+SEQUENCE    dc.b  $70,$B0,$D0,$E0,$00
+;stepper motor
+SPRINKLER_ARR dc.b $0A,$12,$14,$12,$14,$0C,$14,$0C 
+                    
+MyCode:     SECTION
+_Startup:
+Entry:
+            lds     #__SEG_END_SSTACK
+            ;keypad stuff 
+            BSET    DDR_U,#$F0        ;bits 1-3 in bits 4-7 out
+            BSET    PSR_U,#$F0        ;pins 1-3 pull up
+            BSET    PDR_U,#$0F        ;pull up pins 1-3
+            CLR     await_key_release ;do not await by default
+            MOVB    #$FF,await_key_press;await presses by default
+            
+            ;LED stuff
+            BSET    DDR_S,#$FF        ;all outputs on LED port
+            MOVB    #$00,PORT_S       ;off initally
+            
+            ;switch and DC motor stuff
+            MOVB    #$08,DDR_T        ;needs to be set for the motor to spin
+
+            ;LCD stuff
+            JSR  init_LCD
+            
+            ;event loop stuff
+            MOVB    #$80,CRGINT       ;enable real-time interrupts
+            MOVB    #$60,RTICTL       ;set RTI interval to 4 ms; "#$40,RTICTL" would be 1 ms
+            ;MOVB    #$40,RTICTL
+            CLI                       ;enable interrupts
+            
+            ;state variable stuff (password
+            MOVB  #$FF,password       ;this password will never be correct, it needs to be changed
+            MOVB  #$FF,password+1 
+            MOVB  #$FF,password+2 
+            MOVB  #$FF,password+3 
+            MOVB  #$FF,password+4 
+            MOVB  #$FF,password+5 
+            MOVB  #$FF,password+6 
+            MOVB  #$FF,password+7
+            CLR   pw_set              ;the password is not inititally set
+            CLR   pw_incorrect        ;the password will not start out as incorrect because it hasn't been set
+            CLR   pw_correct
+            
+            ;menu stuff
+            CLR   menu_active         ;menu is not inititally active
+            MOVB  #$01,menu_option_num;start on option '1'
+            CLR   menu_timer          ;set the menu timer at '0' this will be incremented in the event loop
+            
+            ;watering and stepper motor stuff
+            CLR   is_watering         ;watering
+            CLR   watering_timer      ;duration of watering
+            CLR   sprinkler_event     ;fired to the stepper motor
+            CLR   sprinkler_timer     ;duration of delay among items of the stepper array sequence
+            MOVB  #$1E,DDR_P          ;DDR setting for the stepper
+            MOVB  #$00,sprinkler_arr_i;start at the beginning of the array
+            
+            ;other menu items
+            CLR   show_temperature    ;menu item
+            CLR   change_time         ;menu item
+            CLR   pw_reset            ;menu item
+            
+            ;circulation             
+            CLR   fan_speed          
+            CLR   circulation_count
+            
+            ;wall clock
+            MOVW  #1970,current_year  ;UNIX time
+            MOVB  #1,current_month    ;start on Jan. 1
+            MOVB  #1,current_day      ;...
+            CLR   current_hour        ;start at 00:00:00
+            CLR   current_minute      ;...
+            CLR   current_second      ;...
+            CLR   wall_timer          ;the timer that sets whether or not the clock displays
+            CLR   clock_event         ;event is not initially fired
+            CLR   second_passed       ;event that will fire each time one second has passed
+            CLR   ms_counter          ;count milliseconds in the event loop
+            CLR   display_time
+
+                        
+Init:
+            ;run any password related things first
+            JSR   Password
+            
+            ;do nothing until the password is set
+            LDAA  pw_set
+            CMPA  #$FF
+            BNE   Init
+            
+            ;activate the menu after the password is set
+            MOVB  #$FF,menu_active
+            ;hide evey other display element
+            
+            
+            ;set the keypress to an impossible value
+            ;this clears the value from the password
+            ;before reading the keypress in the menu
+            MOVB  #$FF,pressed_num
+Main:           
+            ;go to the menu when the password is set
+            JSR   Menu
+            
+            ;call each subroutine
+            ;subroutines are controlled by events fired in the RTI
+            JSR   Circulation
+            JSR   Water
+            JSR   Growlights; <- should be uncommented (using LED's for debugging)
+            JSR   Wall
+            JSR   Password
+            
+            ;read the keypad when the menu is showing
+            ;make the keypad read not branch from the password leftover pressed value
+            ;the keypad being the primary means of controlling the program,
+            ;we have it running in main (for now) 
+            ;get user menu selection (do not await presses or releases)
+            MOVB  #$00,await_key_release
+            MOVB  #$00,await_key_press     
+            JSR   Keypad
+            
+            ;return to the main loop
+            BRA   Main

Final_Project/Sources/main_asm.h

@@ -0,0 +1,15 @@
+#ifndef _MAIN_ASM_H
+#define _MAIN_ASM_H
+
+#ifdef __cplusplus
+    extern "C" { /* our assembly functions have C calling convention */
+#endif
+
+void asm_main(void);
+  /* interface to my assembly main function */
+
+#ifdef __cplusplus
+    }
+#endif
+
+#endif /* _MAIN_ASM_H */

Final_Project/Sources/mc68hc912b32.h

@@ -0,0 +1,2264 @@
+/*****************************************************
+     6812b32.h - Target interface library
+     Describes I/O registers of MC68HC12B32
+----------------------------------------------------
+   Copyright (c) Metrowerks, Basel, Switzerland
+                  Do not modify!
+*****************************************************/
+
+/****************************************!! WARNINGS !!*********************************************/
+/*      1)PORT A, PORT B, and data direction registers DDRA and DDRB are not in map in expanded    */
+/*      and peripheral modes                                                                       */
+/*      2)PORT E and DDRE not in map in peripheral mode; also not in map in expanded modes with    */
+/*      EME set.                                                                                   */
+/*      3)MODE, PUCR, AND RDRIV not in map in peripheral mode.                                     */
+/*      4)Choose carefully your variable names.For example: 'M' is the defined name of the bit 4   */
+/*      from the register 'SC0CR1' (SCI Control Register 1).                                       */
+/***************************************************************************************************/
+
+#ifndef __6812B32_H__
+#define __6812B32_H__
+
+#define _IO_BASE_ADDR 0
+#define _IO_AT(x)  @(_IO_BASE_ADDR+(x))
+
+#ifndef __DECL__6812B32_H__
+#define __DECL__6812B32_H__  extern
+#endif
+
+#pragma MESSAGE DISABLE C1106 /* WARNING C1106: Non-standard bitfield type */
+
+#include <stdtypes.h>
+
+/**************************************************************************************************/
+/*                                         DEFINE PORT A                                          */
+/**************************************************************************************************/
+
+__DECL__6812B32_H__ volatile  unsigned char PORTA    _IO_AT(0x00);  /* port A */
+
+__DECL__6812B32_H__ volatile  unsigned char DDRA     _IO_AT(0x02);  /* data direction port A */
+
+
+/**************************************************************************************************/
+/*                                         DEFINE PORT B                                          */
+/**************************************************************************************************/
+
+__DECL__6812B32_H__ volatile  unsigned char PORTB    _IO_AT(0x01);  /* port B */
+
+__DECL__6812B32_H__ volatile  unsigned char DDRB     _IO_AT(0x03);  /* data direction port B */
+
+
+/**************************************************************************************************/
+/*                                         DEFINE PORT E                                          */
+/**************************************************************************************************/
+
+
+__DECL__6812B32_H__ volatile  unsigned char PORTE    _IO_AT(0x08);  /* port E */
+
+
+__DECL__6812B32_H__ volatile union {
+  struct {
+    unsigned char BIT0:1;
+    unsigned char BIT1:1;
+    unsigned char _DDE2:1;
+    unsigned char _DDE3:1;
+    unsigned char _DDE4:1;
+    unsigned char _DDE5:1;
+    unsigned char _DDE6:1;
+    unsigned char _DDE7:1;
+  } DDRE_BITS;
+  unsigned char DDRE_BYTE;
+}DDRE1  _IO_AT(0x09);
+
+/* DEFINE REGISTER */
+#define DDRE DDRE1.DDRE_BYTE
+
+/*DEFINE REGISTER BITS*/
+#define DDE2 DDRE1.DDRE_BITS._DDE2
+#define DDE3 DDRE1.DDRE_BITS._DDE3
+#define DDE4 DDRE1.DDRE_BITS._DDE4
+#define DDE5 DDRE1.DDRE_BITS._DDE5
+#define DDE6 DDRE1.DDRE_BITS._DDE6
+#define DDE7 DDRE1.DDRE_BITS._DDE7
+
+/**************************************************************************************************/
+/*                               PORT E ASSIGNEMENT REGISTER                                      */
+/**************************************************************************************************/
+
+__DECL__6812B32_H__ volatile union {
+  struct {
+    unsigned char BIT0:1;
+    unsigned char BIT1:1;
+    unsigned char _RDWE:1;
+    unsigned char _LSTRE:1;
+    unsigned char _NECLK:1;
+    unsigned char _PIPOE:1;
+    unsigned char _BIT6:1;
+    unsigned char _NDBE:1;
+  } PEAR_BITS;
+  unsigned char PEAR_BYTE;
+}PEAR1 _IO_AT(0x0a);
+
+/*DEFINE FOR THE COMPATIBILITY WITH OLD VERSION*/
+/*           "CKL" INSTEAD OF "CLK"            */
+#define _NECKL _NECLK
+#define NECKL NECLK
+
+/*DEFINE REGISTER*/
+#define PEAR PEAR1.PEAR_BYTE
+
+/*DEFINE REGISTER BITS*/
+#define RDWE PEAR1.PEAR_BITS._RDWE
+#define LSTRE PEAR1.PEAR_BITS._LSTRE
+#define NECLK PEAR1.PEAR_BITS._NECLK
+#define PIPOE PEAR1.PEAR_BITS._PIPOE
+#define NDBE PEAR1.PEAR_BITS._NDBE
+
+/**************************************************************************************************/
+/*                                            MODE REGISTER                                       */
+/**************************************************************************************************/
+
+__DECL__6812B32_H__ volatile union {
+  struct {
+    unsigned char _EME:1     ;
+    unsigned char _BIT1:1    ;
+    unsigned char _EBSWAI:1  ;
+    unsigned char _IVIS:1    ;
+    unsigned char _ESTR:1    ;
+    unsigned char _MODA:1    ;
+    unsigned char _MODB:1    ;
+    unsigned char _SMODN:1   ;
+  } MODE_BITS;
+  unsigned char MODE_BYTE;
+}MODE1 _IO_AT(0x0B);
+
+/*DEFINE REGISTER*/
+#define MODE MODE1.MODE_BYTE
+
+/*DEFINE REGISTER BITS*/
+#define EME MODE1.MODE_BITS._EME
+#define EBSWAI MODE1.MODE_BITS._EBSWAI
+#define IVIS MODE1.MODE_BITS._IVIS
+#define ESTR MODE1.MODE_BITS._ESTR
+#define MODA MODE1.MODE_BITS._MODA
+#define MODB MODE1.MODE_BITS._MODB
+#define SMODN MODE1.MODE_BITS._SMODN
+
+/**************************************************************************************************/
+/*                               PULL-UP CONTROL REGISTER                                         */
+/**************************************************************************************************/
+
+__DECL__6812B32_H__ volatile union {
+  struct {
+    unsigned char _PUPA:1;
+    unsigned char _PUPB:1;
+    unsigned char BIT2:1;
+    unsigned char BIT3:1;
+    unsigned char _PUPE:1;
+    unsigned char BIT5:1;
+    unsigned char BIT6:1;
+    unsigned char BIT7:1;
+  } PUCR_BITS;
+  unsigned char PUCR_BYTE;
+}PUCR1 _IO_AT(0x0C);
+
+/*DEFINE REGISTER*/
+#define PUCR PUCR1.PUCR_BYTE
+
+/*DEFINE REGISTER BITS*/
+#define PUPA PUCR1.PUCR_BITS._PUPA
+#define PUPB PUCR1.PUCR_BITS._PUPB
+#define PUPE PUCR1.PUCR_BITS._PUPE
+
+/**************************************************************************************************/
+/*                               REDUCED DRIVE OF I\O LINES                                       */
+/**************************************************************************************************/
+
+__DECL__6812B32_H__ volatile union {
+  struct {
+    unsigned char _RDPA:1;
+    unsigned char _RDPB:1;
+    unsigned char BIT2:1;
+    unsigned char _RDPE:1;
+    unsigned char BIT4:1;
+    unsigned char BIT5:1;
+    unsigned char BIT6:1;
+    unsigned char BIT7:1;
+  } RDRIV_BITS;
+  unsigned char RDRIV_BYTE;
+}RDRIV1 _IO_AT(0x0D);
+
+/*DEFINE REGISTER*/
+#define RDRIV RDRIV1.RDRIV_BYTE
+
+/*DEFINE REGISTER BITS*/
+#define RDPA RDRIV1.RDRIV_BITS._RDPA
+#define RDPB RDRIV1.RDRIV_BITS._RDPB
+#define RDPE RDRIV1.RDRIV_BITS._RDPE
+
+/**************************************************************************************************/
+/*                    INITIALIZATION OF INTERNAL RAM POSITION REGISTER                            */
+/**************************************************************************************************/
+
+__DECL__6812B32_H__ volatile union {
+  struct {
+    unsigned char BIT0:1;
+    unsigned char BIT1:1;
+    unsigned char BIT2:1;
+    unsigned char _RAM11:1;
+    unsigned char _RAM12:1;
+    unsigned char _RAM13:1;
+    unsigned char _RAM14:1;
+    unsigned char _RAM15:1;
+  } INITRM_BITS;
+  unsigned char INITRM_BYTE;
+}INITRM1 _IO_AT(0x10);
+
+/*DEFINE REGISTER*/
+#define INITRM INITRM1.INITRM_BYTE
+
+/*DEFINE REGISTER BITS*/
+#define RAM11 INITRM1.INITRM_BITS._RAM11
+#define RAM12 INITRM1.INITRM_BITS._RAM12
+#define RAM13 INITRM1.INITRM_BITS._RAM13
+#define RAM14 INITRM1.INITRM_BITS._RAM14
+#define RAM15 INITRM1.INITRM_BITS._RAM15
+
+/**************************************************************************************************/
+/*                    INITIALIZATION OF INTERNAL REGISTER POSITION REGISTER                       */
+/**************************************************************************************************/
+
+__DECL__6812B32_H__ volatile union {
+  struct {
+    unsigned char _MMSWAI:1;
+    unsigned char BIT1:1;
+    unsigned char BIT2:1;
+    unsigned char _REG11:1;
+    unsigned char _REG12:1;
+    unsigned char _REG13:1;
+    unsigned char _REG14:1;
+    unsigned char _REG15:1;
+  } INITRG_BITS;
+  unsigned char INITRG_BYTE;
+}INITRG1 _IO_AT(0x11);
+
+/*DEFINE REGISTER*/
+#define INITRG INITRG1.INITRG_BYTE
+
+/*DEFINE REGISTER BITS*/
+#define MMSWAI INITRG1.INITRG_BITS._MMSWAI
+#define REG11 INITRG1.INITRG_BITS._REG11
+#define REG12 INITRG1.INITRG_BITS._REG12
+#define REG13 INITRG1.INITRG_BITS._REG13
+#define REG14 INITRG1.INITRG_BITS._REG14
+#define REG15 INITRG1.INITRG_BITS._REG15
+
+/**************************************************************************************************/
+/*                    INITIALIZATION OF INTERNAL EEPROM POSITION REGISTER                         */
+/**************************************************************************************************/
+
+__DECL__6812B32_H__ volatile union {
+  struct {
+    unsigned char _EEON:1;
+    unsigned char BIT1:1;
+    unsigned char BIT2:1;
+    unsigned char BIT3:1;
+    unsigned char _EE12:1;
+    unsigned char _EE13:1;
+    unsigned char _EE14:1;
+    unsigned char _EE15:1;
+  } INITEE_BITS;
+  unsigned char INITEE_BYTE;
+}INITEE1 _IO_AT(0x12);
+
+/*DEFINE REGISTER*/
+#define INITEE INITEE1.INITEE_BYTE
+
+/*DEFINE REGISTER BITS*/
+#define EEON INITEE1.INITEE_BITS._EEON
+#define EE12 INITEE1.INITEE_BITS._EE12
+#define EE13 INITEE1.INITEE_BITS._EE13
+#define EE14 INITEE1.INITEE_BITS._EE14
+#define EE15 INITEE1.INITEE_BITS._EE15
+
+/**************************************************************************************************/
+/*                         MISCELLANEOUS MAPPING CONTROL REGISTER                                 */
+/**************************************************************************************************/
+
+__DECL__6812B32_H__ volatile union {
+  struct {
+    unsigned char _ROMON:1;
+    unsigned char _MAPROM:1;
+    unsigned char _EXSTR0:1;
+    unsigned char _EXSTR1:1;
+    unsigned char _RFSTR0:1;
+    unsigned char _RFSTR1:1;
+    unsigned char _NDRF:1;
+    unsigned char BIT7:1;
+  } MISC_BITS;
+  unsigned char MISC_BYTE;
+}MISC1 _IO_AT(0x13);
+
+/*DEFINE REGISTER*/
+#define MISC MISC1.MISC_BYTE
+
+/*DEFINE REGISTER BITS*/
+#define ROMON MISC1.MISC_BITS._ROMON
+#define MAPROM MISC1.MISC_BITS._MAPROM
+#define EXSTR0 MISC1.MISC_BITS._EXSTR0
+#define EXSTR1 MISC1.MISC_BITS._EXSTR1
+#define RFSTR0 MISC1.MISC_BITS._RFSTR0
+#define RFSTR1 MISC1.MISC_BITS._RFSTR1
+#define NDRF MISC1.MISC_BITS._NDRF
+
+/**************************************************************************************************/
+/*                                     REAL-TIME INTERRUPT ENABLE                                 */
+/**************************************************************************************************/
+
+__DECL__6812B32_H__ volatile union {
+  struct {
+    unsigned char _RTR0:1;
+    unsigned char _RTR1:1;
+    unsigned char _RTR2:1;
+    unsigned char _RTBYP:1;
+    unsigned char _BIT4:1;
+    unsigned char _RSBCK:1;
+    unsigned char _RSWAI:1;
+    unsigned char _RTIE:1;
+  } RTICTL_BITS;
+  unsigned char RTICTL_BYTE;
+}RTICTL1 _IO_AT(0x14);
+
+/*DEFINE REGISTER*/
+#define RTICTL RTICTL1.RTICTL_BYTE
+
+/*DEFINE REGISTER BITS*/
+#define RTR0 RTICTL1.RTICTL_BITS._RTR0
+#define RTR1 RTICTL1.RTICTL_BITS._RTR1
+#define RTR2 RTICTL1.RTICTL_BITS._RTR2
+#define RTBYP RTICTL1.RTICTL_BITS._RTBYP
+#define RSBCK RTICTL1.RTICTL_BITS._RSBCK
+#define RSWAI RTICTL1.RTICTL_BITS._RSWAI
+#define RTIE RTICTL1.RTICTL_BITS._RTIE
+
+/**************************************************************************************************/
+/*                                  REAL-TIME INTERRUPT FLAG REGISTER                             */
+/**************************************************************************************************/
+
+__DECL__6812B32_H__ volatile union {
+  struct {
+    unsigned char BIT0:1;
+    unsigned char BIT1:1;
+    unsigned char BIT2:1;
+    unsigned char BIT3:1;
+    unsigned char BIT4:1;
+    unsigned char BIT5:1;
+    unsigned char BIT6:1;
+    unsigned char _RTIF:1;
+  } RTIFLG_BITS;
+  unsigned char RTIFLG_BYTE;
+}RTIFLG1 _IO_AT(0x15);
+
+/*DEFINE REGISTER*/
+#define RTIFLG RTIFLG1.RTIFLG_BYTE
+
+/*DEFINE REGISTER BITS*/
+#define RTIF RTIFLG1.RTIFLG_BITS._RTIF
+
+
+/**************************************************************************************************/
+/*                                       COP CONTROL REGISTER                                     */
+/**************************************************************************************************/
+
+__DECL__6812B32_H__ volatile union {
+  struct {
+    unsigned char _CR0:1;
+    unsigned char _CR1:1;
+    unsigned char _CR2:1;
+    unsigned char _DISR:1;
+    unsigned char _FCOP:1;
+    unsigned char _FCM:1;
+    unsigned char _FCME:1;
+    unsigned char _CME:1;
+  } COPCTL_BITS;
+  unsigned char COPCTL_BYTE;
+}COPCTL1 _IO_AT(0x16);
+
+/*DEFINE REGISTER*/
+#define COPCTL COPCTL1.COPCTL_BYTE
+
+/*DEFINE REGISTER BITS*/
+#define CR0 COPCTL1.COPCTL_BITS._CR0
+#define CR1 COPCTL1.COPCTL_BITS._CR1
+#define CR2 COPCTL1.COPCTL_BITS._CR2
+#define DISR COPCTL1.COPCTL_BITS._DISR
+#define FCOP COPCTL1.COPCTL_BITS._FCOP
+#define FCM COPCTL1.COPCTL_BITS._FCM
+#define FCME COPCTL1.COPCTL_BITS._FCME
+#define CME COPCTL1.COPCTL_BITS._CME
+
+/**************************************************************************************************/
+/*                                 ARM/RESET COP TIMER REGISTER                                   */
+/**************************************************************************************************/
+
+__DECL__6812B32_H__ volatile  unsigned char COPRST   _IO_AT(0x17);  /* COP arm/reset */
+
+/**************************************************************************************************/
+/*                                   INTERRUPT TEST REGISTERS                                     */
+/**************************************************************************************************/
+
+__DECL__6812B32_H__ volatile  unsigned char ITST0    _IO_AT(0x18);  /* interrupt test 0 */
+__DECL__6812B32_H__ volatile  unsigned char ITST1    _IO_AT(0x19);  /* interrupt test 1 */
+__DECL__6812B32_H__ volatile  unsigned char ITST2    _IO_AT(0x1a);  /* interrupt test 2 */
+__DECL__6812B32_H__ volatile  unsigned char ITST3    _IO_AT(0x1b);  /* interrupt test 3 */
+
+/**************************************************************************************************/
+/*                                     INTERRUPT CONTROL REGISTER                                 */
+/**************************************************************************************************/
+
+__DECL__6812B32_H__ volatile union {
+  struct {
+    unsigned char BIT0:1;
+    unsigned char BIT1:1;
+    unsigned char BIT2:1;
+    unsigned char BIT3:1;
+    unsigned char BIT4:1;
+    unsigned char _DLY:1;
+    unsigned char _IRQEN:1;
+    unsigned char _IRQE:1;
+  } INTCR_BITS;
+  unsigned char INTCR_BYTE;
+}INTCR1 _IO_AT(0x1E);
+
+/*DEFINE REGISTER*/
+#define INTCR INTCR1.INTCR_BYTE
+
+/*DEFINE REGISTER BITS*/
+#define DLY   INTCR1.INTCR_BITS._DLY
+#define IRQEN INTCR1.INTCR_BITS._IRQEN
+#define IRQE  INTCR1.INTCR_BITS._IRQE
+
+/**************************************************************************************************/
+/*                                   HIGHEST PRIORITY I INTERRUPT                                 */
+/**************************************************************************************************/
+
+__DECL__6812B32_H__ volatile union {
+  struct {
+    unsigned char BIT0:1;
+    unsigned char _PSEL1:1;
+    unsigned char _PSEL2:1;
+    unsigned char _PSEL3:1;
+    unsigned char _PSEL4:1;
+    unsigned char _PSEL5:1;
+    unsigned char BIT6:1;
+    unsigned char BIT7:1;
+  } HPRIO_BITS;
+  unsigned char HPRIO_BYTE;
+}HPRIO1 _IO_AT(0x1F);
+
+/*DEFINE REGISTER*/
+#define HPRIO HPRIO1.HPRIO_BYTE
+
+/*DEFINE REGISTER BITS*/
+#define PSEL1 HPRIO1.HPRIO_BITS._PSEL1
+#define PSEL2 HPRIO1.HPRIO_BITS._PSEL2
+#define PSEL3 HPRIO1.HPRIO_BITS._PSEL3
+#define PSEL4 HPRIO1.HPRIO_BITS._PSEL4
+#define PSEL5 HPRIO1.HPRIO_BITS._PSEL5
+
+/**************************************************************************************************/
+/*                                   BREAKPOINT CONTROL REGISTER 0                                */
+/**************************************************************************************************/
+
+__DECL__6812B32_H__ volatile union {
+  struct {
+    unsigned char BIT0:1;
+    unsigned char BIT1:1;
+    unsigned char _BK0ALE:1;
+    unsigned char _BK1ALE:1;
+    unsigned char BIT4:1;
+    unsigned char _BKPM:1;
+    unsigned char _BKEN0:1;
+    unsigned char _BKEN1:1;
+  } BRKCT0_BITS;
+  unsigned char BRKCT0_BYTE;
+}BRKCT01 _IO_AT(0x20);
+
+/*DEFINE REGISTER*/
+#define BRKCT0 BRKCT01.BRKCT0_BYTE
+
+/*DEFINE REGISTER BITS*/
+#define BK0ALE BRKCT01.BRKCT0_BITS._BK0ALE
+#define BK1ALE BRKCT01.BRKCT0_BITS._BK1ALE
+#define BKPM   BRKCT01.BRKCT0_BITS._BKPM
+#define BKEN0  BRKCT01.BRKCT0_BITS._BKEN0
+#define BKEN1  BRKCT01.BRKCT0_BITS._BKEN1
+
+#define BR0ALE BK0ALE
+#define BR1ALE BK1ALE
+
+/*******************************************************************************************/
+/*                                   BREAKPOINT CONTROL REGISTER 1                         */
+/*******************************************************************************************/
+
+__DECL__6812B32_H__ volatile union {
+  struct {
+    unsigned char _BK0RW:1;
+    unsigned char _BK0RWE:1;
+    unsigned char _BK1RW:1;
+    unsigned char _BK1RWE:1;
+    unsigned char _BKMBL:1;
+    unsigned char _BKMBH:1;
+    unsigned char _BKDBE:1;
+    unsigned char BIT7:1;
+  } BRKCT1_BITS;
+  unsigned char BRKCT1_BYTE;
+}BRKCT11 _IO_AT(0x21);
+
+/*DEFINE REGISTER*/
+#define BRKCT1 BRKCT11.BRKCT1_BYTE
+
+/*DEFINE REGISTER BITS*/
+#define BK0RW  BRKCT11.BRKCT1_BITS._BK0RW
+#define BK0RWE BRKCT11.BRKCT1_BITS._BK0RWE
+#define BK1RW  BRKCT11.BRKCT1_BITS._BK1RW
+#define BK1RWE BRKCT11.BRKCT1_BITS._BK1RWE
+#define BKMBL  BRKCT11.BRKCT1_BITS._BKMBL
+#define BKMBH  BRKCT11.BRKCT1_BITS._BKMBH
+#define BKDBE  BRKCT11.BRKCT1_BITS._BKDBE
+
+/*******************************************************************************************/
+/*                           BREAKPOINT DATA AND ADDRESS REGISTERS                         */
+/*******************************************************************************************/
+
+__DECL__6812B32_H__ volatile  unsigned char BRKAH    _IO_AT(0x22);  /* Breakpoint Address Register, High Byte*/
+__DECL__6812B32_H__ volatile  unsigned char BRKAL    _IO_AT(0x23);  /* Breakpoint Address Register, Low Byte*/
+
+__DECL__6812B32_H__ volatile  unsigned char BRKDH     _IO_AT(0x24);  /* Breakpoint Data Register, High Byte*/
+__DECL__6812B32_H__ volatile  unsigned char BRKDL     _IO_AT(0x25);  /* Breakpoint Data Register, Low Byte*/
+
+/*******************************************************************************************/
+/*                              PWM CLOCKS AND CONCATENATE                                 */
+/*******************************************************************************************/
+
+__DECL__6812B32_H__ volatile union {
+  struct {
+    unsigned char _PCKB0:1;
+    unsigned char _PCKB1:1;
+    unsigned char _PCKB2:1;
+    unsigned char _PCKA0:1;
+    unsigned char _PCKA1:1;
+    unsigned char _PCKA2:1;
+    unsigned char _CON01:1;
+    unsigned char _CON02:1;
+  } PWCLK_BITS;
+  unsigned char PWCLK_BYTE;
+}PWCLK1 _IO_AT(0x40);
+
+/*DEFINE FOR THE COMPATIBILITY WITH OLD VERSION*/
+/*           "CKL" INSTEAD OF "CLK"           */
+#define PWCKL_BITS PWCLK_BITS
+#define PWCKL_BYTE PWCLK_BYTE
+#define PWCKL1 PWCLK1
+#define PWCKL  PWCLK
+
+/*DEFINE REGISTER*/
+#define PWCLK PWCLK1.PWCLK_BYTE
+
+/*DEFINE REGISTER BITS*/
+#define PCKB0 PWCLK1.PWCLK_BITS._PCKB0
+#define PCKB1 PWCLK1.PWCLK_BITS._PCKB1
+#define PCKB2 PWCLK1.PWCLK_BITS._PCKB2
+#define PCKA0 PWCLK1.PWCLK_BITS._PCKA0
+#define PCKA1 PWCLK1.PWCLK_BITS._PCKA1
+#define PCKA2 PWCLK1.PWCLK_BITS._PCKA2
+#define CON01 PWCLK1.PWCLK_BITS._CON01
+#define CON02 PWCLK1.PWCLK_BITS._CON02
+
+/*******************************************************************************************/
+/*                              PWM CLOCK SELECT AND POLARITY                              */
+/*******************************************************************************************/
+
+__DECL__6812B32_H__ volatile union {
+  struct {
+    unsigned char _PPOL0:1;
+    unsigned char _PPOL1:1;
+    unsigned char _PPOL2:1;
+    unsigned char _PPOL3:1;
+    unsigned char _PCLK0:1;
+    unsigned char _PCLK1:1;
+    unsigned char _PCLK2:1;
+    unsigned char _PCLK3:1;
+  } PWPOL_BITS;
+  unsigned char PWPOL_BYTE;
+}PWPOL1 _IO_AT(0x41);
+
+/*DEFINE REGISTER*/
+#define PWPOL PWPOL1.PWPOL_BYTE
+
+/*DEFINE REGISTER BITS*/
+#define PPOL0 PWPOL1.PWPOL_BITS._PPOL0
+#define PPOL1 PWPOL1.PWPOL_BITS._PPOL1
+#define PPOL2 PWPOL1.PWPOL_BITS._PPOL2
+#define PPOL3 PWPOL1.PWPOL_BITS._PPOL3
+#define PCLK0 PWPOL1.PWPOL_BITS._PCLK0
+#define PCLK1 PWPOL1.PWPOL_BITS._PCLK1
+#define PCLK2 PWPOL1.PWPOL_BITS._PCLK2
+#define PCLK3 PWPOL1.PWPOL_BITS._PCLK3
+
+/*******************************************************************************************/
+/*                                          PWM ENABLE                                     */
+/*******************************************************************************************/
+
+__DECL__6812B32_H__ volatile union {
+  struct {
+    unsigned char _PWEN0:1;
+    unsigned char _PWEN1:1;
+    unsigned char _PWEN2:1;
+    unsigned char _PWEN3:1;
+    unsigned char BIT4:1;
+    unsigned char BIT5:1;
+    unsigned char BIT6:1;
+    unsigned char BIT7:1;
+  } PWEN_BITS;
+  unsigned char PWEN_BYTE;
+}PWEN_1 _IO_AT(0x42);
+
+/*DEFINE REGISTER*/
+#define PWEN PWEN_1.PWEN_BYTE
+
+/*DEFINE REGISTER BITS*/
+#define PWEN0 PWEN_1.PWEN_BITS._PWEN0
+#define PWEN1 PWEN_1.PWEN_BITS._PWEN1
+#define PWEN2 PWEN_1.PWEN_BITS._PWEN2
+#define PWEN3 PWEN_1.PWEN_BITS._PWEN3
+
+/*******************************************************************************************/
+/*                                 PWM PRESCALE COUNTER                                    */
+/*******************************************************************************************/
+
+__DECL__6812B32_H__ volatile  unsigned char PWPRES   _IO_AT(0x43);  /* PWM Prescale Counter */
+
+/*******************************************************************************************/
+/*                                 PWM SCALE REGISTER 0                                    */
+/*******************************************************************************************/
+
+__DECL__6812B32_H__ volatile  unsigned char PWSCAL0  _IO_AT(0x44); /* PWM Scale 0 */
+
+/*******************************************************************************************/
+/*                                 PWM SCALE COUNTER VALUE 0                               */
+/*******************************************************************************************/
+
+__DECL__6812B32_H__ volatile  unsigned char PWSCNT0  _IO_AT(0x45); /* PWM Counter 0 */
+
+/*******************************************************************************************/
+/*                                 PWM SCALE REGISTER 1                                    */
+/*******************************************************************************************/
+
+__DECL__6812B32_H__ volatile  unsigned char PWSCAL1  _IO_AT(0x46); /* PWM Scale 1 */
+
+/*******************************************************************************************/
+/*                                 PWM SCALE COUNTER VALUE 1                               */
+/*******************************************************************************************/
+
+__DECL__6812B32_H__ volatile  unsigned char PWSCNT1  _IO_AT(0x47); /* PWM Counter 1 */
+
+/*******************************************************************************************/
+/*                                      PWM CHANNEL COUNTERS                               */
+/*******************************************************************************************/
+
+__DECL__6812B32_H__ volatile  unsigned char PWCNT0   _IO_AT(0x48);  /* PWM Channel Counter 0 */
+__DECL__6812B32_H__ volatile  unsigned char PWCNT1   _IO_AT(0x49);  /* PWM Channel Counter 1 */
+__DECL__6812B32_H__ volatile  unsigned char PWCNT2   _IO_AT(0x4a);  /* PWM Channel Counter 2 */
+__DECL__6812B32_H__ volatile  unsigned char PWCNT3   _IO_AT(0x4b);  /* PWM Channel Counter 3 */
+
+/*******************************************************************************************/
+/*                              PWM CHANNEL PERIOD REGISTERS                               */
+/*******************************************************************************************/
+
+__DECL__6812B32_H__ volatile  unsigned char PWPER0   _IO_AT(0x4c);  /* PWM Channel Period 0 */
+__DECL__6812B32_H__ volatile  unsigned char PWPER1   _IO_AT(0x4d);  /* PWM Channel Period 1 */
+__DECL__6812B32_H__ volatile  unsigned char PWPER2   _IO_AT(0x4e);  /* PWM Channel Period 2 */
+__DECL__6812B32_H__ volatile  unsigned char PWPER3   _IO_AT(0x4f);  /* PWM Channel Period 3 */
+
+/*******************************************************************************************/
+/*                                PWM CHANNEL DUTY REGISTERS                               */
+/*******************************************************************************************/
+
+__DECL__6812B32_H__ volatile  unsigned char PWDTY0   _IO_AT(0x50);  /* PWM Channel Duty 0 */
+__DECL__6812B32_H__ volatile  unsigned char PWDTY1   _IO_AT(0x51);  /* PWM Channel Duty 1 */
+__DECL__6812B32_H__ volatile  unsigned char PWDTY2   _IO_AT(0x52);  /* PWM Channel Duty 2 */
+__DECL__6812B32_H__ volatile  unsigned char PWDTY3   _IO_AT(0x53);  /* PWM Channel Duty 3 */
+
+/*******************************************************************************************/
+/*                                PWM CONTROL REGISTER                                     */
+/*******************************************************************************************/
+
+__DECL__6812B32_H__ volatile union {
+  struct {
+    unsigned char _PSBCK:1;
+    unsigned char _PUPP:1;
+    unsigned char _RDPP:1;
+    unsigned char _CENTR:1;
+    unsigned char _PSWAI:1;
+    unsigned char BIT5:1;
+    unsigned char BIT6:1;
+    unsigned char BIT7:1;
+  } PWCTL_BITS;
+  unsigned char PWCTL_BYTE;
+}PWCTL1 _IO_AT(0x54);
+
+/*DEFINE REGISTER*/
+#define PWCTL PWCTL1.PWCTL_BYTE
+
+/*DEFINE REGISTER BITS*/
+#define PSBCK PWCTL1.PWCTL_BITS._PSBCK
+#define PUPP  PWCTL1.PWCTL_BITS._PUPP
+#define RDPP  PWCTL1.PWCTL_BITS._RDPP
+#define CENTR PWCTL1.PWCTL_BITS._CENTR
+#define PSWAI PWCTL1.PWCTL_BITS._PSWAI
+
+/*******************************************************************************************/
+/*                              PWM SPECIAL MODE REGISTER (TEST)                           */
+/*******************************************************************************************/
+
+__DECL__6812B32_H__ volatile union {
+  struct {
+    unsigned char BIT0:1;
+    unsigned char BIT1:1;
+    unsigned char BIT2:1;
+    unsigned char BIT3:1;
+    unsigned char BIT4:1;
+    unsigned char _DISCAL:1;
+    unsigned char _DISCP:1;
+    unsigned char _DISCR:1;
+  } PWTST_BITS;
+  unsigned char PWTST_BYTE;
+}PWTST1 _IO_AT(0x55);
+
+/*DEFINE REGISTER*/
+#define PWTST PWTST1.PWTST_BYTE
+
+/*DEFINE REGISTER BITS*/
+#define DISCAL PWTST1.PWTST_BITS._DISCAL
+#define DISCP PWTST1.PWTST_BITS._DISCP
+#define DISCR PWTST1.PWTST_BITS._DISCR
+
+/**************************************************************************************************/
+/*                                         DEFINE PORT P                                          */
+/**************************************************************************************************/
+
+__DECL__6812B32_H__ volatile  unsigned char PORTP    _IO_AT(0x56);  /* port P */
+
+__DECL__6812B32_H__ volatile  unsigned char DDRP    _IO_AT(0x57);  /* data direction port P */
+
+/**************************************************************************************************/
+/*                                   ATD RESERVED REGISTERS                                       */
+/**************************************************************************************************/
+
+__DECL__6812B32_H__ volatile  unsigned char ATDCTL0  _IO_AT(0x60); /* A/D control register 0 */
+__DECL__6812B32_H__ volatile  unsigned char ATDCTL1  _IO_AT(0x61); /* A/D control register 1 */
+
+/**************************************************************************************************/
+/*                                    ATD CONTROL REGISTERS                                       */
+/**************************************************************************************************/
+
+/**********ATD CONTROL REGISTER 2********/
+__DECL__6812B32_H__ volatile union {
+  struct {
+    unsigned char _ASCIF:1;
+    unsigned char _ASCIE:1;
+    unsigned char BIT2:1;
+    unsigned char BIT3:1;
+    unsigned char BIT4:1;
+    unsigned char _ASWAI:1;
+    unsigned char _AFFC:1;
+    unsigned char _ADPU:1;
+  } ATDCTL2_BITS;
+  unsigned char ATDCTL2_BYTE;
+}ATDCTL21 _IO_AT(0x62);
+
+/*DEFINE REGISTER*/
+#define ATDCTL2 ATDCTL21.ATDCTL2_BYTE
+
+/*DEFINE REGISTER BITS*/
+#define ASCIF ATDCTL21.ATDCTL2_BITS._ASCIF
+#define ASCIE ATDCTL21.ATDCTL2_BITS._ASCIE
+#define ASWAI ATDCTL21.ATDCTL2_BITS._ASWAI
+#define AFFC ATDCTL21.ATDCTL2_BITS._AFFC
+#define ADPU ATDCTL21.ATDCTL2_BITS._ADPU
+
+/**********ATD CONTROL REGISTER 3********/
+
+__DECL__6812B32_H__ volatile union {
+  struct {
+    unsigned char _FRZ0:1;
+    unsigned char _FRZ1:1;
+    unsigned char BIT2:1;
+    unsigned char BIT3:1;
+    unsigned char BIT4:1;
+    unsigned char BIT5:1;
+    unsigned char BIT6:1;
+    unsigned char BIT7:1;
+  } ATDCTL3_BITS;
+  unsigned char ATDCTL3_BYTE;
+}ATDCTL31 _IO_AT(0x63);
+
+/*DEFINE REGISTER*/
+#define ATDCTL3 ATDCTL31.ATDCTL3_BYTE
+
+/*DEFINE REGISTER BITS*/
+#define FRZ0 ATDCTL31.ATDCTL3_BITS._FRZ0
+#define FRZ1 ATDCTL31.ATDCTL3_BITS._FRZ1
+
+/**********ATD CONTROL REGISTER 4********/
+
+__DECL__6812B32_H__ volatile union {
+  struct {
+    unsigned char _PRS0:1;
+    unsigned char _PRS1:1;
+    unsigned char _PRS2:1;
+    unsigned char _PRS3:1;
+    unsigned char _PRS4:1;
+    unsigned char _SMP0:1;
+    unsigned char _SMP1:1;
+    unsigned char BIT7:1;
+  } ATDCTL4_BITS;
+  unsigned char ATDCTL4_BYTE;
+}ATDCTL41 _IO_AT(0x64);
+
+/*DEFINE REGISTER*/
+#define ATDCTL4 ATDCTL41.ATDCTL4_BYTE
+
+/*DEFINE REGISTER BITS*/
+#define PRS0 ATDCTL41.ATDCTL4_BITS._PRS0
+#define PRS1 ATDCTL41.ATDCTL4_BITS._PRS1
+#define PRS2 ATDCTL41.ATDCTL4_BITS._PRS2
+#define PRS3 ATDCTL41.ATDCTL4_BITS._PRS3
+#define PRS4 ATDCTL41.ATDCTL4_BITS._PRS4
+#define SMP0 ATDCTL41.ATDCTL4_BITS._SMP0
+#define SMP1 ATDCTL41.ATDCTL4_BITS._SMP1
+
+/**********ATD CONTROL REGISTER 5********/
+
+__DECL__6812B32_H__ volatile union {
+  struct {
+    unsigned char _CA:1;
+    unsigned char _CB:1;
+    unsigned char _CC:1;
+    unsigned char _CD:1;
+    unsigned char _MULT:1;
+    unsigned char _SCAN:1;
+    unsigned char _S8CM:1;
+    unsigned char BIT7:1;
+  } ATDCTL5_BITS;
+  unsigned char ATDCTL5_BYTE;
+}ATDCTL51 _IO_AT(0x65);
+
+/*DEFINE REGISTER*/
+#define ATDCTL5 ATDCTL51.ATDCTL5_BYTE
+
+/*DEFINE REGISTER BITS*/
+#define CA ATDCTL51.ATDCTL5_BITS._CA
+#define CB ATDCTL51.ATDCTL5_BITS._CB
+#define CC ATDCTL51.ATDCTL5_BITS._CC
+#define CD ATDCTL51.ATDCTL5_BITS._CD
+#define MULT ATDCTL51.ATDCTL5_BITS._MULT
+#define SCAN ATDCTL51.ATDCTL5_BITS._SCAN
+#define S8CM ATDCTL51.ATDCTL5_BITS._S8CM
+
+/**************************************************************************************************/
+/*                                    ATD STATUS REGISTER                                         */
+/**************************************************************************************************/
+
+__DECL__6812B32_H__ volatile union {
+  struct {
+    unsigned int  _CC0:1;
+    unsigned int  _CC1:1;
+    unsigned int  _CC2:1;
+    unsigned int  BIT3:1;
+    unsigned int  BIT4:1;
+    unsigned int  BIT5:1;
+    unsigned int  BIT6:1;
+    unsigned int  _SCF:1;
+    unsigned int  _CCF0:1;
+    unsigned int  _CCF1:1;
+    unsigned int  _CCF2:1;
+    unsigned int  _CCF3:1;
+    unsigned int  _CCF4:1;
+    unsigned int  _CCF5:1;
+    unsigned int  _CCF6:1;
+    unsigned int  _CCF7:1;
+  } ATDSTAT_BITS;
+  unsigned int ATDSTAT_WORD;
+}ATDSTAT1 _IO_AT(0x66);
+
+/*DEFINE REGISTER*/
+#define ATDSTAT ATDSTAT1.ATDSTAT_WORD
+
+/*DEFINE REGISTER BITS*/
+#define CC0 ATDSTAT1.ATDSTAT_BITS._CC0
+#define CC1 ATDSTAT1.ATDSTAT_BITS._CC1
+#define CC2 ATDSTAT1.ATDSTAT_BITS._CC2
+#define SCF ATDSTAT1.ATDSTAT_BITS._SCF
+#define CCF0 ATDSTAT1.ATDSTAT_BITS._CCF0
+#define CCF1 ATDSTAT1.ATDSTAT_BITS._CCF1
+#define CCF2 ATDSTAT1.ATDSTAT_BITS._CCF2
+#define CCF3 ATDSTAT1.ATDSTAT_BITS._CCF3
+#define CCF4 ATDSTAT1.ATDSTAT_BITS._CCF4
+#define CCF5 ATDSTAT1.ATDSTAT_BITS._CCF5
+#define CCF6 ATDSTAT1.ATDSTAT_BITS._CCF6
+#define CCF7 ATDSTAT1.ATDSTAT_BITS._CCF7
+
+/*******************************************************************************************/
+/*                                        ATD TEST REGISTER                                */
+/*******************************************************************************************/
+
+/********ATD TEST REGISTER HIGH*********/
+
+__DECL__6812B32_H__ volatile union {
+  struct {
+    unsigned char _SAR2:1;
+    unsigned char _SAR3:1;
+    unsigned char _SAR4:1;
+    unsigned char _SAR5:1;
+    unsigned char _SAR6:1;
+    unsigned char _SAR7:1;
+    unsigned char _SAR8:1;
+    unsigned char _SAR9:1;
+  } ATDTSTH_BITS;
+  unsigned char ATDTSTH_BYTE;
+} ATDTSTH1 _IO_AT(0x68);
+
+/*DEFINE REGISTER*/
+#define ATDTSTH ATDTSTH1.ATDTSTH_BYTE
+
+/*DEFINE REGISTER BITS*/
+#define SAR2 ATDTSTH1.ATDTSTH_BITS._SAR2
+#define SAR3 ATDTSTH1.ATDTSTH_BITS._SAR3
+#define SAR4 ATDTSTH1.ATDTSTH_BITS._SAR4
+#define SAR5 ATDTSTH1.ATDTSTH_BITS._SAR5
+#define SAR6 ATDTSTH1.ATDTSTH_BITS._SAR6
+#define SAR7 ATDTSTH1.ATDTSTH_BITS._SAR7
+#define SAR8 ATDTSTH1.ATDTSTH_BITS._SAR8
+#define SAR9 ATDTSTH1.ATDTSTH_BITS._SAR9
+
+
+/********ATD TEST REGISTER LOW**********/
+
+__DECL__6812B32_H__ volatile union {
+  struct {
+    unsigned char _TST0:1;
+    unsigned char _TST1:1;
+    unsigned char _TST2:1;
+    unsigned char _TST3:1;
+    unsigned char _TSTOUT:1;
+    unsigned char _RST:1;
+    unsigned char _SAR0:1;
+    unsigned char _SAR1:1;
+  } ATDTSTL_BITS;
+  unsigned char ATDTSTL_BYTE;
+} ATDTSTL1 _IO_AT(0x69);
+
+/*DEFINE REGISTER*/
+#define ATDTSTL ATDTSTL1.ATDTSTL_BYTE
+
+/*DEFINE REGISTER BITS*/
+#define TST0   ATDTSTL1.ATDTSTL_BITS._TST0
+#define TST1   ATDTSTL1.ATDTSTL_BITS._TST1
+#define TST2   ATDTSTL1.ATDTSTL_BITS._TST2
+#define TST3   ATDTSTL1.ATDTSTL_BITS._TST3
+#define TSTOUT ATDTSTL1.ATDTSTL_BITS._TSTOUT
+#define RST    ATDTSTL1.ATDTSTL_BITS._RST
+#define SAR0   ATDTSTL1.ATDTSTL_BITS._SAR0
+#define SAR1   ATDTSTL1.ATDTSTL_BITS._SAR1
+
+/*******************************************************************************************/
+/*                                 PORT AD DATA INPUT REGISTER                             */
+/*******************************************************************************************/
+
+__DECL__6812B32_H__ volatile  unsigned char PORTAD   _IO_AT(0x6f); /* port AD data input register */
+
+/*******************************************************************************************/
+/*                              ADT CONVERTER RESULT REGISTERS                             */
+/*******************************************************************************************/
+
+__DECL__6812B32_H__ volatile  unsigned char ADR0H    _IO_AT(0x70); /* A/D result 0 */
+__DECL__6812B32_H__ volatile  unsigned char ADR1H    _IO_AT(0x72); /* A/D result 1 */
+__DECL__6812B32_H__ volatile  unsigned char ADR2H    _IO_AT(0x74); /* A/D result 2 */
+__DECL__6812B32_H__ volatile  unsigned char ADR3H    _IO_AT(0x76); /* A/D result 3 */
+__DECL__6812B32_H__ volatile  unsigned char ADR4H    _IO_AT(0x78); /* A/D result 4 */
+__DECL__6812B32_H__ volatile  unsigned char ADR5H    _IO_AT(0x7a); /* A/D result 5 */
+__DECL__6812B32_H__ volatile  unsigned char ADR6H    _IO_AT(0x7c); /* A/D result 6 */
+__DECL__6812B32_H__ volatile  unsigned char ADR7H    _IO_AT(0x7e); /* A/D result 7 */
+
+/*******************************************************************************************/
+/*                           TIMER INPUT/OUTPUT COMPARE SELECT                             */
+/*******************************************************************************************/
+
+__DECL__6812B32_H__ volatile  unsigned char TIOS     _IO_AT(0x80);
+
+/*******************************************************************************************/
+/*                          TIMER COMPARE FORCE REGISTER                                  */
+/*******************************************************************************************/
+
+__DECL__6812B32_H__ volatile  unsigned char CFORC    _IO_AT(0x81);
+
+/*******************************************************************************************/
+/*                         OUTPUT COMPARE 7 MASK REGISTER                                  */
+/*******************************************************************************************/
+
+__DECL__6812B32_H__ volatile  unsigned char OC7M     _IO_AT(0x82);
+
+/*******************************************************************************************/
+/*                         OUTPUT COMPARE 7 DATA REGISTER                                  */
+/*******************************************************************************************/
+
+__DECL__6812B32_H__ volatile  unsigned char OC7D     _IO_AT(0x83);
+
+/*******************************************************************************************/
+/*                         OUTPUT COMPARE 7 DATA REGISTER                                  */
+/*******************************************************************************************/
+
+__DECL__6812B32_H__ volatile  unsigned int TCNT     _IO_AT(0x84);
+
+/*******************************************************************************************/
+/*                                TIMER SYSTEM CONTROL REGISTER                            */
+/*******************************************************************************************/
+
+__DECL__6812B32_H__ volatile union {
+  struct {
+    unsigned char BIT0:1;
+    unsigned char BIT1:1;
+    unsigned char BIT2:1;
+    unsigned char BIT3:1;
+    unsigned char _TFFCA:1;
+    unsigned char _TSBCK:1;
+    unsigned char _TSWAI:1;
+    unsigned char _TEN:1;
+  } TSCR_BITS;
+  unsigned char TSCR_BYTE;
+} TSCR1 _IO_AT(0x86);
+
+/*DEFINE REGISTER*/
+#define TSCR TSCR1.TSCR_BYTE
+
+/*DEFINE REGISTER BITS*/
+#define TFFCA TSCR1.TSCR_BITS._TFFCA
+#define TSBCK TSCR1.TSCR_BITS._TSBCK
+#define TSWAI TSCR1.TSCR_BITS._TSWAI
+#define TEN TSCR1.TSCR_BITS._TEN
+
+/*******************************************************************************************/
+/*                         TIMER QUEUE CONTROL REGISTER (RESERVED)                         */
+/*******************************************************************************************/
+
+__DECL__6812B32_H__ volatile  unsigned char TQCR     _IO_AT(0x87);  /* timer queue control */
+
+/*******************************************************************************************/
+/*                                TIMER CONTROL REGISTER 1                                 */
+/*******************************************************************************************/
+
+__DECL__6812B32_H__ volatile union {
+  struct {
+    unsigned char _OL4:1;
+    unsigned char _OM4:1;
+    unsigned char _OL5:1;
+    unsigned char _OM5:1;
+    unsigned char _OL6:1;
+    unsigned char _OM6:1;
+    unsigned char _OL7:1;
+    unsigned char _OM7:1;
+  } TCTL1_BITS;
+  unsigned char TCTL1_BYTE;
+} TCTL11 _IO_AT(0x88);
+
+/*DEFINE REGISTER*/
+#define TCTL1 TCTL11.TCTL1_BYTE
+
+/*DEFINE REGISTER BITS*/
+#define OL4 TCTL11.TCTL1_BITS._OL4
+#define OM4 TCTL11.TCTL1_BITS._OM4
+#define OL5 TCTL11.TCTL1_BITS._OL5
+#define OM5 TCTL11.TCTL1_BITS._OM5
+#define OL6 TCTL11.TCTL1_BITS._OL6
+#define OM6 TCTL11.TCTL1_BITS._OM6
+#define OL7 TCTL11.TCTL1_BITS._OL7
+#define OM7 TCTL11.TCTL1_BITS._OM7
+
+/*******************************************************************************************/
+/*                                TIMER CONTROL REGISTER 2                                 */
+/*******************************************************************************************/
+
+__DECL__6812B32_H__ volatile union {
+  struct {
+    unsigned char _OL0:1;
+    unsigned char _OM0:1;
+    unsigned char _OL1:1;
+    unsigned char _OM1:1;
+    unsigned char _OL2:1;
+    unsigned char _OM2:1;
+    unsigned char _OL3:1;
+    unsigned char _OM3:1;
+  } TCTL2_BITS;
+  unsigned char TCTL2_BYTE;
+} TCTL21 _IO_AT(0x89);
+
+/*DEFINE REGISTER*/
+#define TCTL2 TCTL21.TCTL2_BYTE
+
+/*DEFINE REGISTER BITS*/
+#define OL0 TCTL21.TCTL2_BITS._OL0
+#define OM0 TCTL21.TCTL2_BITS._OM0
+#define OL1 TCTL21.TCTL2_BITS._OL1
+#define OM1 TCTL21.TCTL2_BITS._OM1
+#define OL2 TCTL21.TCTL2_BITS._OL2
+#define OM2 TCTL21.TCTL2_BITS._OM2
+#define OL3 TCTL21.TCTL2_BITS._OL3
+#define OM3 TCTL21.TCTL2_BITS._OM3
+
+/*******************************************************************************************/
+/*                                TIMER CONTROL REGISTER 3                                 */
+/*******************************************************************************************/
+
+__DECL__6812B32_H__ volatile union {
+  struct {
+    unsigned char _EDG4A:1;
+    unsigned char _EDG4B:1;
+    unsigned char _EDG5A:1;
+    unsigned char _EDG5B:1;
+    unsigned char _EDG6A:1;
+    unsigned char _EDG6B:1;
+    unsigned char _EDG7A:1;
+    unsigned char _EDG7B:1;
+  } TCTL3_BITS;
+  unsigned char TCTL3_BYTE;
+} TCTL31 _IO_AT(0x8A);
+
+/*DEFINE REGISTER*/
+#define TCTL3 TCTL31.TCTL3_BYTE
+
+/*DEFINE REGISTER BITS*/
+#define EDG4A TCTL31.TCTL3_BITS._EDG4A
+#define EDG4B TCTL31.TCTL3_BITS._EDG4B
+#define EDG5A TCTL31.TCTL3_BITS._EDG5A
+#define EDG5B TCTL31.TCTL3_BITS._EDG5B
+#define EDG6A TCTL31.TCTL3_BITS._EDG6A
+#define EDG6B TCTL31.TCTL3_BITS._EDG6B
+#define EDG7A TCTL31.TCTL3_BITS._EDG7A
+#define EDG7B TCTL31.TCTL3_BITS._EDG7B
+
+/*******************************************************************************************/
+/*                                TIMER CONTROL REGISTER 4                                 */
+/*******************************************************************************************/
+
+__DECL__6812B32_H__ volatile union {
+  struct {
+    unsigned char _EDG0A:1;
+    unsigned char _EDG0B:1;
+    unsigned char _EDG1A:1;
+    unsigned char _EDG1B:1;
+    unsigned char _EDG2A:1;
+    unsigned char _EDG2B:1;
+    unsigned char _EDG3A:1;
+    unsigned char _EDG3B:1;
+  } TCTL4_BITS;
+  unsigned char TCTL4_BYTE;
+} TCTL41 _IO_AT(0x8B);
+
+/*DEFINE REGISTER*/
+#define TCTL4 TCTL41.TCTL4_BYTE
+
+/*DEFINE REGISTER BITS*/
+#define EDG0A TCTL41.TCTL4_BITS._EDG0A
+#define EDG0B TCTL41.TCTL4_BITS._EDG0B
+#define EDG1A TCTL41.TCTL4_BITS._EDG1A
+#define EDG1B TCTL41.TCTL4_BITS._EDG1B
+#define EDG2A TCTL41.TCTL4_BITS._EDG2A
+#define EDG2B TCTL41.TCTL4_BITS._EDG2B
+#define EDG3A TCTL41.TCTL4_BITS._EDG3A
+#define EDG3B TCTL41.TCTL4_BITS._EDG3B
+
+/*******************************************************************************************/
+/*                                TIMER INTERRUPT MASK 1                                   */
+/*******************************************************************************************/
+
+__DECL__6812B32_H__ volatile union {
+  struct {
+    unsigned char _C0I:1;
+    unsigned char _C1I:1;
+    unsigned char _C2I:1;
+    unsigned char _C3I:1;
+    unsigned char _C4I:1;
+    unsigned char _C5I:1;
+    unsigned char _C6I:1;
+    unsigned char _C7I:1;
+  } TMSK1_BITS;
+  unsigned char TMSK1_BYTE;
+} TMSK11 _IO_AT(0x8C);
+
+/*DEFINE REGISTER*/
+#define TMSK1 TMSK11.TMSK1_BYTE
+
+/*DEFINE REGISTER BITS*/
+#define C0I TMSK11.TMSK1_BITS._C0I
+#define C1I TMSK11.TMSK1_BITS._C1I
+#define C2I TMSK11.TMSK1_BITS._C2I
+#define C3I TMSK11.TMSK1_BITS._C3I
+#define C4I TMSK11.TMSK1_BITS._C4I
+#define C5I TMSK11.TMSK1_BITS._C5I
+#define C6I TMSK11.TMSK1_BITS._C6I
+#define C7I TMSK11.TMSK1_BITS._C7I
+
+/*******************************************************************************************/
+/*                                TIMER INTERRUPT MASK 2                                   */
+/*******************************************************************************************/
+
+__DECL__6812B32_H__ volatile union {
+  struct {
+    unsigned char _PR0:1;
+    unsigned char _PR1:1;
+    unsigned char _PR2:1;
+    unsigned char _TCRE:1;
+    unsigned char _RDPT:1;
+    unsigned char _PUPT:1;
+    unsigned char _BIT6:1;
+    unsigned char _TOI:1;
+  } TMSK2_BITS;
+  unsigned char TMSK2_BYTE;
+} TMSK21 _IO_AT(0x8D);
+
+/*DEFINE REGISTER*/
+#define TMSK2 TMSK21.TMSK2_BYTE
+
+/*DEFINE REGISTER BITS*/
+#define PR0 TMSK21.TMSK2_BITS._PR0
+#define PR1 TMSK21.TMSK2_BITS._PR1
+#define PR2 TMSK21.TMSK2_BITS._PR2
+#define TCRE TMSK21.TMSK2_BITS._TCRE
+#define RDPT TMSK21.TMSK2_BITS._RDPT
+#define PUPT TMSK21.TMSK2_BITS._PUPT
+#define TOI TMSK21.TMSK2_BITS._TOI
+
+/*******************************************************************************************/
+/*                                TIMER INTERRUPT FLAG 1                                   */
+/*******************************************************************************************/
+
+__DECL__6812B32_H__ volatile union {
+  struct {
+    unsigned char _C0F:1;
+    unsigned char _C1F:1;
+    unsigned char _C2F:1;
+    unsigned char _C3F:1;
+    unsigned char _C4F:1;
+    unsigned char _C5F:1;
+    unsigned char _C6F:1;
+    unsigned char _C7F:1;
+  } TFLG1_BITS;
+  unsigned char TFLG1_BYTE;
+} TFLG11 _IO_AT(0x8E);
+
+/*DEFINE REGISTER*/
+#define TFLG1 TFLG11.TFLG1_BYTE
+
+/*DEFINE REGISTER BITS*/
+#define C0F TFLG11.TFLG1_BITS._C0F
+#define C1F TFLG11.TFLG1_BITS._C1F
+#define C2F TFLG11.TFLG1_BITS._C2F
+#define C3F TFLG11.TFLG1_BITS._C3F
+#define C4F TFLG11.TFLG1_BITS._C4F
+#define C5F TFLG11.TFLG1_BITS._C5F
+#define C6F TFLG11.TFLG1_BITS._C6F
+#define C7F TFLG11.TFLG1_BITS._C7F
+
+/*******************************************************************************************/
+/*                                TIMER INTERRUPT FLAG 2                                   */
+/*******************************************************************************************/
+
+__DECL__6812B32_H__ volatile union {
+  struct {
+    unsigned char BIT0:1;
+    unsigned char BIT1:1;
+    unsigned char BIT2:1;
+    unsigned char BIT3:1;
+    unsigned char BIT4:1;
+    unsigned char BIT5:1;
+    unsigned char BIT6:1;
+    unsigned char _TOF:1;
+  } TFLG2_BITS;
+  unsigned char TFLG2_BYTE;
+} TFLG21 _IO_AT(0x8F);
+
+/*DEFINE REGISTER*/
+#define TFLG2 TFLG21.TFLG2_BYTE
+
+/*DEFINE REGISTER BITS*/
+#define TOF TFLG21.TFLG2_BITS._TOF
+
+/*******************************************************************************************/
+/*                         TIMER INPUT CAPTURE/OUTPUT REGISTERS                            */
+/*******************************************************************************************/
+
+/*****TIMER INPUT CAPTURE/OUTPUT REGISTER 0*****/
+__DECL__6812B32_H__ volatile  unsigned int TC0      _IO_AT(0x90);
+
+
+/*****TIMER INPUT CAPTURE/OUTPUT REGISTER 1*****/
+__DECL__6812B32_H__ volatile  unsigned int TC1      _IO_AT(0x92);
+
+
+/*****TIMER INPUT CAPTURE/OUTPUT REGISTER 2*****/
+__DECL__6812B32_H__ volatile  unsigned int TC2      _IO_AT(0x94);
+
+
+/*****TIMER INPUT CAPTURE/OUTPUT REGISTER 3*****/
+__DECL__6812B32_H__ volatile  unsigned int TC3      _IO_AT(0x96);
+
+
+/*****TIMER INPUT CAPTURE/OUTPUT REGISTER 4*****/
+__DECL__6812B32_H__ volatile  unsigned int TC4      _IO_AT(0x98);
+
+
+/*****TIMER INPUT CAPTURE/OUTPUT REGISTER 5*****/
+__DECL__6812B32_H__ volatile  unsigned int TC5      _IO_AT(0x9a);
+
+
+/*****TIMER INPUT CAPTURE/OUTPUT REGISTER 6*****/
+__DECL__6812B32_H__ volatile  unsigned int TC6      _IO_AT(0x9c);
+
+
+/*****TIMER INPUT CAPTURE/OUTPUT REGISTER 7*****/
+__DECL__6812B32_H__ volatile  unsigned int TC7      _IO_AT(0x9e);
+
+/*******************************************************************************************/
+/*                        PULSE ACCUMULATOR CONTROL REGISTER                               */
+/*******************************************************************************************/
+
+__DECL__6812B32_H__ volatile union {
+  struct {
+    unsigned char _PAI:1;
+    unsigned char _PAOVI:1;
+    unsigned char _CLOCK0:1;
+    unsigned char _CLOCK1:1;
+    unsigned char _PEDGE:1;
+    unsigned char _PAMOD:1;
+    unsigned char _PAEN:1;
+    unsigned char BIT7:1;
+  } PACTL_BITS;
+  unsigned char PACTL_BYTE;
+} PACTL1 _IO_AT(0xA0);
+
+/*DEFINE REGISTER*/
+#define PACTL PACTL1.PACTL_BYTE
+
+/*DEFINE REGISTER BITS*/
+#define PAI PACTL1.PACTL_BITS._PAI
+#define PAOVI PACTL1.PACTL_BITS._PAOVI
+#define CLOCK0 PACTL1.PACTL_BITS._CLOCK0
+#define CLOCK1 PACTL1.PACTL_BITS._CLOCK1
+#define PEDGE PACTL1.PACTL_BITS._PEDGE
+#define PAMOD PACTL1.PACTL_BITS._PAMOD
+#define PAEN PACTL1.PACTL_BITS._PAEN
+
+/*******************************************************************************************/
+/*                         PULSE ACCUMULATOR FLAG REGISTER                                 */
+/*******************************************************************************************/
+
+__DECL__6812B32_H__ volatile union {
+  struct {
+    unsigned char _PAIF:1;
+    unsigned char _PAOVF:1;
+    unsigned char BIT2:1;
+    unsigned char BIT3:1;
+    unsigned char BIT4:1;
+    unsigned char BIT5:1;
+    unsigned char BIT6:1;
+    unsigned char BIT7:1;
+  } PAFLG_BITS;
+  unsigned char PAFLG_BYTE;
+} PAFLG1 _IO_AT(0xA1);
+
+/*DEFINE REGISTER*/
+#define PAFLG PAFLG1.PAFLG_BYTE
+
+/*DEFINE REGISTER BITS*/
+#define PAIF PAFLG1.PAFLG_BITS._PAIF
+#define PAOVF PAFLG1.PAFLG_BITS._PAOVF
+
+/*******************************************************************************************/
+/*                      16-BITS PULSE ACCUMULATOR COUNT REGISTER                           */
+/*******************************************************************************************/
+
+__DECL__6812B32_H__ volatile  unsigned int PACNT    _IO_AT(0xa2);
+
+/*******************************************************************************************/
+/*                                  TIMER TEST REGISTER                                    */
+/*******************************************************************************************/
+
+__DECL__6812B32_H__ volatile union {
+  struct {
+    unsigned char _PCBYP:1;
+    unsigned char _TCBYP:1;
+    unsigned char BIT2:1;
+    unsigned char BIT3:1;
+    unsigned char BIT4:1;
+    unsigned char BIT5:1;
+    unsigned char BIT6:1;
+    unsigned char BIT7:1;
+  } TIMTST_BITS;
+  unsigned char TIMTST_BYTE;
+} TIMTST1 _IO_AT(0xAD);
+
+/*DEFINE REGISTER*/
+#define TIMTST TIMTST1.TIMTST_BYTE
+
+/*DEFINE REGISTER BITS*/
+#define PCBYP TIMTST1.TIMTST_BITS._PCBYP
+#define TCBYP TIMTST1.TIMTST_BITS._TCBYP
+
+/*******************************************************************************************/
+/*                                  TIMER PORT DATA REGISTER                               */
+/*******************************************************************************************/
+
+/*****PORT T DEFINITION*****/
+
+__DECL__6812B32_H__ volatile union {
+  struct {
+    unsigned char _I_OC0:1;
+    unsigned char _I_OC1:1;
+    unsigned char _I_OC2:1;
+    unsigned char _I_OC3:1;
+    unsigned char _I_OC4:1;
+    unsigned char _I_OC5:1;
+    unsigned char _I_OC6:1;
+    unsigned char _I_OC7:1;
+  } PORTT_BITS;
+  unsigned char PORTT_BYTE;
+} PORTT1 _IO_AT(0xAE);
+
+/*DEFINE REGISTER*/
+#define PORTT PORTT1.PORTT_BYTE
+
+/*DEFINE REGISTER BITS*/
+#define I_OC0 PORTT1.PORTT_BITS._I_OC0
+#define I_OC1 PORTT1.PORTT_BITS._I_OC1
+#define I_OC2 PORTT1.PORTT_BITS._I_OC2
+#define I_OC3 PORTT1.PORTT_BITS._I_OC3
+#define I_OC4 PORTT1.PORTT_BITS._I_OC4
+#define I_OC5 PORTT1.PORTT_BITS._I_OC5
+#define I_OC6 PORTT1.PORTT_BITS._I_OC6
+#define I_OC7 PORTT1.PORTT_BITS._I_OC7
+
+/*****DATA DIRECTION REGISTER FOR TIMER OUT*****/
+__DECL__6812B32_H__ volatile  unsigned char DDRT     _IO_AT(0xaf);
+
+/*******************************************************************************************/
+/*                            SCI BAUD RATE CONTROL REGISTERS                              */
+/*******************************************************************************************/
+
+/*****SCI BAUD RATE CONTROL REGISTER HIGH*****/
+__DECL__6812B32_H__ volatile union {
+  struct {
+    unsigned char _SBR8:1;
+    unsigned char _SBR9:1;
+    unsigned char _SBR10:1;
+    unsigned char _SBR11:1;
+    unsigned char _SBR12:1;
+    unsigned char _BRLD:1;
+    unsigned char _BSPL:1;
+    unsigned char _BTST:1;
+  } SC0BDH_BITS;
+  unsigned char SC0BDH_BYTE;
+} SC0BDH1 _IO_AT(0xC0);
+
+/*DEFINE REGISTER*/
+#define SC0BDH SC0BDH1.SC0BDH_BYTE
+
+/*DEFINE REGISTER BITS*/
+#define SBR8 SC0BDH1.SC0BDH_BITS._SBR8
+#define SBR9 SC0BDH1.SC0BDH_BITS._SBR9
+#define SBR10 SC0BDH1.SC0BDH_BITS._SBR10
+#define SBR11 SC0BDH1.SC0BDH_BITS._SBR11
+#define SBR12 SC0BDH1.SC0BDH_BITS._SBR12
+#define BRLD SC0BDH1.SC0BDH_BITS._BRLD
+#define BSPL SC0BDH1.SC0BDH_BITS._BSPL
+#define BTST SC0BDH1.SC0BDH_BITS._BTST
+
+
+/*****SCI BAUD RATE CONTROL REGISTER LOW*****/
+__DECL__6812B32_H__ volatile union {
+  struct {
+    unsigned char _SBR0:1;
+    unsigned char _SBR1:1;
+    unsigned char _SBR2:1;
+    unsigned char _SBR3:1;
+    unsigned char _SBR4:1;
+    unsigned char _SBR5:1;
+    unsigned char _SBR6:1;
+    unsigned char _SBR7:1;
+  } SC0BDL_BITS;
+  unsigned char SC0BDL_BYTE;
+} SC0BDL1 _IO_AT(0xC1);
+
+/*DEFINE REGISTER*/
+#define SC0BDL SC0BDL1.SC0BDL_BYTE
+
+/*DEFINE REGISTER BITS*/
+#define SBR0 SC0BDL1.SC0BDL_BITS._SBR0
+#define SBR1 SC0BDL1.SC0BDL_BITS._SBR1
+#define SBR2 SC0BDL1.SC0BDL_BITS._SBR2
+#define SBR3 SC0BDL1.SC0BDL_BITS._SBR3
+#define SBR4 SC0BDL1.SC0BDL_BITS._SBR4
+#define SBR5 SC0BDL1.SC0BDL_BITS._SBR5
+#define SBR6 SC0BDL1.SC0BDL_BITS._SBR6
+#define SBR7 SC0BDL1.SC0BDL_BITS._SBR7
+
+/*******************************************************************************************/
+/*                                 SCI  CONTROL REGISTERS                                  */
+/*******************************************************************************************/
+
+/*****SCI CONTROL REGISTER 1*****/
+__DECL__6812B32_H__ volatile union {
+  struct {
+    unsigned char _PT:1;
+    unsigned char _PE:1;
+    unsigned char _ILT:1;
+    unsigned char _WAKE:1;
+    unsigned char _M:1;
+    unsigned char _RSRC:1;
+    unsigned char _WOMS:1;
+    unsigned char _LOOPS:1;
+  } SC0CR1_BITS;
+  unsigned char SC0CR1_BYTE;
+} SC0CR11 _IO_AT(0xC2);
+
+/*DEFINE REGISTER*/
+#define SC0CR1 SC0CR11.SC0CR1_BYTE
+
+/*DEFINE REGISTER BITS*/
+#define PT SC0CR11.SC0CR1_BITS._PT
+#define PE SC0CR11.SC0CR1_BITS._PE
+#define ILT SC0CR11.SC0CR1_BITS._ILT
+#define WAKE SC0CR11.SC0CR1_BITS._WAKE
+#define M SC0CR11.SC0CR1_BITS._M
+#define RSRC SC0CR11.SC0CR1_BITS._RSRC
+#define WOMS SC0CR11.SC0CR1_BITS._WOMS
+#define LOOPS SC0CR11.SC0CR1_BITS._LOOPS
+
+/*****SCI CONTROL REGISTER 2*****/
+__DECL__6812B32_H__ volatile union {
+  struct {
+    unsigned char _SBK:1;
+    unsigned char _RWU:1;
+    unsigned char _RE:1;
+    unsigned char _TE:1;
+    unsigned char _ILIE:1;
+    unsigned char _RIE:1;
+    unsigned char _TCIE:1;
+    unsigned char _TIE:1;
+  } SC0CR2_BITS;
+  unsigned char SC0CR2_BYTE;
+} SC0CR21 _IO_AT(0xC3);
+
+/*DEFINE REGISTER*/
+#define SC0CR2 SC0CR21.SC0CR2_BYTE
+
+/*DEFINE REGISTER BITS*/
+#define SBK SC0CR21.SC0CR2_BITS._SBK
+#define RWU SC0CR21.SC0CR2_BITS._RWU
+#define RE SC0CR21.SC0CR2_BITS._RE
+#define TE SC0CR21.SC0CR2_BITS._TE
+#define ILIE SC0CR21.SC0CR2_BITS._ILIE
+#define RIE SC0CR21.SC0CR2_BITS._RIE
+#define TCIE SC0CR21.SC0CR2_BITS._TCIE
+#define TIE SC0CR21.SC0CR2_BITS._TIE
+
+/*******************************************************************************************/
+/*                                   SCI STATUS REGISTERS                                  */
+/*******************************************************************************************/
+
+/*****SCI STATUS REGISTER 1*****/
+
+__DECL__6812B32_H__ volatile union {
+  struct {
+    unsigned char _PF:1;
+    unsigned char _FE:1;
+    unsigned char _NF:1;
+    unsigned char _OR:1;
+    unsigned char _IDLE:1;
+    unsigned char _RDRF:1;
+    unsigned char _TC:1;
+    unsigned char _TDRE:1;
+  } SC0SR1_BITS;
+  unsigned char SC0SR1_BYTE;
+} SC0SR11 _IO_AT(0xC4);
+
+/*DEFINE REGISTER*/
+#define SC0SR1 SC0SR11.SC0SR1_BYTE
+
+/*DEFINE REGISTER BITS*/
+#define PF SC0SR11.SC0SR1_BITS._PF
+#define FE SC0SR11.SC0SR1_BITS._FE
+#define NF SC0SR11.SC0SR1_BITS._NF
+#define OR SC0SR11.SC0SR1_BITS._OR
+#define IDLE SC0SR11.SC0SR1_BITS._IDLE
+#define RDRF SC0SR11.SC0SR1_BITS._RDRF
+#define TC SC0SR11.SC0SR1_BITS._TC
+#define TDRE SC0SR11.SC0SR1_BITS._TDRE
+
+/*****SCI STATUS REGISTER 2*****/
+
+__DECL__6812B32_H__ volatile union {
+  struct {
+    unsigned char _RAF:1;
+    unsigned char BIT1:1;
+    unsigned char BIT2:1;
+    unsigned char BIT3:1;
+    unsigned char BIT4:1;
+    unsigned char BIT5:1;
+    unsigned char BIT6:1;
+    unsigned char BIT7:1;
+  } SC0SR2_BITS;
+  unsigned char SC0SR2_BYTE;
+} SC0SR21 _IO_AT(0xC5);
+
+/*DEFINE REGISTER*/
+#define SC0SR2 SC0SR21.SC0SR2_BYTE
+
+/*DEFINE REGISTER BITS*/
+#define RAF SC0SR21.SC0SR2_BITS._RAF
+
+/*******************************************************************************************/
+/*                                   SCI DATA REGISTERS                                    */
+/*******************************************************************************************/
+
+/*****SCI DATA REGISTER HIGH*****/
+
+__DECL__6812B32_H__ volatile union {
+  struct {
+    unsigned char BIT0:1;
+    unsigned char BIT1:1;
+    unsigned char BIT2:1;
+    unsigned char BIT3:1;
+    unsigned char BIT4:1;
+    unsigned char BIT5:1;
+    unsigned char _T8:1;
+    unsigned char _R8:1;
+  } SC0DRH_BITS;
+  unsigned char SC0DRH_BYTE;
+} SC0DRH1 _IO_AT(0xC6);
+
+/*DEFINE REGISTER*/
+#define SC0DRH SC0DRH1.SC0DRH_BYTE
+
+/*DEFINE REGISTER BITS*/
+#define T8 SC0DRH1.SC0DRH_BITS._T8
+#define R8 SC0DRH1.SC0DRH_BITS._R8
+
+/*****SCI DATA REGISTER LOW*****/
+
+__DECL__6812B32_H__ volatile union {
+  struct {
+    unsigned char _R0_T0:1;
+    unsigned char _R1_T1:1;
+    unsigned char _R2_T2:1;
+    unsigned char _R3_T3:1;
+    unsigned char _R4_T4:1;
+    unsigned char _R5_T5:1;
+    unsigned char _R6_T6:1;
+    unsigned char _R7_T7:1;
+  } SC0DRL_BITS;
+  unsigned char SC0DRL_BYTE;
+} SC0DRL1 _IO_AT(0xC7);
+
+/*DEFINE REGISTER*/
+#define SC0DRL SC0DRL1.SC0DRL_BYTE
+
+/*DEFINE REGISTER BITS*/
+#define R0_T0 SC0DRL1.SC0DRL_BITS._R0_T0
+#define R1_T1 SC0DRL1.SC0DRL_BITS._R1_T1
+#define R2_T2 SC0DRL1.SC0DRL_BITS._R2_T2
+#define R3_T3 SC0DRL1.SC0DRL_BITS._R3_T3
+#define R4_T4 SC0DRL1.SC0DRL_BITS._R4_T4
+#define R5_T5 SC0DRL1.SC0DRL_BITS._R5_T5
+#define R6_T6 SC0DRL1.SC0DRL_BITS._R6_T6
+#define R7_T7 SC0DRL1.SC0DRL_BITS._R7_T7
+
+
+/*******************************************************************************************/
+/*                                 SPI  CONTROL REGISTERS                                  */
+/*******************************************************************************************/
+
+/*****SPI CONTROL REGISTER 1*****/
+
+__DECL__6812B32_H__ volatile union {
+  struct {
+    unsigned char _LSBF:1;
+    unsigned char _SSOE:1;
+    unsigned char _CPHA:1;
+    unsigned char _CPOL:1;
+    unsigned char _MSTR:1;
+    unsigned char _SWOM:1;
+    unsigned char _SPE:1;
+    unsigned char _SPIE:1;
+  } SP0CR1_BITS;
+  unsigned char SP0CR1_BYTE;
+} SP0CR11 _IO_AT(0xD0);
+
+/*DEFINE REGISTER*/
+#define SP0CR1 SP0CR11.SP0CR1_BYTE
+
+/*DEFINE REGISTER BITS*/
+#define LSBF SP0CR11.SP0CR1_BITS._LSBF
+#define SSOE SP0CR11.SP0CR1_BITS._SSOE
+#define CPHA SP0CR11.SP0CR1_BITS._CPHA
+#define CPOL SP0CR11.SP0CR1_BITS._CPOL
+#define MSTR SP0CR11.SP0CR1_BITS._MSTR
+#define SWOM SP0CR11.SP0CR1_BITS._SWOM
+#define SPE SP0CR11.SP0CR1_BITS._SPE
+#define SPIE SP0CR11.SP0CR1_BITS._SPIE
+
+/*****SPI CONTROL REGISTER 2*****/
+
+__DECL__6812B32_H__ volatile union {
+  struct {
+    unsigned char _SPC0:1;
+    unsigned char _SSWAI:1;
+    unsigned char BIT2:1;
+    unsigned char BIT3:1;
+    unsigned char BIT4:1;
+    unsigned char BIT5:1;
+    unsigned char BIT6:1;
+    unsigned char BIT7:1;
+  } SP0CR2_BITS;
+  unsigned char SP0CR2_BYTE;
+} SP0CR21 _IO_AT(0xD1);
+
+/*DEFINE REGISTER*/
+#define SP0CR2 SP0CR21.SP0CR2_BYTE
+
+/*DEFINE REGISTER BITS*/
+#define SPC0 SP0CR21.SP0CR2_BITS._SPC0
+#define SSWAI SP0CR21.SP0CR2_BITS._SSWAI
+
+/*******************************************************************************************/
+/*                                 SPI BAUD RATE REGISTER                                  */
+/*******************************************************************************************/
+
+__DECL__6812B32_H__ volatile union {
+  struct {
+    unsigned char _SPR0:1;
+    unsigned char _SPR1:1;
+    unsigned char _SPR2:1;
+    unsigned char BIT3:1;
+    unsigned char BIT4:1;
+    unsigned char BIT5:1;
+    unsigned char BIT6:1;
+    unsigned char BIT7:1;
+  } SP0BR_BITS;
+  unsigned char SP0BR_BYTE;
+} SP0BR1 _IO_AT(0xD2);
+
+/*DEFINE REGISTER*/
+#define SP0BR SP0BR1.SP0BR_BYTE
+
+/*DEFINE REGISTER BITS*/
+#define SPR0 SP0BR1.SP0BR_BITS._SPR0
+#define SPR1 SP0BR1.SP0BR_BITS._SPR1
+#define SPR2 SP0BR1.SP0BR_BITS._SPR2
+
+/*******************************************************************************************/
+/*                                    SPI STATUS REGISTER                                  */
+/*******************************************************************************************/
+
+__DECL__6812B32_H__ volatile union {
+  struct {
+    unsigned char BIT0:1;
+    unsigned char BIT1:1;
+    unsigned char BIT2:1;
+    unsigned char BIT3:1;
+    unsigned char _MODF:1;
+    unsigned char BIT5:1;
+    unsigned char _WCOL:1;
+    unsigned char _SPIF:1;
+  } SP0SR_BITS;
+  unsigned char SP0SR_BYTE;
+} SP0SR1 _IO_AT(0xD3);
+
+/*DEFINE REGISTER*/
+#define SP0SR SP0SR1.SP0SR_BYTE
+
+/*DEFINE REGISTER BITS*/
+#define MODF SP0SR1.SP0SR_BITS._MODF
+#define WCOL SP0SR1.SP0SR_BITS._WCOL
+#define SPIF SP0SR1.SP0SR_BITS._SPIF
+
+/*******************************************************************************************/
+/*                                   SCI DATA REGISTERS                                    */
+/*******************************************************************************************/
+
+__DECL__6812B32_H__ volatile  unsigned char SP0DR    _IO_AT(0xd5);
+
+/*******************************************************************************************/
+/*                                             PORT S                                      */
+/*******************************************************************************************/
+
+/*****PORT S DEFINITION*****/
+
+__DECL__6812B32_H__ volatile union {
+  struct {
+    unsigned char _RXD0:1;
+    unsigned char _TXD0:1;
+    unsigned char _I_O1:1;
+    unsigned char _I_O2:1;
+    unsigned char _MISO_SISO:1;
+    unsigned char _MOSI_MOMI:1;
+    unsigned char _SCK:1;
+    unsigned char _SS__CSA:1;
+  } PORTS_BITS;
+  unsigned char PORTS_BYTE;
+} PORTS1 _IO_AT(0xD6);
+
+/*DEFINE REGISTER*/
+#define PORTS PORTS1.PORTS_BYTE
+
+/*DEFINE REGISTER BITS*/
+#define RXD0        PORTS1.PORTS_BITS._RXD0
+#define TXD0        PORTS1.PORTS_BITS._TXD0
+#define I_O1        PORTS1.PORTS_BITS._I_O1
+#define I_O2        PORTS1.PORTS_BITS._I_O2
+#define MISO_SISO   PORTS1.PORTS_BITS._MISO_SISO
+#define MOSI_MOMI   PORTS1.PORTS_BITS._MOSI_MOMI
+#define SCK         PORTS1.PORTS_BITS._SCK
+#define _SS__CS     PORTS1.PORTS_BITS._SS__CSA
+
+/*****DATA DIRECTION REGISTER FOR PORT S*****/
+
+__DECL__6812B32_H__ volatile  unsigned char DDRS     _IO_AT(0xd7);
+
+/*******************************************************************************************/
+/*                   PULL_UP AND REDUCED DRIVE FOR PORT S                                  */
+/*******************************************************************************************/
+
+__DECL__6812B32_H__ volatile union {
+  struct {
+    unsigned char _PUPS0:1;
+    unsigned char _PUPS1:1;
+    unsigned char _PUPS2:1;
+    unsigned char BIT3:1;
+    unsigned char _RDPS0:1;
+    unsigned char _RDPS1:1;
+    unsigned char _RDPS2:1;
+    unsigned char BIT7:1;
+  } PURDS_BITS;
+  unsigned char PURDS_BYTE;
+} PURDS1 _IO_AT(0xDB);
+
+/*DEFINE REGISTER*/
+#define PURDS PURDS1.PURDS_BYTE
+
+/*DEFINE REGISTER BITS*/
+#define PUPS0 PURDS1.PURDS_BITS._PUPS0
+#define PUPS1 PURDS1.PURDS_BITS._PUPS1
+#define PUPS2 PURDS1.PURDS_BITS._PUPS2
+#define RDPS0 PURDS1.PURDS_BITS._RDPS0
+#define RDPS1 PURDS1.PURDS_BITS._RDPS1
+#define RDPS2 PURDS1.PURDS_BITS._RDPS2
+
+/*******************************************************************************************/
+/*                            EEPROM MODULE CONFIGURATION                                  */
+/*******************************************************************************************/
+
+__DECL__6812B32_H__ volatile union {
+  struct {
+    unsigned char _EERC:1;
+    unsigned char _PROTLCK:1;
+    unsigned char _EESWAI:1;
+    unsigned char BIT3:1;
+    unsigned char BIT4:1;
+    unsigned char BIT5:1;
+    unsigned char BIT6:1;
+    unsigned char BIT7:1;
+  } EEMCR_BITS;
+  unsigned char EEMCR_BYTE;
+} EEMCR1 _IO_AT(0xF0);
+
+/*DEFINE REGISTER*/
+#define EEMCR EEMCR1.EEMCR_BYTE
+
+/*DEFINE REGISTER BITS*/
+#define EERC EEMCR1.EEMCR_BITS._EERC
+#define PROTLCK EEMCR1.EEMCR_BITS._PROTLCK
+#define EESWAI EEMCR1.EEMCR_BITS._EESWAI
+
+/*******************************************************************************************/
+/*                                   EEPROM BLOCK PROTECT                                  */
+/*******************************************************************************************/
+
+__DECL__6812B32_H__ volatile union {
+  struct {
+    unsigned char _BPROT0:1;
+    unsigned char _BPROT1:1;
+    unsigned char _BPROT2:1;
+    unsigned char _BPROT3:1;
+    unsigned char _BPROT4:1;
+    unsigned char BIT5:1;
+    unsigned char BIT6:1;
+    unsigned char BIT7:1;
+  } EEPROT_BITS;
+  unsigned char EEPROT_BYTE;
+} EEPROT1 _IO_AT(0xF1);
+
+/*DEFINE REGISTER*/
+#define EEPROT EEPROT1.EEPROT_BYTE
+
+/*DEFINE REGISTER BITS*/
+#define BPROT0 EEPROT1.EEPROT_BITS._BPROT0
+#define BPROT1 EEPROT1.EEPROT_BITS._BPROT1
+#define BPROT2 EEPROT1.EEPROT_BITS._BPROT2
+#define BPROT3 EEPROT1.EEPROT_BITS._BPROT3
+#define BPROT4 EEPROT1.EEPROT_BITS._BPROT4
+
+/*******************************************************************************************/
+/*                                       EEPROM TEST                                       */
+/*******************************************************************************************/
+
+__DECL__6812B32_H__ volatile union {
+  struct {
+    unsigned char BIT0:1;
+    unsigned char _EECPM:1;
+    unsigned char BIT2:1;
+    unsigned char _EECPRD:1;
+    unsigned char _EECPD:1;
+    unsigned char _MARG:1;
+    unsigned char _EEVEN:1;
+    unsigned char _EEODD:1;
+  } EETST_BITS;
+  unsigned char EETST_BYTE;
+} EETST1 _IO_AT(0xF2);
+
+/*DEFINE REGISTER*/
+#define EETST EETST1.EETST_BYTE
+
+/*DEFINE REGISTER BITS*/
+#define EECPM EETST1.EETST_BITS._EECPM
+#define EECPRD EETST1.EETST_BITS._EECPRD
+#define EECPD EETST1.EETST_BITS._EECPD
+#define MARG EETST1.EETST_BITS._MARG
+#define EEVEN EETST1.EETST_BITS._EEVEN
+#define EEODD EETST1.EETST_BITS._EEODD
+
+/*******************************************************************************************/
+/*                                       EEPROM CONTROL                                    */
+/*******************************************************************************************/
+
+__DECL__6812B32_H__ volatile union {
+  struct {
+    unsigned char _EEPGM:1;
+    unsigned char _EELAT:1;
+    unsigned char _ERASE:1;
+    unsigned char _ROW:1;
+    unsigned char _BYTE:1;
+    unsigned char BIT5:1;
+    unsigned char BIT6:1;
+    unsigned char _BULKP:1;
+  } EEPROG_BITS;
+  unsigned char EEPROG_BYTE;
+} EEPROG1 _IO_AT(0xF3);
+
+/*DEFINE REGISTER*/
+#define EEPROG EEPROG1.EEPROG_BYTE
+
+/*DEFINE REGISTER BITS*/
+#define EEPGM EEPROG1.EEPROG_BITS._EEPGM
+#define EELAT EEPROG1.EEPROG_BITS._EELAT
+#define ERASE EEPROG1.EEPROG_BITS._ERASE
+#define ROW EEPROG1.EEPROG_BITS._ROW
+#define BYTE EEPROG1.EEPROG_BITS._BYTE
+#define BULKP EEPROG1.EEPROG_BITS._BULKP
+
+/*******************************************************************************************/
+/*                          FLASH EEPROM LOCK CONTROL REGISTER                             */
+/*******************************************************************************************/
+
+__DECL__6812B32_H__ volatile union {
+  struct {
+    unsigned char _LOCK:1;
+    unsigned char BIT1:1;
+    unsigned char BIT2:1;
+    unsigned char BIT3:1;
+    unsigned char BIT4:1;
+    unsigned char BIT5:1;
+    unsigned char BIT6:1;
+    unsigned char BIT7:1;
+  } FEELCK_BITS;
+  unsigned char FEELCK_BYTE;
+} FEELCK1 _IO_AT(0xF4);
+
+/*DEFINE REGISTER*/
+#define FEELCK FEELCK1.FEELCK_BYTE
+
+/*DEFINE REGISTER BITS*/
+#define LOCK FEELCK1.FEELCK_BITS._LOCK
+
+/*******************************************************************************************/
+/*                          FLASH EEPROM MODULE CONFIGURATION REGISTER                     */
+/*******************************************************************************************/
+
+__DECL__6812B32_H__ volatile union {
+  struct {
+    unsigned char _BOOTP:1;
+    unsigned char BIT1:1;
+    unsigned char BIT2:1;
+    unsigned char BIT3:1;
+    unsigned char BIT4:1;
+    unsigned char BIT5:1;
+    unsigned char BIT6:1;
+    unsigned char BIT7:1;
+  } FEEMCR_BITS;
+  unsigned char FEEMCR_BYTE;
+} FEEMCR1 _IO_AT(0xF5);
+
+/*DEFINE REGISTER*/
+#define FEEMCR FEEMCR1.FEEMCR_BYTE
+
+/*DEFINE REGISTER BITS*/
+#define BOOTP FEEMCR1.FEEMCR_BITS._BOOTP
+
+/*******************************************************************************************/
+/*                              FLASH EEPROM MODULE TEST REGISTER                          */
+/*******************************************************************************************/
+
+__DECL__6812B32_H__ volatile union {
+  struct {
+    unsigned char _MWPR:1;
+    unsigned char _STRE:1;
+    unsigned char _VTCK:1;
+    unsigned char _FDISVFP:1;
+    unsigned char _FENLV:1;
+    unsigned char _HVT:1;
+    unsigned char _GADR:1;
+    unsigned char _FSTE:1;
+  } FEETST_BITS;
+  unsigned char FEETST_BYTE;
+} FEETST1 _IO_AT(0xF6);
+
+/*DEFINE REGISTER*/
+#define FEETST FEETST1.FEETST_BYTE
+
+/*DEFINE REGISTER BITS*/
+#define MWPR FEETST1.FEETST_BITS._MWPR
+#define STRE FEETST1.FEETST_BITS._STRE
+#define VTCK FEETST1.FEETST_BITS._VTCK
+#define FDISVFP FEETST1.FEETST_BITS._FDISVFP
+#define FENLV FEETST1.FEETST_BITS._FENLV
+#define HVT FEETST1.FEETST_BITS._HVT
+#define GADR FEETST1.FEETST_BITS._GADR
+#define FSTE FEETST1.FEETST_BITS._FSTE
+
+/*******************************************************************************************/
+/*                              FLASH EEPROM CONTROL REGISTER                              */
+/*******************************************************************************************/
+
+__DECL__6812B32_H__ volatile union {
+  struct {
+    unsigned char _ENTPE:1;
+    unsigned char _LAT:1;
+    unsigned char _ERAS:1;
+    unsigned char _SVFP:1;
+    unsigned char _FEESWAI:1;
+    unsigned char BIT5:1;
+    unsigned char BIT6:1;
+    unsigned char BIT7:1;
+  } FEECTL_BITS;
+  unsigned char FEECTL_BYTE;
+} FEECTL1 _IO_AT(0xF7);
+
+/*DEFINE REGISTER*/
+#define FEECTL FEECTL1.FEECTL_BYTE
+
+/*DEFINE REGISTER BITS*/
+#define ENTPE FEECTL1.FEECTL_BITS._ENTPE
+#define LAT FEECTL1.FEECTL_BITS._LAT
+#define ERAS FEECTL1.FEECTL_BITS._ERAS
+#define SVFP FEECTL1.FEECTL_BITS._SVFP
+#define FEESWAI FEECTL1.FEECTL_BITS._FEESWAI
+
+/*******************************************************************************************/
+/*                                     BDLC CONTROL REGISTER 1                             */
+/*******************************************************************************************/
+
+__DECL__6812B32_H__ volatile union {
+  struct {
+    unsigned char _WCM:1;
+    unsigned char _IE:1;
+    unsigned char BIT2:1;
+    unsigned char BIT3:1;
+    unsigned char _R0:1;
+    unsigned char _R1:1;
+    unsigned char _CLOCKS:1;
+    unsigned char _IMSG:1;
+  } BCR1_BITS;
+  unsigned char BCR1_BYTE;
+} BCR11 _IO_AT(0xF8);
+
+/*DEFINE REGISTER*/
+#define BCR1 BCR11.BCR1_BYTE
+
+/*DEFINE REGISTER BITS*/
+#define WCM BCR11.BCR1_BITS._WCM
+#define IE BCR11.BCR1_BITS._IE
+#define R0 BCR11.BCR1_BITS._R0
+#define R1 BCR11.BCR1_BITS._R1
+#define CLOCKS BCR11.BCR1_BITS._CLOCKS
+#define IMSG BCR11.BCR1_BITS._IMSG
+
+/*******************************************************************************************/
+/*                                  BDLC STATE VECTOR REGISTER                             */
+/*******************************************************************************************/
+
+__DECL__6812B32_H__ volatile union {
+  struct {
+    unsigned char BIT0:1;
+    unsigned char BIT1:1;
+    unsigned char _I0:1;
+    unsigned char _I1:1;
+    unsigned char _I2:1;
+    unsigned char _I3:1;
+    unsigned char BIT6:1;
+    unsigned char BIT7:1;
+  } BSVR_BITS;
+  unsigned char BSVR_BYTE;
+} BSVR1 _IO_AT(0xF9);
+
+/*DEFINE REGISTER*/
+#define BSVR BSVR1.BSVR_BYTE
+
+/*DEFINE REGISTER BITS*/
+#define I0 BSVR1.BSVR_BITS._I0
+#define I1 BSVR1.BSVR_BITS._I1
+#define I2 BSVR1.BSVR_BITS._I2
+#define I3 BSVR1.BSVR_BITS._I3
+
+/*******************************************************************************************/
+/*                                     BDLC CONTROL REGISTER 2                             */
+/*******************************************************************************************/
+
+__DECL__6812B32_H__ volatile union {
+  struct {
+    unsigned char _TMIFR0:1;
+    unsigned char _TMIFR1:1;
+    unsigned char _TSIFR:1;
+    unsigned char _TEOD:1;
+    unsigned char _NBFS:1;
+    unsigned char _RX4XE:1;
+    unsigned char _DLOOP:1;
+    unsigned char _ALOOP:1;
+  } BCR2_BITS;
+  unsigned char BCR2_BYTE;
+} BCR21 _IO_AT(0xFA);
+
+/*DEFINE REGISTER*/
+#define BCR2 BCR21.BCR2_BYTE
+
+/*DEFINE REGISTER BITS*/
+#define TMIFR0 BCR21.BCR2_BITS._TMIFR0
+#define TMIFR1 BCR21.BCR2_BITS._TMIFR1
+#define TSIFR BCR21.BCR2_BITS._TSIFR
+#define TEOD BCR21.BCR2_BITS._TEOD
+#define RX4XE BCR21.BCR2_BITS._RX4XE
+#define DLOOP BCR21.BCR2_BITS._DLOOP
+#define ALOOP BCR21.BCR2_BITS._ALOOP
+
+/*******************************************************************************************/
+/*                                     BDLC DATA REGISTER                                  */
+/*******************************************************************************************/
+
+__DECL__6812B32_H__ volatile  unsigned char BDR      _IO_AT(0xfB);
+
+/*******************************************************************************************/
+/*                        BDLC ANALOG ROUNDTRIP DELAY REGISTER                             */
+/*******************************************************************************************/
+
+__DECL__6812B32_H__ volatile union {
+  struct {
+    unsigned char _BO0:1;
+    unsigned char _BO1:1;
+    unsigned char _BO2:1;
+    unsigned char _BO3:1;
+    unsigned char BIT4:1;
+    unsigned char BIT5:1;
+    unsigned char _RXPOL:1;
+    unsigned char _ATE:1;
+  } BARD_BITS;
+  unsigned char BARD_BYTE;
+} BARD1 _IO_AT(0xFC);
+
+/*DEFINE REGISTER*/
+#define BARD BARD1.BARD_BYTE
+
+/*DEFINE REGISTER BITS*/
+#define BO0 BARD1.BARD_BITS._BO0
+#define BO1 BARD1.BARD_BITS._BO1
+#define BO2 BARD1.BARD_BITS._BO2
+#define BO3 BARD1.BARD_BITS._BO3
+#define RXPOL BARD1.BARD_BITS._RXPOL
+#define ATE BARD1.BARD_BITS._ATE
+
+/*******************************************************************************************/
+/*                                   PORT DLC CONTROL REGISTER                             */
+/*******************************************************************************************/
+
+__DECL__6812B32_H__ volatile union {
+  struct {
+    unsigned char _RDPDLC:1;
+    unsigned char _PUPDLC:1;
+    unsigned char _BDLGEN:1;
+    unsigned char BIT3:1;
+    unsigned char BIT4:1;
+    unsigned char BIT5:1;
+    unsigned char BIT6:1;
+    unsigned char BIT7:1;
+  } DLCSCR_BITS;
+  unsigned char DLCSCR_BYTE;
+} DLCSCR1 _IO_AT(0xFD);
+
+/*DEFINE REGISTER*/
+#define DLCSCR DLCSCR1.DLCSCR_BYTE
+
+/*DEFINE REGISTER BITS*/
+#define RDPDLC DLCSCR1.DLCSCR_BITS._RDPDLC
+#define PUPDLC DLCSCR1.DLCSCR_BITS._PUPDLC
+#define BDLGEN DLCSCR1.DLCSCR_BITS._BDLGEN
+
+/*******************************************************************************************/
+/*                                             PORT DLC                                      */
+/*******************************************************************************************/
+
+/*****PORT DLC DEFINITION*****/
+
+__DECL__6812B32_H__ volatile union {
+  struct {
+    unsigned char _DLCRX:1;
+    unsigned char _DLCTX:1;
+    unsigned char BIT2:1;
+    unsigned char BIT3:1;
+    unsigned char BIT4:1;
+    unsigned char BIT5:1;
+    unsigned char BIT6:1;
+    unsigned char BIT7:1;
+  } PORTDLC_BITS;
+  unsigned char PORTDLC_BYTE;
+} PORTDLC1 _IO_AT(0xFE);
+
+/*DEFINE REGISTER*/
+#define PORTDLC PORTDLC1.PORTDLC_BYTE
+
+/*DEFINE REGISTER BITS*/
+#define DLCRX PORTDLC1.PORTDLC_BITS._DLCRX
+#define DLCTX PORTDLC1.PORTDLC_BITS._DLCTX
+
+/*****DATA DIRECTION REGISTER FOR PORT DLC*****/
+__DECL__6812B32_H__ volatile  unsigned char DDRDLC   _IO_AT(0xff);  /* port DLC direction register */
+
+#endif /* __6812B32_H__ */

Final_Project/Sources/menu.asm

@@ -0,0 +1,266 @@
+                         	XDEF	Menu
+	XREF	__SEG_END_SSTACK,pw_set,disp,display_string,menu_option_num,menu_active,menu_selection
+	
+Variables:	    	Section
+
+Constants:	      Section
+
+Code:		  	Section
+
+Menu:      ;push register and accumulator values for retention                   
+            PSHA
+            PSHB
+            PSHD
+            PSHX
+            PSHY
+            
+            LDAA  menu_active ;do nothing if the menu is not active
+            CMPA  #$00
+            LBEQ  Return
+            
+PrintTopLine:
+           ;all menu items print this line
+           movb #'S',disp
+           movb #'e',disp+1
+           movb #'l',disp+2
+           movb #'e',disp+3
+           movb #'c',disp+4
+           movb #'t',disp+5
+           movb #' ',disp+6
+           movb #'o',disp+7
+           movb #'p',disp+8
+           movb #'t',disp+9
+           movb #'i',disp+10
+           movb #'o',disp+11
+           movb #'n',disp+12
+           movb #':',disp+13
+           movb #' ',disp+14
+           movb #' ',disp+15
+           ;next line
+           
+            ;load the menu option and output the correct lower string           
+            LDAA  menu_option_num
+            CMPA  #$01
+            LBEQ  PrintOption1
+                 
+            CMPA  #$02
+            LBEQ   PrintOption2
+            
+            CMPA  #$03
+            LBEQ  PrintOption3
+            
+            CMPA  #$04
+            LBEQ  PrintOption4
+            
+            CMPA  #$05
+            LBEQ  PrintOption5
+            
+            CMPA  #$06
+            LBEQ  PrintOption6
+
+            CMPA  #$07
+            LBEQ  PrintOption7
+            
+Reset:
+            MOVB  #$01,menu_option_num
+            LBRA  PrintTopLine
+              
+           
+;==================== main menu =======================
+; 1. water the plants
+; 2. show temperature (adjusts when the pot is turned)
+; 3. show time
+; 4. set time (passord protected)
+; 5. change password (password protected)
+;======================================================
+
+PrintOption1:
+           movb #'1',disp+16
+           movb #'.',disp+17
+           movb #' ',disp+18
+           movb #'W',disp+19
+           movb #'a',disp+20
+           movb #'t',disp+21
+           movb #'e',disp+22
+           movb #'r',disp+23
+           movb #' ',disp+24
+           movb #'p',disp+25
+           movb #'l',disp+26
+           movb #'a',disp+27
+           movb #'n',disp+28
+           movb #'t',disp+29
+           movb #'s',disp+30
+           movb #' ',disp+31
+           movb #0,disp+32    ;string terminator, acts like '\0'
+		       
+		       ;print the prompt string
+		       LDD   #disp         ;both of these steps are necessary to
+           jsr  display_string ;print to the LCD screen
+           
+           ;get out of the menu, do not go to PrintOption2
+           LBRA  Return
+
+PrintOption2:
+           movb #'2',disp+16
+           movb #'.',disp+17
+           movb #' ',disp+18
+           movb #'S',disp+19
+           movb #'h',disp+20
+           movb #'o',disp+21
+           movb #'w',disp+22
+           movb #' ',disp+23
+           movb #'t',disp+24
+           movb #'e',disp+25
+           movb #'m',disp+26
+           movb #'p',disp+27
+           movb #'.',disp+28
+           movb #' ',disp+29
+           movb #' ',disp+30
+           movb #' ',disp+31
+           movb #0,disp+32    ;string terminator, acts like '\0'
+           
+           ;print the prompt string
+		       LDD   #disp         ;both of these steps are necessary to
+           jsr  display_string ;print to the LCD screen
+           
+           ;get out of the menu, do not go to PrintOption23
+           LBRA  Return
+
+PrintOption3:
+           movb #'3',disp+16
+           movb #'.',disp+17
+           movb #' ',disp+18
+           movb #'S',disp+19
+           movb #'h',disp+20
+           movb #'o',disp+21
+           movb #'w',disp+22
+           movb #' ',disp+23
+           movb #'t',disp+24
+           movb #'i',disp+25
+           movb #'m',disp+26
+           movb #'e',disp+27
+           movb #' ',disp+28
+           movb #' ',disp+29
+           movb #' ',disp+30
+           movb #' ',disp+31
+           movb #0,disp+32    ;string terminator, acts like '\0'
+           
+           ;print the prompt string
+		       LDD   #disp         ;both of these steps are necessary to
+           jsr  display_string ;print to the LCD screen
+           
+           ;get out of the menu, do not go to PrintOption23
+           LBRA  Return
+PrintOption4:
+           movb #'4',disp+16
+           movb #'.',disp+17
+           movb #' ',disp+18
+           movb #'S',disp+19
+           movb #'e',disp+20
+           movb #'t',disp+21
+           movb #' ',disp+22
+           movb #'t',disp+23
+           movb #'i',disp+24
+           movb #'m',disp+25
+           movb #'e',disp+26
+           movb #' ',disp+27
+           movb #' ',disp+28
+           movb #' ',disp+29
+           movb #' ',disp+30
+           movb #' ',disp+31
+           movb #0,disp+32    ;string terminator, acts like '\0'
+           
+           ;print the prompt string
+		       LDD   #disp         ;both of these steps are necessary to
+           jsr  display_string ;print to the LCD screen
+           
+           ;get out of the menu, do not go to PrintOption23
+           LBRA Return
+PrintOption5:
+           movb #'5',disp+16
+           movb #'.',disp+17
+           movb #' ',disp+18
+           movb #'R',disp+19
+           movb #'e',disp+20
+           movb #'s',disp+21
+           movb #'e',disp+22
+           movb #'t',disp+23
+           movb #' ',disp+24
+           movb #'p',disp+25
+           movb #'a',disp+26
+           movb #'s',disp+27
+           movb #'s',disp+28
+           movb #'w',disp+29
+           movb #'d',disp+30
+           movb #'.',disp+31
+           movb #0,disp+32    ;string terminator, acts like '\0'
+           
+           ;print the prompt string
+		       LDD   #disp         ;both of these steps are necessary to
+           jsr  display_string ;print to the LCD screen
+           
+           ;get out of the menu, do not go to PrintOption23
+           LBRA Return
+           
+PrintOption6:
+           movb #'6',disp+16
+           movb #'.',disp+17
+           movb #' ',disp+18
+           movb #'P',disp+19
+           movb #'l',disp+20
+           movb #'a',disp+21
+           movb #'n',disp+22
+           movb #'t',disp+23
+           movb #' ',disp+24
+           movb #'s',disp+25
+           movb #'e',disp+26
+           movb #'e',disp+27
+           movb #'d',disp+28
+           movb #'s',disp+29
+           movb #' ',disp+30
+           movb #' ',disp+31
+           movb #0,disp+32    ;string terminator, acts like '\0'
+           
+           ;print the prompt string
+		       LDD   #disp         ;both of these steps are necessary to
+           jsr  display_string ;print to the LCD screen
+           
+           ;get out of the menu, do not go to PrintOption6
+           BRA  Return
+           
+PrintOption7:
+           movb #'7',disp+16
+           movb #'.',disp+17
+           movb #' ',disp+18
+           movb #'S',disp+19
+           movb #'h',disp+20
+           movb #'o',disp+21
+           movb #'w',disp+22
+           movb #' ',disp+23
+           movb #'p',disp+24
+           movb #'l',disp+25
+           movb #'o',disp+26
+           movb #'t',disp+27
+           movb #' ',disp+28
+           movb #' ',disp+29
+           movb #' ',disp+30
+           movb #' ',disp+31
+           movb #0,disp+32    ;string terminator, acts like '\0'
+           
+           ;print the prompt string
+		       LDD   #disp         ;both of these steps are necessary to
+           jsr  display_string ;print to the LCD screen
+           
+           ;get out of the menu, do not go to PrintOption7
+           BRA  Return
+           
+
+            
+Return:     ;restore registers and accumulators
+            PULY
+            PULX
+            PULD
+            PULB
+            PULA
+            
+            RTS

Final_Project/Sources/password.asm

@@ -0,0 +1,639 @@
+	XDEF	Password
+	XREF	__SEG_END_SSTACK,pw_required,byte_out,disp,Keypad,display_string,pressed_num,password,pw_set,pw_reset,pw_check,PORT_S,await_key_release,await_key_press,entered_password,pw_correct
+	
+Variables:	    	Section
+pw_char_index     ds.b  1
+pw_char           ds.b  1
+
+Constants:	      Section
+
+Code:		  	Section
+
+Password:
+           ;push register and accumulator values for retention                   
+            PSHA
+            PSHB
+            PSHD
+            PSHX
+            PSHY
+            
+            ;setting password for the 1st time
+            LDAA  pw_set
+            CMPA  #$00
+            BEQ   PasswordInit
+            
+            ;user has elected to change the password
+            LDAA  pw_reset
+            CMPA  #$FF
+            LBEQ   PasswordReset
+            
+            ;user has selected something requiring auth
+            LDAA  pw_check
+            CMPA  #$FF
+            LBEQ   PasswordCheck
+            
+            LBRA   Return
+            
+            
+PasswordInit:
+
+            
+           ;MOVB   #$FF,
+            
+            
+           ;inital prompt
+           movb #'S',disp
+           movb #'e',disp+1
+           movb #'t',disp+2
+           movb #' ',disp+3
+           movb #'p',disp+4
+           movb #'a',disp+5
+           movb #'s',disp+6
+           movb #'s',disp+7
+           movb #'w',disp+8
+           movb #'o',disp+9
+           movb #'r',disp+10
+           movb #'d',disp+11
+           movb #':',disp+12
+           movb #' ',disp+13
+           movb #' ',disp+14
+           movb #' ',disp+15
+           ;next line
+           movb #'_',disp+16
+           movb #'_',disp+17
+           movb #'_',disp+18
+           movb #'_',disp+19
+           movb #'_',disp+20
+           movb #'_',disp+21
+           movb #'_',disp+22
+           movb #'_',disp+23
+           movb #' ',disp+24
+           movb #' ',disp+25
+           movb #' ',disp+26
+           movb #' ',disp+27
+           movb #' ',disp+28
+           movb #' ',disp+29
+           movb #' ',disp+30
+           movb #' ',disp+31
+           movb #0,disp+32    ;string terminator, acts like '\0'
+		       
+		       ;print the prompt string
+		       LDD   #disp         ;both of these steps are necessary to
+           jsr  display_string ;print to the LCD screen
+
+
+           ;AWAIT KEYPRESS
+           movb   #$FF,await_key_press
+           
+           ;READ EACH CHARACTER
+           MOVB   #$FF,await_key_release     
+           jsr Keypad                  ;read a keypress
+           movb  #'*',disp+16          ;change the display to acknowledge input
+           MOVB  pressed_num,password  ;store the read value into the password
+           LDD   #disp
+           jsr  display_string
+           ;LBRA  Return
+               
+           MOVB   #$FF,await_key_release           
+           jsr Keypad                  ;read a keypress
+           movb  #'*',disp+17          ;change the display to acknowledge input
+           MOVB  pressed_num,password+1  ;store the read value into the password            
+           LDD   #disp
+           jsr  display_string
+           ;LBRA  Return
+           
+           MOVB   #$FF,await_key_release           
+           jsr Keypad                  ;read a keypress
+           movb  #'*',disp+18          ;change the display to acknowledge input
+           MOVB  pressed_num,password+2  ;store the read value into the password
+           LDD   #disp
+           jsr  display_string
+           
+           MOVB   #$FF,await_key_release                      
+           jsr Keypad                  ;read a keypress
+           movb  #'*',disp+19          ;change the display to acknowledge input
+           MOVB  pressed_num,password+3  ;store the read value into the password
+           LDD   #disp
+           jsr  display_string                      
+           
+           MOVB   #$FF,await_key_release
+           jsr Keypad                  ;read a keypress
+           movb  #'*',disp+20          ;change the display to acknowledge input
+           MOVB  pressed_num,password+4  ;store the read value into the password
+           LDD   #disp
+           jsr  display_string
+           
+           MOVB   #$FF,await_key_release           
+           jsr Keypad                  ;read a keypress
+           movb  #'*',disp+21          ;change the display to acknowledge input
+           MOVB  pressed_num,password+5  ;store the read value into the password
+           LDD   #disp
+           jsr  display_string
+           
+           MOVB   #$FF,await_key_release           
+           jsr Keypad                  ;read a keypress
+           movb  #'*',disp+22          ;change the display to acknowledge input
+           MOVB  pressed_num,password+6  ;store the read value into the password 
+           LDD   #disp
+           jsr  display_string             
+           
+           MOVB   #$FF,await_key_release          
+           jsr Keypad                  ;read a keypress
+           movb  #'*',disp+23          ;change the display to acknowledge input
+           MOVB  pressed_num,password+7  ;store the read value into the password
+           LDD   #disp
+           jsr  display_string
+           
+           ;mark the password as set
+           MOVB   #$FF,pw_set
+           LBRA    Return
+
+
+PasswordReset:
+                      ;MOVB   #$FF,
+            
+            
+           ;inital prompt
+           movb #'C',disp
+           movb #'u',disp+1
+           movb #'r',disp+2
+           movb #'r',disp+3
+           movb #'e',disp+4
+           movb #'n',disp+5
+           movb #'t',disp+6
+           movb #' ',disp+7
+           movb #'p',disp+8
+           movb #'a',disp+9
+           movb #'s',disp+10
+           movb #'s',disp+11
+           movb #'w',disp+12
+           movb #'d',disp+13
+           movb #'.',disp+14
+           movb #':',disp+15
+           ;next line
+           movb #'_',disp+16
+           movb #'_',disp+17
+           movb #'_',disp+18
+           movb #'_',disp+19
+           movb #'_',disp+20
+           movb #'_',disp+21
+           movb #'_',disp+22
+           movb #'_',disp+23
+           movb #' ',disp+24
+           movb #' ',disp+25
+           movb #' ',disp+26
+           movb #' ',disp+27
+           movb #' ',disp+28
+           movb #' ',disp+29
+           movb #' ',disp+30
+           movb #' ',disp+31
+           movb #0,disp+32    ;string terminator, acts like '\0'
+		       
+		       ;print the prompt string
+		       LDD   #disp         ;both of these steps are necessary to
+           jsr  display_string ;print to the LCD screen
+
+
+           ;AWAIT KEYPRESS
+           movb   #$FF,await_key_press
+           
+           ;READ EACH CHARACTER
+           MOVB   #$FF,await_key_release     
+           jsr Keypad                  ;read a keypress
+           movb  #'*',disp+16          ;change the display to acknowledge input
+           MOVB  pressed_num,entered_password  ;store the read value into the password
+           LDD   #disp
+           jsr  display_string
+           ;LBRA  Return
+               
+           MOVB   #$FF,await_key_release           
+           jsr Keypad                  ;read a keypress
+           movb  #'*',disp+17          ;change the display to acknowledge input
+           MOVB  pressed_num,entered_password+1  ;store the read value into the password            
+           LDD   #disp
+           jsr  display_string
+           ;LBRA  Return
+           
+           MOVB   #$FF,await_key_release           
+           jsr Keypad                  ;read a keypress
+           movb  #'*',disp+18          ;change the display to acknowledge input
+           MOVB  pressed_num,entered_password+2  ;store the read value into the password
+           LDD   #disp
+           jsr  display_string
+           
+           MOVB   #$FF,await_key_release                      
+           jsr Keypad                  ;read a keypress
+           movb  #'*',disp+19          ;change the display to acknowledge input
+           MOVB  pressed_num,entered_password+3  ;store the read value into the password
+           LDD   #disp
+           jsr  display_string                      
+           
+           MOVB   #$FF,await_key_release
+           jsr Keypad                  ;read a keypress
+           movb  #'*',disp+20          ;change the display to acknowledge input
+           MOVB  pressed_num,entered_password+4  ;store the read value into the password
+           LDD   #disp
+           jsr  display_string
+           
+           MOVB   #$FF,await_key_release           
+           jsr Keypad                  ;read a keypress
+           movb  #'*',disp+21          ;change the display to acknowledge input
+           MOVB  pressed_num,entered_password+5  ;store the read value into the password
+           LDD   #disp
+           jsr  display_string
+           
+           MOVB   #$FF,await_key_release           
+           jsr Keypad                  ;read a keypress
+           movb  #'*',disp+22          ;change the display to acknowledge input
+           MOVB  pressed_num,entered_password+6  ;store the read value into the password 
+           LDD   #disp
+           jsr  display_string             
+           
+           MOVB   #$FF,await_key_release          
+           jsr Keypad                  ;read a keypress
+           movb  #'*',disp+23          ;change the display to acknowledge input
+           MOVB  pressed_num,entered_password+7  ;store the read value into the password
+           LDD   #disp
+           jsr  display_string
+           
+           ;check if the password is correct
+           LDX    #password
+           LDY    #entered_password
+           
+           ;read the current password character and compare it to the new password character
+           ;this resets if the password is incorrect
+           ;1.
+           LDAA   0,X
+           LDAB   0,Y
+           CBA
+           LBNE    PasswordReset
+           
+           INX
+           INY
+           
+           ;2.
+           LDAA   0,X
+           LDAB   0,Y
+           CBA
+           LBNE    PasswordReset
+           
+           INX
+           INY
+           
+           ;3.
+           LDAA   0,X
+           LDAB   0,Y
+           CBA
+           LBNE    PasswordReset
+           
+           INX
+           INY
+           
+           ;4.
+           LDAA   0,X
+           LDAB   0,Y
+           CBA
+           LBNE    PasswordReset
+           
+           INX
+           INY
+           
+           ;5.
+           LDAA   0,X
+           LDAB   0,Y
+           CBA
+           LBNE    PasswordReset
+           
+           INX
+           INY
+           
+           ;6.
+           LDAA   0,X
+           LDAB   0,Y
+           CBA
+           LBNE    PasswordReset
+           
+           INX
+           INY
+           
+           ;7.
+           LDAA   0,X
+           LDAB   0,Y
+           CBA
+           LBNE    PasswordReset
+           
+           INX
+           INY
+           
+           ;8.
+           LDAA   0,X
+           LDAB   0,Y
+           CBA
+           LBNE    PasswordReset
+           
+                      ;inital prompt
+           movb #'N',disp
+           movb #'e',disp+1
+           movb #'w',disp+2
+           movb #' ',disp+3
+           movb #'p',disp+4
+           movb #'a',disp+5
+           movb #'s',disp+6
+           movb #'s',disp+7
+           movb #'w',disp+8
+           movb #'o',disp+9
+           movb #'r',disp+10
+           movb #'d',disp+11
+           movb #':',disp+12
+           movb #' ',disp+13
+           movb #' ',disp+14
+           movb #' ',disp+15
+           ;next line
+           movb #'_',disp+16
+           movb #'_',disp+17
+           movb #'_',disp+18
+           movb #'_',disp+19
+           movb #'_',disp+20
+           movb #'_',disp+21
+           movb #'_',disp+22
+           movb #'_',disp+23
+           movb #' ',disp+24
+           movb #' ',disp+25
+           movb #' ',disp+26
+           movb #' ',disp+27
+           movb #' ',disp+28
+           movb #' ',disp+29
+           movb #' ',disp+30
+           movb #' ',disp+31
+           movb #0,disp+32    ;string terminator, acts like '\0'
+		       
+		       ;print the prompt string
+		       LDD   #disp         ;both of these steps are necessary to
+           jsr  display_string ;print to the LCD screen
+
+
+           ;AWAIT KEYPRESS
+           movb   #$FF,await_key_press
+           
+           ;READ EACH CHARACTER
+           MOVB   #$FF,await_key_release     
+           jsr Keypad                  ;read a keypress
+           movb  #'*',disp+16          ;change the display to acknowledge input
+           MOVB  pressed_num,password  ;store the read value into the password
+           LDD   #disp
+           jsr  display_string
+           ;LBRA  Return
+               
+           MOVB   #$FF,await_key_release           
+           jsr Keypad                  ;read a keypress
+           movb  #'*',disp+17          ;change the display to acknowledge input
+           MOVB  pressed_num,password+1  ;store the read value into the password            
+           LDD   #disp
+           jsr  display_string
+           ;LBRA  Return
+           
+           MOVB   #$FF,await_key_release           
+           jsr Keypad                  ;read a keypress
+           movb  #'*',disp+18          ;change the display to acknowledge input
+           MOVB  pressed_num,password+2  ;store the read value into the password
+           LDD   #disp
+           jsr  display_string
+           
+           MOVB   #$FF,await_key_release                      
+           jsr Keypad                  ;read a keypress
+           movb  #'*',disp+19          ;change the display to acknowledge input
+           MOVB  pressed_num,password+3  ;store the read value into the password
+           LDD   #disp
+           jsr  display_string                      
+           
+           MOVB   #$FF,await_key_release
+           jsr Keypad                  ;read a keypress
+           movb  #'*',disp+20          ;change the display to acknowledge input
+           MOVB  pressed_num,password+4  ;store the read value into the password
+           LDD   #disp
+           jsr  display_string
+           
+           MOVB   #$FF,await_key_release           
+           jsr Keypad                  ;read a keypress
+           movb  #'*',disp+21          ;change the display to acknowledge input
+           MOVB  pressed_num,password+5  ;store the read value into the password
+           LDD   #disp
+           jsr  display_string
+           
+           MOVB   #$FF,await_key_release           
+           jsr Keypad                  ;read a keypress
+           movb  #'*',disp+22          ;change the display to acknowledge input
+           MOVB  pressed_num,password+6  ;store the read value into the password 
+           LDD   #disp
+           jsr  display_string             
+           
+           MOVB   #$FF,await_key_release          
+           jsr Keypad                  ;read a keypress
+           movb  #'*',disp+23          ;change the display to acknowledge input
+           MOVB  pressed_num,password+7  ;store the read value into the password
+           LDD   #disp
+           jsr  display_string
+           
+           ;password has been reset
+           MOVB  #$00,pw_reset
+
+           LBRA    Return
+
+PasswordCheck:
+                      ;MOVB   #$FF,
+            
+            
+           ;inital prompt
+           movb #'E',disp
+           movb #'n',disp+1
+           movb #'t',disp+2
+           movb #'e',disp+3
+           movb #'r',disp+4
+           movb #' ',disp+5
+           movb #'p',disp+6
+           movb #'a',disp+7
+           movb #'s',disp+8
+           movb #'s',disp+9
+           movb #'w',disp+10
+           movb #'o',disp+11
+           movb #'r',disp+12
+           movb #'d',disp+13
+           movb #':',disp+14
+           movb #' ',disp+15
+           ;next line
+           movb #'_',disp+16
+           movb #'_',disp+17
+           movb #'_',disp+18
+           movb #'_',disp+19
+           movb #'_',disp+20
+           movb #'_',disp+21
+           movb #'_',disp+22
+           movb #'_',disp+23
+           movb #' ',disp+24
+           movb #' ',disp+25
+           movb #' ',disp+26
+           movb #' ',disp+27
+           movb #' ',disp+28
+           movb #' ',disp+29
+           movb #' ',disp+30
+           movb #' ',disp+31
+           movb #0,disp+32    ;string terminator, acts like '\0'
+		       
+		       ;print the prompt string
+		       LDD   #disp         ;both of these steps are necessary to
+           jsr  display_string ;print to the LCD screen
+
+
+           ;AWAIT KEYPRESS
+           movb   #$FF,await_key_press
+           
+           ;READ EACH CHARACTER
+           MOVB   #$FF,await_key_release     
+           jsr Keypad                  ;read a keypress
+           movb  #'*',disp+16          ;change the display to acknowledge input
+           MOVB  pressed_num,entered_password  ;store the read value into the password
+           LDD   #disp
+           jsr  display_string
+           ;LBRA  Return
+               
+           MOVB   #$FF,await_key_release           
+           jsr Keypad                  ;read a keypress
+           movb  #'*',disp+17          ;change the display to acknowledge input
+           MOVB  pressed_num,entered_password+1  ;store the read value into the password            
+           LDD   #disp
+           jsr  display_string
+           ;LBRA  Return
+           
+           MOVB   #$FF,await_key_release           
+           jsr Keypad                  ;read a keypress
+           movb  #'*',disp+18          ;change the display to acknowledge input
+           MOVB  pressed_num,entered_password+2  ;store the read value into the password
+           LDD   #disp
+           jsr  display_string
+           
+           MOVB   #$FF,await_key_release                      
+           jsr Keypad                  ;read a keypress
+           movb  #'*',disp+19          ;change the display to acknowledge input
+           MOVB  pressed_num,entered_password+3  ;store the read value into the password
+           LDD   #disp
+           jsr  display_string                      
+           
+           MOVB   #$FF,await_key_release
+           jsr Keypad                  ;read a keypress
+           movb  #'*',disp+20          ;change the display to acknowledge input
+           MOVB  pressed_num,entered_password+4  ;store the read value into the password
+           LDD   #disp
+           jsr  display_string
+           
+           MOVB   #$FF,await_key_release           
+           jsr Keypad                  ;read a keypress
+           movb  #'*',disp+21          ;change the display to acknowledge input
+           MOVB  pressed_num,entered_password+5  ;store the read value into the password
+           LDD   #disp
+           jsr  display_string
+           
+           MOVB   #$FF,await_key_release           
+           jsr Keypad                  ;read a keypress
+           movb  #'*',disp+22          ;change the display to acknowledge input
+           MOVB  pressed_num,entered_password+6  ;store the read value into the password 
+           LDD   #disp
+           jsr  display_string             
+           
+           MOVB   #$FF,await_key_release          
+           jsr Keypad                  ;read a keypress
+           movb  #'*',disp+23          ;change the display to acknowledge input
+           MOVB  pressed_num,entered_password+7  ;store the read value into the password
+           LDD   #disp
+           jsr  display_string
+           
+           ;check if the password is correct
+           LDX    #password
+           LDY    #entered_password
+           
+           ;read the current password character and compare it to the new password character
+           ;this resets if the password is incorrect
+           ;1.
+           LDAA   0,X
+           LDAB   0,Y
+           CBA
+           LBNE    PasswordCheck
+           
+           INX
+           INY
+           
+           ;2.
+           LDAA   0,X
+           LDAB   0,Y
+           CBA
+           LBNE    PasswordCheck
+           
+           INX
+           INY
+           
+           ;3.
+           LDAA   0,X
+           LDAB   0,Y
+           CBA
+           LBNE    PasswordCheck
+           
+           INX
+           INY
+           
+           ;4.
+           LDAA   0,X
+           LDAB   0,Y
+           CBA
+           LBNE    PasswordCheck
+           
+           INX
+           INY
+           
+           ;5.
+           LDAA   0,X
+           LDAB   0,Y
+           CBA
+           LBNE    PasswordCheck
+           
+           INX
+           INY
+           
+           ;6.
+           LDAA   0,X
+           LDAB   0,Y
+           CBA
+           LBNE    PasswordCheck
+           
+           INX
+           INY
+           
+           ;7.
+           LDAA   0,X
+           LDAB   0,Y
+           CBA
+           LBNE    PasswordCheck
+           
+           INX
+           INY
+           
+           ;8.
+           LDAA   0,X
+           LDAB   0,Y
+           CBA
+           LBNE    PasswordCheck
+           
+           CLR    pw_required
+           
+           BRA    Return           
+            
+Return:    
+            ;here, set the pressed number to something impossible so that
+            ;the password input doesn't spill into other code
+            MOVB  #$FF,pressed_num    ;set the pressed_num to something impossible
+            ;restore registers and accumulators
+            PULY
+            PULX
+            PULD
+            PULB
+            PULA
+            
+            RTS

Final_Project/Sources/potentiometer.c

@@ -0,0 +1,23 @@
+#include "derivative.h"
+#include "funct.h"
+
+unsigned int pot_value;
+
+void read_pot(void)
+{
+	//turn on A/D
+	ATDCTL2 = 0x80;
+
+	//wait for power-up
+	Delay(2);
+
+	//start conversion channel 0
+	ATDCTL5 = 0;
+
+	//wait for conversion complete
+	while(!(ATDSTAT0 & 0x80))
+		;
+
+	//get data
+	pot_value = ATDDR0H;
+}			

Final_Project/Sources/wall.asm

@@ -0,0 +1,233 @@
+	XDEF	Wall
+	XREF	__SEG_END_SSTACK,display_time,display_string,disp
+  ;counters and variables
+  XREF  current_year,current_month,current_day,current_hour,current_minute,current_second
+  
+	;events
+	XREF  second_passed
+	
+	;debug
+	XREF  byte_out,word_out
+	
+clock_digits: Section
+;digits to display
+seconds_tens  ds.b  1
+seconds_ones  ds.b  1
+minutes_tens  ds.b  1
+minutes_ones  ds.b  1
+hours_tens    ds.b  1
+hours_ones    ds.b  1
+
+clock_code:   Section	
+Wall: ;push register and accumulator values for retention                   
+            PSHA
+            PSHB
+            PSHD
+            PSHX
+            PSHY
+            
+            ;handle the event that fires evey second
+            LDAA  second_passed
+            CMPA  #$FF
+            LBNE   PrintWall       ;display time between seconds
+            
+            ;if a second has passed
+            LDAA  current_second
+            INCA                  ;increment the seconds counter
+            STAA  current_second
+            CMPA  #60             ;less than a minute has passed
+            LBLT   PrintWall       ;display the time if required
+            CLR   current_second  ;resest the seconds counter to zero
+            
+            ;one minute has passed
+            LDAA  current_minute
+            INCA
+            STAA  current_minute
+            CMPA  #60
+            LBLT   PrintWall
+            CLR   current_minute
+            
+            ;one hour has passed
+            LDAA  current_hour
+            INCA
+            STAA  current_hour
+            CMPA  #24
+            LBLT   PrintWall
+            CLR   current_hour
+            
+            ;one day has passed (30 days in a month)
+            LDAA  current_day
+            INCA  
+            STAA  current_day
+            CMPA  #30
+            LBLT   PrintWall
+            MOVB  #$01,current_day
+            
+            ;one month has passed
+            LDAA  current_month
+            INCA
+            STAA  current_month
+            CMPA  #12
+            LBLT   PrintWall
+            MOVB  #$01,current_month
+            
+            ;one year has passed
+            LDX   current_year
+            INX
+            STX  current_year
+            ;no need to do anything else, years counts up indefinitely
+            
+SetWall:
+           movb #'M',disp
+           movb #'M',disp+1
+           movb #'/',disp+2
+           movb #'D',disp+3
+           movb #'D',disp+4
+           movb #'/',disp+5
+           movb #'Y',disp+6
+           movb #'Y',disp+7
+           movb #'Y',disp+8
+           movb #'Y',disp+9
+           movb #' ',disp+10
+           movb #'h',disp+11
+           movb #'h',disp+12
+           movb #':',disp+13
+           movb #'m',disp+14
+           movb #'m',disp+15
+           ;
+           ;next line
+           ;
+           movb #'_',disp+16
+           movb #'_',disp+17
+           movb #'/',disp+18
+           movb #'_',disp+19                                                                                                      
+           movb #'_',disp+20
+           movb #'/',disp+21
+           movb #'_',disp+22
+           movb #'_',disp+23
+           movb #'_',disp+24
+           movb #'_',disp+25
+           movb #' ',disp+26
+           movb #'_',disp+27
+           movb #'_',disp+28
+           movb #':',disp+29
+           
+           movb #'_',disp+30
+           movb #'_',disp+31
+           movb #0,disp+32    ;string terminator, acts like '\0'
+            
+            
+PrintWall: 
+
+           ;check if the time should show
+           LDAA  display_time
+           CMPA  #$00
+           LBEQ  Return
+           
+           ;if the time should show, calculate the ASCII values
+           ; (seconds)
+           LDX    #10		          ;load the bottom part of the divide (forget what it's called)
+           LDD    current_second  ;two-digit seconds number
+           IDIV                   ;D / X -> X (remainder D) (D has the one's place and X has the 10's)
+           
+           ADDD   #$30            ;convert the one's place to ascii
+           STAB   seconds_ones
+           XGDX
+           ADDD   #$30
+           STAB   seconds_tens
+           
+           ;from lab 6.3
+           ;XGDX                   ;X <-> D, X will now have the 1's and D has the 10's
+           ;ADDD   #$30            ;convert to ASCII
+           ;STAB   seconds_tens    ;lower byte of d has the 10's place for the seconds
+           ;STAB   word_out
+           ;XGDX                   ;swap back X and D (X still has the 1's)
+           ;ADDD   #$30            ;conver the ones place to ASCII
+           ;STAB   seconds_ones    ;X has the remainer, i.e. the one's place
+           ;STAB   byte_out
+           
+           ;STAB   byte_out
+           ;STX    word_out 
+           
+           ; (minutes)
+           ;LDX    #10		          ;load the bottom part of the divide (forget what it's called)
+           ;LDD    current_minute  ;two-digit minutes number
+           ;IDIV                   ;D / X -> X (remainder D)
+           ;XGDX                   ;X <-> D, X now has remainder and D has quotient
+           ;ADDD   #$30            ;convert to ASCII
+           ;STAB   minutes_tens     ;lower byte of d has the 10's place for the seconds
+           ;STX    minutes_ones    ;X has the remainer, i.e. the one's place 
+           
+           ;print the time and date (includes placeholders)
+           movb #'D',disp
+           movb #'a',disp+1
+           movb #'t',disp+2
+           movb #'e',disp+3
+           movb #':',disp+4
+           movb #' ',disp+5
+           ;month
+           movb #'1',disp+6
+           movb #'2',disp+7
+           movb #'/',disp+8
+           ;day
+           movb #'0',disp+9
+           movb #'2',disp+10
+           movb #'/',disp+11
+           ;year
+           movb #'1',disp+12
+           movb #'9',disp+13
+           movb #'9',disp+14
+           movb #'3',disp+15
+           ;
+           ;next line
+           ;
+           movb #'T',disp+16
+           movb #'i',disp+17
+           movb #'m',disp+18
+           movb #'e',disp+19                                                                                                      
+           movb #':',disp+20
+           movb #' ',disp+21
+           
+           ;hour
+           movb #'1',disp+22
+           movb #'1',disp+23
+           
+           movb #':',disp+24
+           ;minute
+           movb #'1',disp+25
+           movb #'1',disp+26
+           
+           movb #':',disp+27
+           ;seconds
+           ;movb #'1',disp+28
+           ;movb #'8',disp+29
+           
+           movb #' ',disp+30
+           movb #' ',disp+31
+           movb #0,disp+32    ;string terminator, acts like '\0'
+           
+           ;store out calculated ascii values in the appropriate places in the display
+           MOVB   seconds_tens,disp+28
+           MOVB   seconds_ones,disp+29
+           
+           ;MOVB   minutes_tens,disp+25
+           ;MOVB   minutes_ones,disp+26
+           
+           LDD   #disp         ;both of these steps are necessary to
+           jsr  display_string ;print to the LCD screen          
+
+Return:     
+            ;clear the flag that is set evey second
+            CLR   second_passed
+            
+            ;restore registers and accumulators
+            PULY
+            PULX
+            PULD
+            PULB
+            PULA
+            
+            RTS
+   
+	
+	

Final_Project/Sources/water.asm

@@ -0,0 +1,98 @@
+  XDEF	Water
+	XREF	__SEG_END_SSTACK,grow_lights,PORT_T,display_string,disp,is_watering,PORT_S,PORT_P,sprinkler_event,word_out,SPRINKLER_ARR,byte_out,sprinkler_arr_i
+
+
+Constants:	     Section
+;STEP_ARR   	dc.b  $0A,$12,$14,$0C,$0 ;array sequence to spin motor
+ARRAY_LENGTH  dc.b  $04
+Variables:        Section
+	
+	
+Water:      ;push register and accumulator values for retention                   
+            PSHA
+            PSHB
+            PSHD
+            PSHX
+            PSHY
+
+            ;get out of here if we should not be watering (don't do anything with sprinkler) or the display
+            LDAB  is_watering
+            CMPB  #$FF
+            LBNE  Return
+            
+            ;sprinkler stuff
+            LDAB    sprinkler_event   ;check the event flag
+            CMPB    #$FF              ;all 1's indicates that the event has fired, if it's not equal, show watering
+            LBNE    ShowWatering      ;still display the watering... message
+            
+            ;handle sprinkle event
+            LDAB    sprinkler_arr_i       ;check which array position we are at
+            INCB                      ;go to next index
+            STAB    sprinkler_arr_i       ; ^
+            CMPB    #8                ;check if we have reached the end of the array
+            BLT     Continue          ;continue if not at the end of the array
+            MOVB    #$00,sprinkler_arr_i  ;reset the array index to the beginning
+            LDAB    #$00
+Continue:   
+            LDX     #SPRINKLER_ARR
+            ABX
+            STX     word_out         
+            LDAA    0,X
+            STAA    PORT_P
+            STAB    byte_out
+            
+            
+            CLR       sprinkler_event
+            
+                                      ;...
+ShowWatering:
+          ;print the temperature
+           movb #'W',disp
+           movb #'a',disp+1
+           movb #'t',disp+2
+           movb #'e',disp+3
+           movb #'r',disp+4
+           movb #'i',disp+5
+           movb #'n',disp+6
+           movb #'g',disp+7
+           movb #'.',disp+8
+           movb #'.',disp+9
+           movb #'.',disp+10
+           movb #' ',disp+11
+           movb #' ',disp+12
+           movb #' ',disp+13
+           movb #' ',disp+14
+           movb #' ',disp+15
+           ;next line
+           movb #' ',disp+16
+           movb #' ',disp+17
+           movb #' ',disp+18
+           movb #' ',disp+19
+           movb #' ',disp+20
+           movb #' ',disp+21
+           movb #' ',disp+22
+           movb #' ',disp+23
+           movb #' ',disp+24
+           movb #' ',disp+25
+           movb #' ',disp+26
+           movb #' ',disp+27
+           movb #' ',disp+28
+           movb #' ',disp+29
+           movb #' ',disp+30
+           movb #' ',disp+31
+           movb #0,disp+32    ;string terminator, acts like '\0'
+           
+           LDD  #disp         ;both of these steps are necessary to
+           jsr  display_string ;print to the LCD screen           
+    
+Return:     ;restore registers and accumulators
+            PULY
+            PULX
+            PULD
+            PULB
+            PULA
+            
+            RTS
+   
+	
+	

Final_Project/bin/IRQ_ISR.dbg

@@ -0,0 +1,5 @@
+              XDEF      IRQ_ISR
+
+IRQ_ISR:      
+
+

Final_Project/bin/Project.abs.phy

@@ -0,0 +1,149 @@
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Final_Project/bin/Project.map

@@ -0,0 +1,1928 @@
+*** EVALUATION ***
+PROGRAM "C:\Users\shcorya\OneDrive - Indiana University\362\Final_Project\bin\Project.abs"
+
+*********************************************************************************************
+TARGET SECTION
+---------------------------------------------------------------------------------------------
+Processor   : Freescale HC12
+Memory Model: SMALL
+File Format : ELF\DWARF 2.0
+Linker      : SmartLinker V-5.0.40 Build 10203, Jul 23 2010
+
+*********************************************************************************************
+FILE SECTION
+---------------------------------------------------------------------------------------------
+main.asm.o                              Model: SMALL,         Lang: Assembler
+lcddisp.c.o                             Model: SMALL,         Lang: ANSI-C
+mc9s12e128.c.o                          Model: SMALL,         Lang: ANSI-C
+potentiometer.c.o                       Model: SMALL,         Lang: ANSI-C
+IRQ_ISR.asm.o                           Model: SMALL,         Lang: Assembler
+circulation.asm.o                       Model: SMALL,         Lang: Assembler
+debounce.asm.o                          Model: SMALL,         Lang: Assembler
+eventloop.asm.o                         Model: SMALL,         Lang: Assembler
+growlights.asm.o                        Model: SMALL,         Lang: Assembler
+menu.asm.o                              Model: SMALL,         Lang: Assembler
+password.asm.o                          Model: SMALL,         Lang: Assembler
+keypad.asm.o                            Model: SMALL,         Lang: Assembler
+water.asm.o                             Model: SMALL,         Lang: Assembler
+wall.asm.o                              Model: SMALL,         Lang: Assembler
+
+*********************************************************************************************
+STARTUP SECTION
+---------------------------------------------------------------------------------------------
+Entry point: 0xC000 (_Startup)
+
+*********************************************************************************************
+SECTION-ALLOCATION SECTION
+Section Name                    Size  Type     From       To       Segment
+---------------------------------------------------------------------------------------------
+.init                            242     R     0xC000     0xC0F1   ROM_C000
+NON_BANKED                       267     R     0xC0F2     0xC1FC   ROM_C000
+.stack                           256   R/W      0x400      0x4FF   RAM
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+.abs_section_1a2                   2   N/I      0x1A2      0x1A3   .absSeg240
+.abs_section_1ec                   2   N/I      0x1EC      0x1ED   .absSeg241
+.abs_section_1ee                   2   N/I      0x1EE      0x1EF   .absSeg242
+.abs_section_1f0                   2   N/I      0x1F0      0x1F1   .absSeg243
+.abs_section_1f2                   2   N/I      0x1F2      0x1F3   .absSeg244
+.abs_section_1f4                   2   N/I      0x1F4      0x1F5   .absSeg245
+.abs_section_1f6                   2   N/I      0x1F6      0x1F7   .absSeg246
+.abs_section_1f8                   2   N/I      0x1F8      0x1F9   .absSeg247
+.abs_section_1fa                   2   N/I      0x1FA      0x1FB   .absSeg248
+.abs_section_1fc                   2   N/I      0x1FC      0x1FD   .absSeg249
+.abs_section_210                   2   N/I      0x210      0x211   .absSeg250
+.abs_section_212                   2   N/I      0x212      0x213   .absSeg251
+.abs_section_214                   2   N/I      0x214      0x215   .absSeg252
+.abs_section_216                   2   N/I      0x216      0x217   .absSeg253
+.abs_section_218                   2   N/I      0x218      0x219   .absSeg254
+.abs_section_21a                   2   N/I      0x21A      0x21B   .absSeg255
+.abs_section_222                   2   N/I      0x222      0x223   .absSeg256
+.abs_section_224                   2   N/I      0x224      0x225   .absSeg257
+.abs_section_226                   2   N/I      0x226      0x227   .absSeg258
+.abs_section_22a                   2   N/I      0x22A      0x22B   .absSeg259
+.abs_section_22c                   2   N/I      0x22C      0x22D   .absSeg260
+.abs_section_22e                   2   N/I      0x22E      0x22F   .absSeg261
+.abs_section_232                   2   N/I      0x232      0x233   .absSeg262
+.abs_section_234                   2   N/I      0x234      0x235   .absSeg263
+.abs_section_236                   2   N/I      0x236      0x237   .absSeg264
+.abs_section_270                   2   N/I      0x270      0x271   .absSeg265
+.abs_section_272                   2   N/I      0x272      0x273   .absSeg266
+.abs_section_274                   2   N/I      0x274      0x275   .absSeg267
+.abs_section_276                   2   N/I      0x276      0x277   .absSeg268
+.abs_section_278                   2   N/I      0x278      0x279   .absSeg269
+.abs_section_27a                   2   N/I      0x27A      0x27B   .absSeg270
+.abs_section_27c                   2   N/I      0x27C      0x27D   .absSeg271
+.abs_section_27e                   2   N/I      0x27E      0x27F   .absSeg272
+.bss                               2   R/W      0x500      0x501   RAM
+my_constant                       29     R     0xC1FD     0xC219   ROM_C000
+my_variable                      104   R/W      0x502      0x569   RAM
+.common                            2   R/W      0x56A      0x56B   RAM
+circulation.asm._SEC000000        219     R     0xC21A     0xC2F4   ROM_C000
+debounce.asm._SEC000000            9     R     0xC2F5     0xC2FD   ROM_C000
+eventloop.asm._SEC000000         465     R     0xC2FE     0xC4CE   ROM_C000
+growlights.asm._SEC000000         17     R     0xC4CF     0xC4DF   ROM_C000
+Code                            2668     R     0xC4E0     0xCF4B   ROM_C000
+Variables                        237     R     0xCF4C     0xD038   ROM_C000
+clock_code                       483     R     0xD039     0xD21B   ROM_C000
+clock_digits                       6   R/W      0x56C      0x571   RAM
+.vectSeg273_vect                   4     R     0xFFF0     0xFFF3   .vectSeg273
+.vectSeg274_vect                   2     R     0xFFFE     0xFFFF   .vectSeg274
+
+Summary of section sizes per section type:
+READ_ONLY (R):        1222 (dec:     4642)
+READ_WRITE (R/W):      172 (dec:      370)
+NO_INIT (N/I):         160 (dec:      352)
+
+*********************************************************************************************
+VECTOR-ALLOCATION SECTION
+    Address     InitValue   InitFunction
+---------------------------------------------------------------------------------------------
+     0xFFF0        0xC2FE   RTI_ISR
+     0xFFF2         0x56C   IRQ_ISR
+     0xFFFE        0xC000   _Startup
+
+*********************************************************************************************
+OBJECT-ALLOCATION SECTION
+     Name               Module                 Addr   hSize   dSize     Ref    Section   RLIB
+---------------------------------------------------------------------------------------------
+MODULE:                 -- main.asm.o --
+- PROCEDURES:
+     Entry                                     C000      BD     189       0   .init       
+     _Startup                                  C000       0       0       0   .init       
+     Init                                      C0BD      14      20       0   .init       
+     Main                                      C0D1      21      33       0   .init       
+- VARIABLES:
+     disp                                       502      21      33     477   my_variable 
+     password                                   523       8       8      26   my_variable 
+     entered_password                           52B       8       8      18   my_variable 
+     new_password                               533       8       8       0   my_variable 
+     pw_prompt_shown                            53B       1       1       0   my_variable 
+     pw_check                                   53C       1       1       1   my_variable 
+     pw_correct                                 53D       1       1       1   my_variable 
+     pw_set                                     53E       1       1       6   my_variable 
+     pw_incorrect                               53F       1       1       1   my_variable 
+     pw_required                                540       1       1       2   my_variable 
+     pressed_key                                541       1       1       2   my_variable 
+     pressed_num                                542       1       1      43   my_variable 
+     await_key_release                          543       1       1      35   my_variable 
+     await_key_press                            544       1       1       7   my_variable 
+     menu_active                                545       1       1       9   my_variable 
+     toast_timer                                546       2       2       5   my_variable 
+     menu_option_num                            548       1       1       5   my_variable 
+     menu_timer                                 549       2       2       5   my_variable 
+     display_timeout                            54B       1       1       0   my_variable 
+     is_watering                                54C       1       1       8   my_variable 
+     watering_timer                             54D       2       2       6   my_variable 
+     sprinkler_event                            54F       1       1       4   my_variable 
+     sprinkler_timer                            550       1       1       5   my_variable 
+     sprinkler_arr_i                            551       1       1       4   my_variable 
+     show_temperature                           552       1       1       7   my_variable 
+     fan_speed                                  553       1       1       3   my_variable 
+     circulation_count                          554       1       1       4   my_variable 
+     dc_on                                      555       1       1       3   my_variable 
+     display_time                               556       1       1       7   my_variable 
+     current_year                               557       2       2       3   my_variable 
+     current_month                              559       1       1       4   my_variable 
+     current_day                                55A       1       1       4   my_variable 
+     current_hour                               55B       1       1       4   my_variable 
+     current_minute                             55C       1       1       4   my_variable 
+     current_second                             55D       1       1       5   my_variable 
+     wall_timer                                 55E       2       2       6   my_variable 
+     clock_event                                560       1       1       1   my_variable 
+     ms_counter                                 561       2       2       4   my_variable 
+     second_passed                              563       1       1       4   my_variable 
+     setting_wall                               564       1       1       0   my_variable 
+     change_time                                565       1       1       1   my_variable 
+     pw_reset                                   566       1       1       5   my_variable 
+     word_out                                   567       2       2       2   my_variable 
+     byte_out                                   569       1       1       1   my_variable 
+     KVS                                       C1FD      10      16       1   my_constant 
+     SEQUENCE                                  C20D       5       5       1   my_constant 
+     SPRINKLER_ARR                             C212       8       8       1   my_constant 
+- LABELS:
+     __SEG_END_SSTACK                           500       0       0       1               
+     CRGFLG                                      37       0       0       1   .text       
+     PORT_T                                     240       0       0       3   .text       
+     DDR_T                                      242       0       0       0   .text       
+     PORT_S                                     248       0       0       1   .text       
+     DDR_S                                      24A       0       0       0   .text       
+     PORT_P                                     258       0       0       1   .text       
+     DDR_P                                      25A       0       0       0   .text       
+     PORT_U                                     268       0       0       3   .text       
+     PDR_U                                      26C       0       0       0   .text       
+     PSR_U                                      26D       0       0       0   .text       
+MODULE:                 -- lcddisp.c.o --
+- PROCEDURES:
+     delay_ms                                  C0F2      17      23       5   NON_BANKED  
+     init_LCD                                  C109      52      82       1   NON_BANKED  
+     display_string                            C15B      38      56      46   NON_BANKED  
+     Delay                                     C193      1F      31       1   NON_BANKED  
+     epulse                                    C1B2      24      36       3   NON_BANKED  
+     sendCommand                               C1D6       F      15       7   NON_BANKED  
+- VARIABLES:
+     data                                       500       2       2       4   .bss        
+MODULE:                 -- mc9s12e128.c.o --
+- PROCEDURES:
+- VARIABLES:
+     _PORTE                                       8       1       1       0   .abs_section_8
+     _DDRE                                        9       1       1       0   .abs_section_9
+     _PEAR                                        A       1       1       0   .abs_section_a
+     _MODE                                        B       1       1       0   .abs_section_b
+     _PUCR                                        C       1       1       0   .abs_section_c
+     _RDRIV                                       D       1       1       0   .abs_section_d
+     _EBICTL                                      E       1       1       0   .abs_section_e
+     _INITRM                                     10       1       1       0   .abs_section_10
+     _INITRG                                     11       1       1       0   .abs_section_11
+     _MISC                                       13       1       1       0   .abs_section_13
+     _ITCR                                       15       1       1       0   .abs_section_15
+     _ITEST                                      16       1       1       0   .abs_section_16
+     _VREGCTRL                                   19       1       1       0   .abs_section_19
+     _MEMSIZ0                                    1C       1       1       0   .abs_section_1c
+     _MEMSIZ1                                    1D       1       1       0   .abs_section_1d
+     _INTCR                                      1E       1       1       0   .abs_section_1e
+     _HPRIO                                      1F       1       1       0   .abs_section_1f
+     _DBGC1                                      20       1       1       0   .abs_section_20
+     _DBGSC                                      21       1       1       0   .abs_section_21
+     _DBGCNT                                     24       1       1       0   .abs_section_24
+     _DBGCCX                                     25       1       1       0   .abs_section_25
+     _DBGC2                                      28       1       1       0   .abs_section_28
+     _DBGC3                                      29       1       1       0   .abs_section_29
+     _DBGCAX                                     2A       1       1       0   .abs_section_2a
+     _DBGCBX                                     2D       1       1       0   .abs_section_2d
+     _PPAGE                                      30       1       1       0   .abs_section_30
+     _PORTK                                      32       1       1       0   .abs_section_32
+     _DDRK                                       33       1       1       0   .abs_section_33
+     _SYNR                                       34       1       1       0   .abs_section_34
+     _REFDV                                      35       1       1       0   .abs_section_35
+     _CRGFLG                                     37       1       1       0   .abs_section_37
+     _CRGINT                                     38       1       1       0   .abs_section_38
+     _CLKSEL                                     39       1       1       0   .abs_section_39
+     _PLLCTL                                     3A       1       1       0   .abs_section_3a
+     _RTICTL                                     3B       1       1       0   .abs_section_3b
+     _COPCTL                                     3C       1       1       0   .abs_section_3c
+     _ARMCOP                                     3F       1       1       0   .abs_section_3f
+     _TIM0_TIOS                                  40       1       1       0   .abs_section_40
+     _TIM0_CFORC                                 41       1       1       0   .abs_section_41
+     _TIM0_OC7M                                  42       1       1       0   .abs_section_42
+     _TIM0_OC7D                                  43       1       1       0   .abs_section_43
+     _TIM0_TSCR1                                 46       1       1       0   .abs_section_46
+     _TIM0_TTOV                                  47       1       1       0   .abs_section_47
+     _TIM0_TCTL1                                 48       1       1       0   .abs_section_48
+     _TIM0_TCTL3                                 4A       1       1       0   .abs_section_4a
+     _TIM0_TIE                                   4C       1       1       0   .abs_section_4c
+     _TIM0_TSCR2                                 4D       1       1       0   .abs_section_4d
+     _TIM0_TFLG1                                 4E       1       1       0   .abs_section_4e
+     _TIM0_TFLG2                                 4F       1       1       0   .abs_section_4f
+     _TIM0_PACTL                                 60       1       1       0   .abs_section_60
+     _TIM0_PAFLG                                 61       1       1       0   .abs_section_61
+     _ATDSTAT0                                   86       1       1       1   .abs_section_86
+     _ATDTEST1                                   89       1       1       0   .abs_section_89
+     _ATDSTAT2                                   8A       1       1       0   .abs_section_8a
+     _ATDSTAT1                                   8B       1       1       0   .abs_section_8b
+     _PORTAD0                                    8E       1       1       0   .abs_section_8e
+     _PORTAD1                                    8F       1       1       0   .abs_section_8f
+     _SCI0CR1                                    CA       1       1       0   .abs_section_ca
+     _SCI0CR2                                    CB       1       1       0   .abs_section_cb
+     _SCI0SR1                                    CC       1       1       0   .abs_section_cc
+     _SCI0SR2                                    CD       1       1       0   .abs_section_cd
+     _SCI0DRH                                    CE       1       1       0   .abs_section_ce
+     _SCI0DRL                                    CF       1       1       0   .abs_section_cf
+     _SCI1CR1                                    D2       1       1       0   .abs_section_d2
+     _SCI1CR2                                    D3       1       1       0   .abs_section_d3
+     _SCI1SR1                                    D4       1       1       0   .abs_section_d4
+     _SCI1SR2                                    D5       1       1       0   .abs_section_d5
+     _SCI1DRH                                    D6       1       1       0   .abs_section_d6
+     _SCI1DRL                                    D7       1       1       0   .abs_section_d7
+     _SPICR1                                     D8       1       1       0   .abs_section_d8
+     _SPICR2                                     D9       1       1       0   .abs_section_d9
+     _SPIBR                                      DA       1       1       0   .abs_section_da
+     _SPISR                                      DB       1       1       0   .abs_section_db
+     _SPIDR                                      DD       1       1       0   .abs_section_dd
+     _IBAD                                       E0       1       1       0   .abs_section_e0
+     _IBFD                                       E1       1       1       0   .abs_section_e1
+     _IBCR                                       E2       1       1       0   .abs_section_e2
+     _IBSR                                       E3       1       1       0   .abs_section_e3
+     _IBDR                                       E4       1       1       0   .abs_section_e4
+     _SCI2CR1                                    EA       1       1       0   .abs_section_ea
+     _SCI2CR2                                    EB       1       1       0   .abs_section_eb
+     _SCI2SR1                                    EC       1       1       0   .abs_section_ec
+     _SCI2SR2                                    ED       1       1       0   .abs_section_ed
+     _SCI2DRH                                    EE       1       1       0   .abs_section_ee
+     _SCI2DRL                                    EF       1       1       0   .abs_section_ef
+     _DAC0_DACC0                                 F0       1       1       0   .abs_section_f0
+     _DAC0_DACDLeft                              F2       1       1       0   .abs_section_f2
+     _DAC0_DACDRight                             F3       1       1       0   .abs_section_f3
+     _DAC1_DACC0                                 F4       1       1       0   .abs_section_f4
+     _DAC1_DACDLeft                              F6       1       1       0   .abs_section_f6
+     _DAC1_DACDRight                             F7       1       1       0   .abs_section_f7
+     _FCLKDIV                                   100       1       1       0   .abs_section_100
+     _FSEC                                      101       1       1       0   .abs_section_101
+     _FCNFG                                     103       1       1       0   .abs_section_103
+     _FPROT                                     104       1       1       0   .abs_section_104
+     _FSTAT                                     105       1       1       0   .abs_section_105
+     _FCMD                                      106       1       1       0   .abs_section_106
+     _TIM1_TIOS                                 140       1       1       0   .abs_section_140
+     _TIM1_CFORC                                141       1       1       0   .abs_section_141
+     _TIM1_OC7M                                 142       1       1       0   .abs_section_142
+     _TIM1_OC7D                                 143       1       1       0   .abs_section_143
+     _TIM1_TSCR1                                146       1       1       0   .abs_section_146
+     _TIM1_TTOV                                 147       1       1       0   .abs_section_147
+     _TIM1_TCTL1                                148       1       1       0   .abs_section_148
+     _TIM1_TCTL3                                14A       1       1       0   .abs_section_14a
+     _TIM1_TIE                                  14C       1       1       0   .abs_section_14c
+     _TIM1_TSCR2                                14D       1       1       0   .abs_section_14d
+     _TIM1_TFLG1                                14E       1       1       0   .abs_section_14e
+     _TIM1_TFLG2                                14F       1       1       0   .abs_section_14f
+     _TIM1_PACTL                                160       1       1       0   .abs_section_160
+     _TIM1_PAFLG                                161       1       1       0   .abs_section_161
+     _TIM2_TIOS                                 180       1       1       0   .abs_section_180
+     _TIM2_CFORC                                181       1       1       0   .abs_section_181
+     _TIM2_OC7M                                 182       1       1       0   .abs_section_182
+     _TIM2_OC7D                                 183       1       1       0   .abs_section_183
+     _TIM2_TSCR1                                186       1       1       0   .abs_section_186
+     _TIM2_TTOV                                 187       1       1       0   .abs_section_187
+     _TIM2_TCTL1                                188       1       1       0   .abs_section_188
+     _TIM2_TCTL3                                18A       1       1       0   .abs_section_18a
+     _TIM2_TIE                                  18C       1       1       0   .abs_section_18c
+     _TIM2_TSCR2                                18D       1       1       0   .abs_section_18d
+     _TIM2_TFLG1                                18E       1       1       0   .abs_section_18e
+     _TIM2_TFLG2                                18F       1       1       0   .abs_section_18f
+     _TIM2_PACTL                                1A0       1       1       0   .abs_section_1a0
+     _TIM2_PAFLG                                1A1       1       1       0   .abs_section_1a1
+     _PWME                                      1E0       1       1       0   .abs_section_1e0
+     _PWMPOL                                    1E1       1       1       0   .abs_section_1e1
+     _PWMCLK                                    1E2       1       1       0   .abs_section_1e2
+     _PWMPRCLK                                  1E3       1       1       0   .abs_section_1e3
+     _PWMCAE                                    1E4       1       1       0   .abs_section_1e4
+     _PWMCTL                                    1E5       1       1       0   .abs_section_1e5
+     _PWMSCLA                                   1E8       1       1       0   .abs_section_1e8
+     _PWMSCLB                                   1E9       1       1       0   .abs_section_1e9
+     _PWMSDN                                    1FE       1       1       0   .abs_section_1fe
+     _PMFCFG0                                   200       1       1       0   .abs_section_200
+     _PMFCFG1                                   201       1       1       0   .abs_section_201
+     _PMFCFG2                                   202       1       1       0   .abs_section_202
+     _PMFCFG3                                   203       1       1       0   .abs_section_203
+     _PMFFCTL                                   204       1       1       0   .abs_section_204
+     _PMFFPIN                                   205       1       1       0   .abs_section_205
+     _PMFFSTA                                   206       1       1       0   .abs_section_206
+     _PMFQSMP                                   207       1       1       0   .abs_section_207
+     _PMFDMPA                                   208       1       1       0   .abs_section_208
+     _PMFDMPB                                   209       1       1       0   .abs_section_209
+     _PMFDMPC                                   20A       1       1       0   .abs_section_20a
+     _PMFOUTC                                   20C       1       1       0   .abs_section_20c
+     _PMFOUTB                                   20D       1       1       0   .abs_section_20d
+     _PMFDTMS                                   20E       1       1       0   .abs_section_20e
+     _PMFCCTL                                   20F       1       1       0   .abs_section_20f
+     _PMFENCA                                   220       1       1       0   .abs_section_220
+     _PMFFQCA                                   221       1       1       0   .abs_section_221
+     _PMFENCB                                   228       1       1       0   .abs_section_228
+     _PMFFQCB                                   229       1       1       0   .abs_section_229
+     _PMFENCC                                   230       1       1       0   .abs_section_230
+     _PMFFQCC                                   231       1       1       0   .abs_section_231
+     _PTT                                       240       1       1       0   .abs_section_240
+     _PTIT                                      241       1       1       0   .abs_section_241
+     _DDRT                                      242       1       1       0   .abs_section_242
+     _RDRT                                      243       1       1       0   .abs_section_243
+     _PERT                                      244       1       1       0   .abs_section_244
+     _PPST                                      245       1       1       0   .abs_section_245
+     _PTS                                       248       1       1       0   .abs_section_248
+     _PTIS                                      249       1       1       0   .abs_section_249
+     _DDRS                                      24A       1       1       0   .abs_section_24a
+     _RDRS                                      24B       1       1       0   .abs_section_24b
+     _PERS                                      24C       1       1       0   .abs_section_24c
+     _PPSS                                      24D       1       1       0   .abs_section_24d
+     _WOMS                                      24E       1       1       0   .abs_section_24e
+     _PTM                                       250       1       1       5   .abs_section_250
+     _PTIM                                      251       1       1       0   .abs_section_251
+     _DDRM                                      252       1       1       1   .abs_section_252
+     _RDRM                                      253       1       1       0   .abs_section_253
+     _PERM                                      254       1       1       0   .abs_section_254
+     _PPSM                                      255       1       1       0   .abs_section_255
+     _WOMM                                      256       1       1       0   .abs_section_256
+     _PTP                                       258       1       1       0   .abs_section_258
+     _PTIP                                      259       1       1       0   .abs_section_259
+     _DDRP                                      25A       1       1       0   .abs_section_25a
+     _RDRP                                      25B       1       1       0   .abs_section_25b
+     _PERP                                      25C       1       1       0   .abs_section_25c
+     _PPSP                                      25D       1       1       0   .abs_section_25d
+     _PTQ                                       260       1       1       0   .abs_section_260
+     _PTIQ                                      261       1       1       0   .abs_section_261
+     _DDRQ                                      262       1       1       0   .abs_section_262
+     _RDRQ                                      263       1       1       0   .abs_section_263
+     _PERQ                                      264       1       1       0   .abs_section_264
+     _PPSQ                                      265       1       1       0   .abs_section_265
+     _PTU                                       268       1       1       0   .abs_section_268
+     _PTIU                                      269       1       1       0   .abs_section_269
+     _DDRU                                      26A       1       1       0   .abs_section_26a
+     _RDRU                                      26B       1       1       0   .abs_section_26b
+     _PERU                                      26C       1       1       0   .abs_section_26c
+     _PPSU                                      26D       1       1       0   .abs_section_26d
+     _MODRR                                     26E       1       1       0   .abs_section_26e
+     _PORTAB                                      0       2       2       0   .abs_section_0
+     _DDRAB                                       2       2       2       0   .abs_section_2
+     _PARTID                                     1A       2       2       0   .abs_section_1a
+     _DBGTB                                      22       2       2       0   .abs_section_22
+     _DBGCC                                      26       2       2       0   .abs_section_26
+     _DBGCA                                      2B       2       2       0   .abs_section_2b
+     _DBGCB                                      2E       2       2       0   .abs_section_2e
+     _TIM0_TCNT                                  44       2       2       0   .abs_section_44
+     _TIM0_TC4                                   58       2       2       0   .abs_section_58
+     _TIM0_TC5                                   5A       2       2       0   .abs_section_5a
+     _TIM0_TC6                                   5C       2       2       0   .abs_section_5c
+     _TIM0_TC7                                   5E       2       2       0   .abs_section_5e
+     _TIM0_PACNT                                 62       2       2       0   .abs_section_62
+     _ATDCTL23                                   82       2       2       1   .abs_section_82
+     _ATDCTL45                                   84       2       2       1   .abs_section_84
+     _ATDDIEN                                    8C       2       2       0   .abs_section_8c
+     _ATDDR0                                     90       2       2       1   .abs_section_90
+     _ATDDR1                                     92       2       2       0   .abs_section_92
+     _ATDDR2                                     94       2       2       0   .abs_section_94
+     _ATDDR3                                     96       2       2       0   .abs_section_96
+     _ATDDR4                                     98       2       2       0   .abs_section_98
+     _ATDDR5                                     9A       2       2       0   .abs_section_9a
+     _ATDDR6                                     9C       2       2       0   .abs_section_9c
+     _ATDDR7                                     9E       2       2       0   .abs_section_9e
+     _ATDDR8                                     A0       2       2       0   .abs_section_a0
+     _ATDDR9                                     A2       2       2       0   .abs_section_a2
+     _ATDDR10                                    A4       2       2       0   .abs_section_a4
+     _ATDDR11                                    A6       2       2       0   .abs_section_a6
+     _ATDDR12                                    A8       2       2       0   .abs_section_a8
+     _ATDDR13                                    AA       2       2       0   .abs_section_aa
+     _ATDDR14                                    AC       2       2       0   .abs_section_ac
+     _ATDDR15                                    AE       2       2       0   .abs_section_ae
+     _SCI0BD                                     C8       2       2       0   .abs_section_c8
+     _SCI1BD                                     D0       2       2       0   .abs_section_d0
+     _SCI2BD                                     E8       2       2       0   .abs_section_e8
+     _TIM1_TCNT                                 144       2       2       0   .abs_section_144
+     _TIM1_TC4                                  158       2       2       0   .abs_section_158
+     _TIM1_TC5                                  15A       2       2       0   .abs_section_15a
+     _TIM1_TC6                                  15C       2       2       0   .abs_section_15c
+     _TIM1_TC7                                  15E       2       2       0   .abs_section_15e
+     _TIM1_PACNT                                162       2       2       0   .abs_section_162
+     _TIM2_TCNT                                 184       2       2       0   .abs_section_184
+     _TIM2_TC4                                  198       2       2       0   .abs_section_198
+     _TIM2_TC5                                  19A       2       2       0   .abs_section_19a
+     _TIM2_TC6                                  19C       2       2       0   .abs_section_19c
+     _TIM2_TC7                                  19E       2       2       0   .abs_section_19e
+     _TIM2_PACNT                                1A2       2       2       0   .abs_section_1a2
+     _PWMCNT01                                  1EC       2       2       0   .abs_section_1ec
+     _PWMCNT23                                  1EE       2       2       0   .abs_section_1ee
+     _PWMCNT45                                  1F0       2       2       0   .abs_section_1f0
+     _PWMPER01                                  1F2       2       2       0   .abs_section_1f2
+     _PWMPER23                                  1F4       2       2       0   .abs_section_1f4
+     _PWMPER45                                  1F6       2       2       0   .abs_section_1f6
+     _PWMDTY01                                  1F8       2       2       0   .abs_section_1f8
+     _PWMDTY23                                  1FA       2       2       0   .abs_section_1fa
+     _PWMDTY45                                  1FC       2       2       0   .abs_section_1fc
+     _PMFVAL0                                   210       2       2       0   .abs_section_210
+     _PMFVAL1                                   212       2       2       0   .abs_section_212
+     _PMFVAL2                                   214       2       2       0   .abs_section_214
+     _PMFVAL3                                   216       2       2       0   .abs_section_216
+     _PMFVAL4                                   218       2       2       0   .abs_section_218
+     _PMFVAL5                                   21A       2       2       0   .abs_section_21a
+     _PMFCNTA                                   222       2       2       0   .abs_section_222
+     _PMFMODA                                   224       2       2       0   .abs_section_224
+     _PMFDTMA                                   226       2       2       0   .abs_section_226
+     _PMFCNTB                                   22A       2       2       0   .abs_section_22a
+     _PMFMODB                                   22C       2       2       0   .abs_section_22c
+     _PMFDTMB                                   22E       2       2       0   .abs_section_22e
+     _PMFCNTC                                   232       2       2       0   .abs_section_232
+     _PMFMODC                                   234       2       2       0   .abs_section_234
+     _PMFDTMC                                   236       2       2       0   .abs_section_236
+     _PTAD                                      270       2       2       4   .abs_section_270
+     _PTIAD                                     272       2       2       0   .abs_section_272
+     _DDRAD                                     274       2       2       1   .abs_section_274
+     _RDRAD                                     276       2       2       0   .abs_section_276
+     _PERAD                                     278       2       2       0   .abs_section_278
+     _PPSAD                                     27A       2       2       0   .abs_section_27a
+     _PIEAD                                     27C       2       2       0   .abs_section_27c
+     _PIFAD                                     27E       2       2       0   .abs_section_27e
+MODULE:                 -- potentiometer.c.o --
+- PROCEDURES:
+     read_pot                                  C1E5      18      24       1   NON_BANKED  
+- VARIABLES:
+     pot_value                                  56A       2       2       1   .common     
+MODULE:                 -- IRQ_ISR.asm.o --
+- PROCEDURES:
+- VARIABLES:
+     IRQ_ISR                                    56C       0       0       0   IRQ_ISR.asm._SEC000000
+MODULE:                 -- circulation.asm.o --
+- PROCEDURES:
+     Circulation                               C21A      1B      27       1   circulation.asm._SEC000000
+     PulseOff                                  C235       6       6       0   circulation.asm._SEC000000
+     PrintTemperature                          C23B      B4     180       0   circulation.asm._SEC000000
+     Return                                    C2EF       6       6       0   circulation.asm._SEC000000
+- VARIABLES:
+MODULE:                 -- debounce.asm.o --
+- PROCEDURES:
+     Debounce                                  C2F5       4       4       1   debounce.asm._SEC000000
+     Loop                                      C2F9       5       5       0   debounce.asm._SEC000000
+- VARIABLES:
+MODULE:                 -- eventloop.asm.o --
+- PROCEDURES:
+     RTI_ISR                                   C2FE      16      22       0   eventloop.asm._SEC000000
+     LessThanSec                               C314      2E      46       0   eventloop.asm._SEC000000
+     FanOff                                    C342       3       3       0   eventloop.asm._SEC000000
+     FanReset                                  C345       9       9       0   eventloop.asm._SEC000000
+     DidMotor                                  C34E      8C     140       0   eventloop.asm._SEC000000
+     CycleMenu                                 C3DA      11      17       0   eventloop.asm._SEC000000
+     StartWatering                             C3EB      23      35       0   eventloop.asm._SEC000000
+     StopWatering                              C40E      1D      29       0   eventloop.asm._SEC000000
+     Sprinkle                                  C42B      15      21       0   eventloop.asm._SEC000000
+     DisplayTemperature                        C440      23      35       0   eventloop.asm._SEC000000
+     HideTemperature                           C463      1B      27       0   eventloop.asm._SEC000000
+     DisplayTime                               C47E      23      35       0   eventloop.asm._SEC000000
+     HideTime                                  C4A1      1B      27       0   eventloop.asm._SEC000000
+     SetTime                                   C4BC       7       7       0   eventloop.asm._SEC000000
+     ResetPassword                             C4C3       7       7       0   eventloop.asm._SEC000000
+     Return                                    C4CA       5       5       0   eventloop.asm._SEC000000
+- VARIABLES:
+MODULE:                 -- growlights.asm.o --
+- PROCEDURES:
+     Growlights                                C4CF      11      17       1   growlights.asm._SEC000000
+- VARIABLES:
+MODULE:                 -- menu.asm.o --
+- PROCEDURES:
+     Menu                                      C4E0       E      14       1   Code        
+     PrintTopLine                              C4EE      86     134       0   Code        
+     PrintOption1                              C574      5F      95       0   Code        
+     PrintOption2                              C5D3      5F      95       0   Code        
+     PrintOption3                              C632      5F      95       0   Code        
+     PrintOption4                              C691      5F      95       0   Code        
+     PrintOption5                              C6F0      5F      95       0   Code        
+     PrintOption6                              C74F      5D      93       0   Code        
+     PrintOption7                              C7AC      5D      93       0   Code        
+     Return                                    C809       6       6       0   Code        
+- VARIABLES:
+MODULE:                 -- password.asm.o --
+- PROCEDURES:
+     Password                                  C80F      22      34       2   Code        
+     PasswordInit                              C831     181     385       0   Code        
+     PasswordReset                             C9B2     35D     861       0   Code        
+     PasswordCheck                             CD0F     1E1     481       0   Code        
+     Return                                    CEF0       B      11       0   Code        
+- VARIABLES:
+MODULE:                 -- keypad.asm.o --
+- PROCEDURES:
+     Keypad                                    CEFB       7       7      33   Code        
+     ArrayEnd                                  CF02       7       7       0   Code        
+     InitSequence                              CF09       3       3       0   Code        
+     ReadKeypress                              CF0C      1F      31       0   Code        
+     AwaitRelease                              CF2B       9       9       0   Code        
+     InitLookup                                CF34       5       5       0   Code        
+     Lookup                                    CF39       A      10       0   Code        
+     Found                                     CF43       3       3       0   Code        
+     Return                                    CF46       6       6       0   Code        
+- VARIABLES:
+MODULE:                 -- water.asm.o --
+- PROCEDURES:
+     Water                                     CF4C      29      41       1   Variables   
+     Continue                                  CF75      13      19       0   Variables   
+     ShowWatering                              CF88      AB     171       0   Variables   
+     Return                                    D033       6       6       0   Variables   
+- VARIABLES:
+MODULE:                 -- wall.asm.o --
+- PROCEDURES:
+     Wall                                      D039     10E     270       1   clock_code  
+     PrintWall                                 D147      CC     204       0   clock_code  
+     Return                                    D213       9       9       0   clock_code  
+- VARIABLES:
+     seconds_tens                               56C       1       1       2   clock_digits
+     seconds_ones                               56D       1       1       2   clock_digits
+     minutes_tens                               56E       1       1       0   clock_digits
+     minutes_ones                               56F       1       1       0   clock_digits
+     hours_tens                                 570       1       1       0   clock_digits
+     hours_ones                                 571       1       1       0   clock_digits
+
+*********************************************************************************************
+MODULE STATISTIC
+  Name                                      Data   Code  Const
+---------------------------------------------------------------------------------------------
+  main.asm.o                                 104    242     29
+  lcddisp.c.o                                  2    243      0
+  mc9s12e128.c.o                             352      0      0
+  potentiometer.c.o                            2     24      0
+  IRQ_ISR.asm.o                                0      0      0
+  circulation.asm.o                            0    219      0
+  debounce.asm.o                               0      9      0
+  eventloop.asm.o                              0    465      0
+  growlights.asm.o                             0     17      0
+  menu.asm.o                                   0    815      0
+  password.asm.o                               0   1772      0
+  keypad.asm.o                                 0     81      0
+  water.asm.o                                  0    237      0
+  wall.asm.o                                   6    483      0
+  other                                      256      6      0
+
+*********************************************************************************************
+SECTION USE IN OBJECT-ALLOCATION SECTION
+---------------------------------------------------------------------------------------------
+SECTION: ".text"
+  CRGFLG PORT_T DDR_T PORT_S DDR_S PORT_P DDR_P PORT_U PDR_U PSR_U 
+SECTION: ".bss"
+  data 
+SECTION: ".init"
+  _Startup Entry Init Main 
+SECTION: "NON_BANKED"
+  delay_ms init_LCD display_string Delay epulse sendCommand read_pot 
+SECTION: "my_constant"
+  KVS SEQUENCE SPRINKLER_ARR 
+SECTION: "my_variable"
+  disp password entered_password new_password pw_prompt_shown pw_check 
+  pw_correct pw_set pw_incorrect pw_required pressed_key pressed_num 
+  await_key_release await_key_press menu_active toast_timer menu_option_num 
+  menu_timer display_timeout is_watering watering_timer sprinkler_event 
+  sprinkler_timer sprinkler_arr_i show_temperature fan_speed circulation_count 
+  dc_on display_time current_year current_month current_day current_hour 
+  current_minute current_second wall_timer clock_event ms_counter second_passed 
+  setting_wall change_time pw_reset word_out byte_out 
+SECTION: ".common"
+  pot_value 
+SECTION: ".abs_section_8"
+  _PORTE 
+SECTION: ".abs_section_9"
+  _DDRE 
+SECTION: ".abs_section_a"
+  _PEAR 
+SECTION: ".abs_section_b"
+  _MODE 
+SECTION: ".abs_section_c"
+  _PUCR 
+SECTION: ".abs_section_d"
+  _RDRIV 
+SECTION: ".abs_section_e"
+  _EBICTL 
+SECTION: ".abs_section_10"
+  _INITRM 
+SECTION: ".abs_section_11"
+  _INITRG 
+SECTION: ".abs_section_13"
+  _MISC 
+SECTION: ".abs_section_15"
+  _ITCR 
+SECTION: ".abs_section_16"
+  _ITEST 
+SECTION: ".abs_section_19"
+  _VREGCTRL 
+SECTION: ".abs_section_1c"
+  _MEMSIZ0 
+SECTION: ".abs_section_1d"
+  _MEMSIZ1 
+SECTION: ".abs_section_1e"
+  _INTCR 
+SECTION: ".abs_section_1f"
+  _HPRIO 
+SECTION: ".abs_section_20"
+  _DBGC1 
+SECTION: ".abs_section_21"
+  _DBGSC 
+SECTION: ".abs_section_24"
+  _DBGCNT 
+SECTION: ".abs_section_25"
+  _DBGCCX 
+SECTION: ".abs_section_28"
+  _DBGC2 
+SECTION: ".abs_section_29"
+  _DBGC3 
+SECTION: ".abs_section_2a"
+  _DBGCAX 
+SECTION: ".abs_section_2d"
+  _DBGCBX 
+SECTION: ".abs_section_30"
+  _PPAGE 
+SECTION: ".abs_section_32"
+  _PORTK 
+SECTION: ".abs_section_33"
+  _DDRK 
+SECTION: ".abs_section_34"
+  _SYNR 
+SECTION: ".abs_section_35"
+  _REFDV 
+SECTION: ".abs_section_37"
+  _CRGFLG 
+SECTION: ".abs_section_38"
+  _CRGINT 
+SECTION: ".abs_section_39"
+  _CLKSEL 
+SECTION: ".abs_section_3a"
+  _PLLCTL 
+SECTION: ".abs_section_3b"
+  _RTICTL 
+SECTION: ".abs_section_3c"
+  _COPCTL 
+SECTION: ".abs_section_3f"
+  _ARMCOP 
+SECTION: ".abs_section_40"
+  _TIM0_TIOS 
+SECTION: ".abs_section_41"
+  _TIM0_CFORC 
+SECTION: ".abs_section_42"
+  _TIM0_OC7M 
+SECTION: ".abs_section_43"
+  _TIM0_OC7D 
+SECTION: ".abs_section_46"
+  _TIM0_TSCR1 
+SECTION: ".abs_section_47"
+  _TIM0_TTOV 
+SECTION: ".abs_section_48"
+  _TIM0_TCTL1 
+SECTION: ".abs_section_4a"
+  _TIM0_TCTL3 
+SECTION: ".abs_section_4c"
+  _TIM0_TIE 
+SECTION: ".abs_section_4d"
+  _TIM0_TSCR2 
+SECTION: ".abs_section_4e"
+  _TIM0_TFLG1 
+SECTION: ".abs_section_4f"
+  _TIM0_TFLG2 
+SECTION: ".abs_section_60"
+  _TIM0_PACTL 
+SECTION: ".abs_section_61"
+  _TIM0_PAFLG 
+SECTION: ".abs_section_86"
+  _ATDSTAT0 
+SECTION: ".abs_section_89"
+  _ATDTEST1 
+SECTION: ".abs_section_8a"
+  _ATDSTAT2 
+SECTION: ".abs_section_8b"
+  _ATDSTAT1 
+SECTION: ".abs_section_8e"
+  _PORTAD0 
+SECTION: ".abs_section_8f"
+  _PORTAD1 
+SECTION: ".abs_section_ca"
+  _SCI0CR1 
+SECTION: ".abs_section_cb"
+  _SCI0CR2 
+SECTION: ".abs_section_cc"
+  _SCI0SR1 
+SECTION: ".abs_section_cd"
+  _SCI0SR2 
+SECTION: ".abs_section_ce"
+  _SCI0DRH 
+SECTION: ".abs_section_cf"
+  _SCI0DRL 
+SECTION: ".abs_section_d2"
+  _SCI1CR1 
+SECTION: ".abs_section_d3"
+  _SCI1CR2 
+SECTION: ".abs_section_d4"
+  _SCI1SR1 
+SECTION: ".abs_section_d5"
+  _SCI1SR2 
+SECTION: ".abs_section_d6"
+  _SCI1DRH 
+SECTION: ".abs_section_d7"
+  _SCI1DRL 
+SECTION: ".abs_section_d8"
+  _SPICR1 
+SECTION: ".abs_section_d9"
+  _SPICR2 
+SECTION: ".abs_section_da"
+  _SPIBR 
+SECTION: ".abs_section_db"
+  _SPISR 
+SECTION: ".abs_section_dd"
+  _SPIDR 
+SECTION: ".abs_section_e0"
+  _IBAD 
+SECTION: ".abs_section_e1"
+  _IBFD 
+SECTION: ".abs_section_e2"
+  _IBCR 
+SECTION: ".abs_section_e3"
+  _IBSR 
+SECTION: ".abs_section_e4"
+  _IBDR 
+SECTION: ".abs_section_ea"
+  _SCI2CR1 
+SECTION: ".abs_section_eb"
+  _SCI2CR2 
+SECTION: ".abs_section_ec"
+  _SCI2SR1 
+SECTION: ".abs_section_ed"
+  _SCI2SR2 
+SECTION: ".abs_section_ee"
+  _SCI2DRH 
+SECTION: ".abs_section_ef"
+  _SCI2DRL 
+SECTION: ".abs_section_f0"
+  _DAC0_DACC0 
+SECTION: ".abs_section_f2"
+  _DAC0_DACDLeft 
+SECTION: ".abs_section_f3"
+  _DAC0_DACDRight 
+SECTION: ".abs_section_f4"
+  _DAC1_DACC0 
+SECTION: ".abs_section_f6"
+  _DAC1_DACDLeft 
+SECTION: ".abs_section_f7"
+  _DAC1_DACDRight 
+SECTION: ".abs_section_100"
+  _FCLKDIV 
+SECTION: ".abs_section_101"
+  _FSEC 
+SECTION: ".abs_section_103"
+  _FCNFG 
+SECTION: ".abs_section_104"
+  _FPROT 
+SECTION: ".abs_section_105"
+  _FSTAT 
+SECTION: ".abs_section_106"
+  _FCMD 
+SECTION: ".abs_section_140"
+  _TIM1_TIOS 
+SECTION: ".abs_section_141"
+  _TIM1_CFORC 
+SECTION: ".abs_section_142"
+  _TIM1_OC7M 
+SECTION: ".abs_section_143"
+  _TIM1_OC7D 
+SECTION: ".abs_section_146"
+  _TIM1_TSCR1 
+SECTION: ".abs_section_147"
+  _TIM1_TTOV 
+SECTION: ".abs_section_148"
+  _TIM1_TCTL1 
+SECTION: ".abs_section_14a"
+  _TIM1_TCTL3 
+SECTION: ".abs_section_14c"
+  _TIM1_TIE 
+SECTION: ".abs_section_14d"
+  _TIM1_TSCR2 
+SECTION: ".abs_section_14e"
+  _TIM1_TFLG1 
+SECTION: ".abs_section_14f"
+  _TIM1_TFLG2 
+SECTION: ".abs_section_160"
+  _TIM1_PACTL 
+SECTION: ".abs_section_161"
+  _TIM1_PAFLG 
+SECTION: ".abs_section_180"
+  _TIM2_TIOS 
+SECTION: ".abs_section_181"
+  _TIM2_CFORC 
+SECTION: ".abs_section_182"
+  _TIM2_OC7M 
+SECTION: ".abs_section_183"
+  _TIM2_OC7D 
+SECTION: ".abs_section_186"
+  _TIM2_TSCR1 
+SECTION: ".abs_section_187"
+  _TIM2_TTOV 
+SECTION: ".abs_section_188"
+  _TIM2_TCTL1 
+SECTION: ".abs_section_18a"
+  _TIM2_TCTL3 
+SECTION: ".abs_section_18c"
+  _TIM2_TIE 
+SECTION: ".abs_section_18d"
+  _TIM2_TSCR2 
+SECTION: ".abs_section_18e"
+  _TIM2_TFLG1 
+SECTION: ".abs_section_18f"
+  _TIM2_TFLG2 
+SECTION: ".abs_section_1a0"
+  _TIM2_PACTL 
+SECTION: ".abs_section_1a1"
+  _TIM2_PAFLG 
+SECTION: ".abs_section_1e0"
+  _PWME 
+SECTION: ".abs_section_1e1"
+  _PWMPOL 
+SECTION: ".abs_section_1e2"
+  _PWMCLK 
+SECTION: ".abs_section_1e3"
+  _PWMPRCLK 
+SECTION: ".abs_section_1e4"
+  _PWMCAE 
+SECTION: ".abs_section_1e5"
+  _PWMCTL 
+SECTION: ".abs_section_1e8"
+  _PWMSCLA 
+SECTION: ".abs_section_1e9"
+  _PWMSCLB 
+SECTION: ".abs_section_1fe"
+  _PWMSDN 
+SECTION: ".abs_section_200"
+  _PMFCFG0 
+SECTION: ".abs_section_201"
+  _PMFCFG1 
+SECTION: ".abs_section_202"
+  _PMFCFG2 
+SECTION: ".abs_section_203"
+  _PMFCFG3 
+SECTION: ".abs_section_204"
+  _PMFFCTL 
+SECTION: ".abs_section_205"
+  _PMFFPIN 
+SECTION: ".abs_section_206"
+  _PMFFSTA 
+SECTION: ".abs_section_207"
+  _PMFQSMP 
+SECTION: ".abs_section_208"
+  _PMFDMPA 
+SECTION: ".abs_section_209"
+  _PMFDMPB 
+SECTION: ".abs_section_20a"
+  _PMFDMPC 
+SECTION: ".abs_section_20c"
+  _PMFOUTC 
+SECTION: ".abs_section_20d"
+  _PMFOUTB 
+SECTION: ".abs_section_20e"
+  _PMFDTMS 
+SECTION: ".abs_section_20f"
+  _PMFCCTL 
+SECTION: ".abs_section_220"
+  _PMFENCA 
+SECTION: ".abs_section_221"
+  _PMFFQCA 
+SECTION: ".abs_section_228"
+  _PMFENCB 
+SECTION: ".abs_section_229"
+  _PMFFQCB 
+SECTION: ".abs_section_230"
+  _PMFENCC 
+SECTION: ".abs_section_231"
+  _PMFFQCC 
+SECTION: ".abs_section_240"
+  _PTT 
+SECTION: ".abs_section_241"
+  _PTIT 
+SECTION: ".abs_section_242"
+  _DDRT 
+SECTION: ".abs_section_243"
+  _RDRT 
+SECTION: ".abs_section_244"
+  _PERT 
+SECTION: ".abs_section_245"
+  _PPST 
+SECTION: ".abs_section_248"
+  _PTS 
+SECTION: ".abs_section_249"
+  _PTIS 
+SECTION: ".abs_section_24a"
+  _DDRS 
+SECTION: ".abs_section_24b"
+  _RDRS 
+SECTION: ".abs_section_24c"
+  _PERS 
+SECTION: ".abs_section_24d"
+  _PPSS 
+SECTION: ".abs_section_24e"
+  _WOMS 
+SECTION: ".abs_section_250"
+  _PTM 
+SECTION: ".abs_section_251"
+  _PTIM 
+SECTION: ".abs_section_252"
+  _DDRM 
+SECTION: ".abs_section_253"
+  _RDRM 
+SECTION: ".abs_section_254"
+  _PERM 
+SECTION: ".abs_section_255"
+  _PPSM 
+SECTION: ".abs_section_256"
+  _WOMM 
+SECTION: ".abs_section_258"
+  _PTP 
+SECTION: ".abs_section_259"
+  _PTIP 
+SECTION: ".abs_section_25a"
+  _DDRP 
+SECTION: ".abs_section_25b"
+  _RDRP 
+SECTION: ".abs_section_25c"
+  _PERP 
+SECTION: ".abs_section_25d"
+  _PPSP 
+SECTION: ".abs_section_260"
+  _PTQ 
+SECTION: ".abs_section_261"
+  _PTIQ 
+SECTION: ".abs_section_262"
+  _DDRQ 
+SECTION: ".abs_section_263"
+  _RDRQ 
+SECTION: ".abs_section_264"
+  _PERQ 
+SECTION: ".abs_section_265"
+  _PPSQ 
+SECTION: ".abs_section_268"
+  _PTU 
+SECTION: ".abs_section_269"
+  _PTIU 
+SECTION: ".abs_section_26a"
+  _DDRU 
+SECTION: ".abs_section_26b"
+  _RDRU 
+SECTION: ".abs_section_26c"
+  _PERU 
+SECTION: ".abs_section_26d"
+  _PPSU 
+SECTION: ".abs_section_26e"
+  _MODRR 
+SECTION: ".abs_section_0"
+  _PORTAB 
+SECTION: ".abs_section_2"
+  _DDRAB 
+SECTION: ".abs_section_1a"
+  _PARTID 
+SECTION: ".abs_section_22"
+  _DBGTB 
+SECTION: ".abs_section_26"
+  _DBGCC 
+SECTION: ".abs_section_2b"
+  _DBGCA 
+SECTION: ".abs_section_2e"
+  _DBGCB 
+SECTION: ".abs_section_44"
+  _TIM0_TCNT 
+SECTION: ".abs_section_58"
+  _TIM0_TC4 
+SECTION: ".abs_section_5a"
+  _TIM0_TC5 
+SECTION: ".abs_section_5c"
+  _TIM0_TC6 
+SECTION: ".abs_section_5e"
+  _TIM0_TC7 
+SECTION: ".abs_section_62"
+  _TIM0_PACNT 
+SECTION: ".abs_section_82"
+  _ATDCTL23 
+SECTION: ".abs_section_84"
+  _ATDCTL45 
+SECTION: ".abs_section_8c"
+  _ATDDIEN 
+SECTION: ".abs_section_90"
+  _ATDDR0 
+SECTION: ".abs_section_92"
+  _ATDDR1 
+SECTION: ".abs_section_94"
+  _ATDDR2 
+SECTION: ".abs_section_96"
+  _ATDDR3 
+SECTION: ".abs_section_98"
+  _ATDDR4 
+SECTION: ".abs_section_9a"
+  _ATDDR5 
+SECTION: ".abs_section_9c"
+  _ATDDR6 
+SECTION: ".abs_section_9e"
+  _ATDDR7 
+SECTION: ".abs_section_a0"
+  _ATDDR8 
+SECTION: ".abs_section_a2"
+  _ATDDR9 
+SECTION: ".abs_section_a4"
+  _ATDDR10 
+SECTION: ".abs_section_a6"
+  _ATDDR11 
+SECTION: ".abs_section_a8"
+  _ATDDR12 
+SECTION: ".abs_section_aa"
+  _ATDDR13 
+SECTION: ".abs_section_ac"
+  _ATDDR14 
+SECTION: ".abs_section_ae"
+  _ATDDR15 
+SECTION: ".abs_section_c8"
+  _SCI0BD 
+SECTION: ".abs_section_d0"
+  _SCI1BD 
+SECTION: ".abs_section_e8"
+  _SCI2BD 
+SECTION: ".abs_section_144"
+  _TIM1_TCNT 
+SECTION: ".abs_section_158"
+  _TIM1_TC4 
+SECTION: ".abs_section_15a"
+  _TIM1_TC5 
+SECTION: ".abs_section_15c"
+  _TIM1_TC6 
+SECTION: ".abs_section_15e"
+  _TIM1_TC7 
+SECTION: ".abs_section_162"
+  _TIM1_PACNT 
+SECTION: ".abs_section_184"
+  _TIM2_TCNT 
+SECTION: ".abs_section_198"
+  _TIM2_TC4 
+SECTION: ".abs_section_19a"
+  _TIM2_TC5 
+SECTION: ".abs_section_19c"
+  _TIM2_TC6 
+SECTION: ".abs_section_19e"
+  _TIM2_TC7 
+SECTION: ".abs_section_1a2"
+  _TIM2_PACNT 
+SECTION: ".abs_section_1ec"
+  _PWMCNT01 
+SECTION: ".abs_section_1ee"
+  _PWMCNT23 
+SECTION: ".abs_section_1f0"
+  _PWMCNT45 
+SECTION: ".abs_section_1f2"
+  _PWMPER01 
+SECTION: ".abs_section_1f4"
+  _PWMPER23 
+SECTION: ".abs_section_1f6"
+  _PWMPER45 
+SECTION: ".abs_section_1f8"
+  _PWMDTY01 
+SECTION: ".abs_section_1fa"
+  _PWMDTY23 
+SECTION: ".abs_section_1fc"
+  _PWMDTY45 
+SECTION: ".abs_section_210"
+  _PMFVAL0 
+SECTION: ".abs_section_212"
+  _PMFVAL1 
+SECTION: ".abs_section_214"
+  _PMFVAL2 
+SECTION: ".abs_section_216"
+  _PMFVAL3 
+SECTION: ".abs_section_218"
+  _PMFVAL4 
+SECTION: ".abs_section_21a"
+  _PMFVAL5 
+SECTION: ".abs_section_222"
+  _PMFCNTA 
+SECTION: ".abs_section_224"
+  _PMFMODA 
+SECTION: ".abs_section_226"
+  _PMFDTMA 
+SECTION: ".abs_section_22a"
+  _PMFCNTB 
+SECTION: ".abs_section_22c"
+  _PMFMODB 
+SECTION: ".abs_section_22e"
+  _PMFDTMB 
+SECTION: ".abs_section_232"
+  _PMFCNTC 
+SECTION: ".abs_section_234"
+  _PMFMODC 
+SECTION: ".abs_section_236"
+  _PMFDTMC 
+SECTION: ".abs_section_270"
+  _PTAD 
+SECTION: ".abs_section_272"
+  _PTIAD 
+SECTION: ".abs_section_274"
+  _DDRAD 
+SECTION: ".abs_section_276"
+  _RDRAD 
+SECTION: ".abs_section_278"
+  _PERAD 
+SECTION: ".abs_section_27a"
+  _PPSAD 
+SECTION: ".abs_section_27c"
+  _PIEAD 
+SECTION: ".abs_section_27e"
+  _PIFAD 
+SECTION: "IRQ_ISR.asm._SEC000000"
+  IRQ_ISR 
+SECTION: "circulation.asm._SEC000000"
+  Circulation PulseOff PrintTemperature Return 
+SECTION: "debounce.asm._SEC000000"
+  Debounce Loop 
+SECTION: "eventloop.asm._SEC000000"
+  RTI_ISR LessThanSec FanOff FanReset DidMotor CycleMenu StartWatering 
+  StopWatering Sprinkle DisplayTemperature HideTemperature DisplayTime HideTime 
+  SetTime ResetPassword Return 
+SECTION: "growlights.asm._SEC000000"
+  Growlights 
+SECTION: "Code"
+  Menu PrintTopLine PrintOption1 PrintOption2 PrintOption3 PrintOption4 
+  PrintOption5 PrintOption6 PrintOption7 Return Password PasswordInit 
+  PasswordReset PasswordCheck Return Keypad ArrayEnd InitSequence ReadKeypress 
+  AwaitRelease InitLookup Lookup Found Return 
+SECTION: "Variables"
+  Water Continue ShowWatering Return 
+SECTION: "clock_code"
+  Wall PrintWall Return 
+SECTION: "clock_digits"
+  seconds_tens seconds_ones minutes_tens minutes_ones hours_tens hours_ones 
+
+*********************************************************************************************
+OBJECT LIST SORTED BY ADDRESS
+     Name                                      Addr   hSize   dSize     Ref    Section   RLIB
+---------------------------------------------------------------------------------------------
+     _PORTAB                                      0       2       2       0   .abs_section_0
+     _DDRAB                                       2       2       2       0   .abs_section_2
+     _PORTE                                       8       1       1       0   .abs_section_8
+     _DDRE                                        9       1       1       0   .abs_section_9
+     _PEAR                                        A       1       1       0   .abs_section_a
+     _MODE                                        B       1       1       0   .abs_section_b
+     _PUCR                                        C       1       1       0   .abs_section_c
+     _RDRIV                                       D       1       1       0   .abs_section_d
+     _EBICTL                                      E       1       1       0   .abs_section_e
+     _INITRM                                     10       1       1       0   .abs_section_10
+     _INITRG                                     11       1       1       0   .abs_section_11
+     _MISC                                       13       1       1       0   .abs_section_13
+     _ITCR                                       15       1       1       0   .abs_section_15
+     _ITEST                                      16       1       1       0   .abs_section_16
+     _VREGCTRL                                   19       1       1       0   .abs_section_19
+     _PARTID                                     1A       2       2       0   .abs_section_1a
+     _MEMSIZ0                                    1C       1       1       0   .abs_section_1c
+     _MEMSIZ1                                    1D       1       1       0   .abs_section_1d
+     _INTCR                                      1E       1       1       0   .abs_section_1e
+     _HPRIO                                      1F       1       1       0   .abs_section_1f
+     _DBGC1                                      20       1       1       0   .abs_section_20
+     _DBGSC                                      21       1       1       0   .abs_section_21
+     _DBGTB                                      22       2       2       0   .abs_section_22
+     _DBGCNT                                     24       1       1       0   .abs_section_24
+     _DBGCCX                                     25       1       1       0   .abs_section_25
+     _DBGCC                                      26       2       2       0   .abs_section_26
+     _DBGC2                                      28       1       1       0   .abs_section_28
+     _DBGC3                                      29       1       1       0   .abs_section_29
+     _DBGCAX                                     2A       1       1       0   .abs_section_2a
+     _DBGCA                                      2B       2       2       0   .abs_section_2b
+     _DBGCBX                                     2D       1       1       0   .abs_section_2d
+     _DBGCB                                      2E       2       2       0   .abs_section_2e
+     _PPAGE                                      30       1       1       0   .abs_section_30
+     _PORTK                                      32       1       1       0   .abs_section_32
+     _DDRK                                       33       1       1       0   .abs_section_33
+     _SYNR                                       34       1       1       0   .abs_section_34
+     _REFDV                                      35       1       1       0   .abs_section_35
+     _CRGFLG                                     37       1       1       0   .abs_section_37
+     CRGFLG                                      37       0       0       1   .text       
+     _CRGINT                                     38       1       1       0   .abs_section_38
+     _CLKSEL                                     39       1       1       0   .abs_section_39
+     _PLLCTL                                     3A       1       1       0   .abs_section_3a
+     _RTICTL                                     3B       1       1       0   .abs_section_3b
+     _COPCTL                                     3C       1       1       0   .abs_section_3c
+     _ARMCOP                                     3F       1       1       0   .abs_section_3f
+     _TIM0_TIOS                                  40       1       1       0   .abs_section_40
+     _TIM0_CFORC                                 41       1       1       0   .abs_section_41
+     _TIM0_OC7M                                  42       1       1       0   .abs_section_42
+     _TIM0_OC7D                                  43       1       1       0   .abs_section_43
+     _TIM0_TCNT                                  44       2       2       0   .abs_section_44
+     _TIM0_TSCR1                                 46       1       1       0   .abs_section_46
+     _TIM0_TTOV                                  47       1       1       0   .abs_section_47
+     _TIM0_TCTL1                                 48       1       1       0   .abs_section_48
+     _TIM0_TCTL3                                 4A       1       1       0   .abs_section_4a
+     _TIM0_TIE                                   4C       1       1       0   .abs_section_4c
+     _TIM0_TSCR2                                 4D       1       1       0   .abs_section_4d
+     _TIM0_TFLG1                                 4E       1       1       0   .abs_section_4e
+     _TIM0_TFLG2                                 4F       1       1       0   .abs_section_4f
+     _TIM0_TC4                                   58       2       2       0   .abs_section_58
+     _TIM0_TC5                                   5A       2       2       0   .abs_section_5a
+     _TIM0_TC6                                   5C       2       2       0   .abs_section_5c
+     _TIM0_TC7                                   5E       2       2       0   .abs_section_5e
+     _TIM0_PACTL                                 60       1       1       0   .abs_section_60
+     _TIM0_PAFLG                                 61       1       1       0   .abs_section_61
+     _TIM0_PACNT                                 62       2       2       0   .abs_section_62
+     _ATDCTL23                                   82       2       2       1   .abs_section_82
+     _ATDCTL45                                   84       2       2       1   .abs_section_84
+     _ATDSTAT0                                   86       1       1       1   .abs_section_86
+     _ATDTEST1                                   89       1       1       0   .abs_section_89
+     _ATDSTAT2                                   8A       1       1       0   .abs_section_8a
+     _ATDSTAT1                                   8B       1       1       0   .abs_section_8b
+     _ATDDIEN                                    8C       2       2       0   .abs_section_8c
+     _PORTAD0                                    8E       1       1       0   .abs_section_8e
+     _PORTAD1                                    8F       1       1       0   .abs_section_8f
+     _ATDDR0                                     90       2       2       1   .abs_section_90
+     _ATDDR1                                     92       2       2       0   .abs_section_92
+     _ATDDR2                                     94       2       2       0   .abs_section_94
+     _ATDDR3                                     96       2       2       0   .abs_section_96
+     _ATDDR4                                     98       2       2       0   .abs_section_98
+     _ATDDR5                                     9A       2       2       0   .abs_section_9a
+     _ATDDR6                                     9C       2       2       0   .abs_section_9c
+     _ATDDR7                                     9E       2       2       0   .abs_section_9e
+     _ATDDR8                                     A0       2       2       0   .abs_section_a0
+     _ATDDR9                                     A2       2       2       0   .abs_section_a2
+     _ATDDR10                                    A4       2       2       0   .abs_section_a4
+     _ATDDR11                                    A6       2       2       0   .abs_section_a6
+     _ATDDR12                                    A8       2       2       0   .abs_section_a8
+     _ATDDR13                                    AA       2       2       0   .abs_section_aa
+     _ATDDR14                                    AC       2       2       0   .abs_section_ac
+     _ATDDR15                                    AE       2       2       0   .abs_section_ae
+     _SCI0BD                                     C8       2       2       0   .abs_section_c8
+     _SCI0CR1                                    CA       1       1       0   .abs_section_ca
+     _SCI0CR2                                    CB       1       1       0   .abs_section_cb
+     _SCI0SR1                                    CC       1       1       0   .abs_section_cc
+     _SCI0SR2                                    CD       1       1       0   .abs_section_cd
+     _SCI0DRH                                    CE       1       1       0   .abs_section_ce
+     _SCI0DRL                                    CF       1       1       0   .abs_section_cf
+     _SCI1BD                                     D0       2       2       0   .abs_section_d0
+     _SCI1CR1                                    D2       1       1       0   .abs_section_d2
+     _SCI1CR2                                    D3       1       1       0   .abs_section_d3
+     _SCI1SR1                                    D4       1       1       0   .abs_section_d4
+     _SCI1SR2                                    D5       1       1       0   .abs_section_d5
+     _SCI1DRH                                    D6       1       1       0   .abs_section_d6
+     _SCI1DRL                                    D7       1       1       0   .abs_section_d7
+     _SPICR1                                     D8       1       1       0   .abs_section_d8
+     _SPICR2                                     D9       1       1       0   .abs_section_d9
+     _SPIBR                                      DA       1       1       0   .abs_section_da
+     _SPISR                                      DB       1       1       0   .abs_section_db
+     _SPIDR                                      DD       1       1       0   .abs_section_dd
+     _IBAD                                       E0       1       1       0   .abs_section_e0
+     _IBFD                                       E1       1       1       0   .abs_section_e1
+     _IBCR                                       E2       1       1       0   .abs_section_e2
+     _IBSR                                       E3       1       1       0   .abs_section_e3
+     _IBDR                                       E4       1       1       0   .abs_section_e4
+     _SCI2BD                                     E8       2       2       0   .abs_section_e8
+     _SCI2CR1                                    EA       1       1       0   .abs_section_ea
+     _SCI2CR2                                    EB       1       1       0   .abs_section_eb
+     _SCI2SR1                                    EC       1       1       0   .abs_section_ec
+     _SCI2SR2                                    ED       1       1       0   .abs_section_ed
+     _SCI2DRH                                    EE       1       1       0   .abs_section_ee
+     _SCI2DRL                                    EF       1       1       0   .abs_section_ef
+     _DAC0_DACC0                                 F0       1       1       0   .abs_section_f0
+     _DAC0_DACDLeft                              F2       1       1       0   .abs_section_f2
+     _DAC0_DACDRight                             F3       1       1       0   .abs_section_f3
+     _DAC1_DACC0                                 F4       1       1       0   .abs_section_f4
+     _DAC1_DACDLeft                              F6       1       1       0   .abs_section_f6
+     _DAC1_DACDRight                             F7       1       1       0   .abs_section_f7
+     _FCLKDIV                                   100       1       1       0   .abs_section_100
+     _FSEC                                      101       1       1       0   .abs_section_101
+     _FCNFG                                     103       1       1       0   .abs_section_103
+     _FPROT                                     104       1       1       0   .abs_section_104
+     _FSTAT                                     105       1       1       0   .abs_section_105
+     _FCMD                                      106       1       1       0   .abs_section_106
+     _TIM1_TIOS                                 140       1       1       0   .abs_section_140
+     _TIM1_CFORC                                141       1       1       0   .abs_section_141
+     _TIM1_OC7M                                 142       1       1       0   .abs_section_142
+     _TIM1_OC7D                                 143       1       1       0   .abs_section_143
+     _TIM1_TCNT                                 144       2       2       0   .abs_section_144
+     _TIM1_TSCR1                                146       1       1       0   .abs_section_146
+     _TIM1_TTOV                                 147       1       1       0   .abs_section_147
+     _TIM1_TCTL1                                148       1       1       0   .abs_section_148
+     _TIM1_TCTL3                                14A       1       1       0   .abs_section_14a
+     _TIM1_TIE                                  14C       1       1       0   .abs_section_14c
+     _TIM1_TSCR2                                14D       1       1       0   .abs_section_14d
+     _TIM1_TFLG1                                14E       1       1       0   .abs_section_14e
+     _TIM1_TFLG2                                14F       1       1       0   .abs_section_14f
+     _TIM1_TC4                                  158       2       2       0   .abs_section_158
+     _TIM1_TC5                                  15A       2       2       0   .abs_section_15a
+     _TIM1_TC6                                  15C       2       2       0   .abs_section_15c
+     _TIM1_TC7                                  15E       2       2       0   .abs_section_15e
+     _TIM1_PACTL                                160       1       1       0   .abs_section_160
+     _TIM1_PAFLG                                161       1       1       0   .abs_section_161
+     _TIM1_PACNT                                162       2       2       0   .abs_section_162
+     _TIM2_TIOS                                 180       1       1       0   .abs_section_180
+     _TIM2_CFORC                                181       1       1       0   .abs_section_181
+     _TIM2_OC7M                                 182       1       1       0   .abs_section_182
+     _TIM2_OC7D                                 183       1       1       0   .abs_section_183
+     _TIM2_TCNT                                 184       2       2       0   .abs_section_184
+     _TIM2_TSCR1                                186       1       1       0   .abs_section_186
+     _TIM2_TTOV                                 187       1       1       0   .abs_section_187
+     _TIM2_TCTL1                                188       1       1       0   .abs_section_188
+     _TIM2_TCTL3                                18A       1       1       0   .abs_section_18a
+     _TIM2_TIE                                  18C       1       1       0   .abs_section_18c
+     _TIM2_TSCR2                                18D       1       1       0   .abs_section_18d
+     _TIM2_TFLG1                                18E       1       1       0   .abs_section_18e
+     _TIM2_TFLG2                                18F       1       1       0   .abs_section_18f
+     _TIM2_TC4                                  198       2       2       0   .abs_section_198
+     _TIM2_TC5                                  19A       2       2       0   .abs_section_19a
+     _TIM2_TC6                                  19C       2       2       0   .abs_section_19c
+     _TIM2_TC7                                  19E       2       2       0   .abs_section_19e
+     _TIM2_PACTL                                1A0       1       1       0   .abs_section_1a0
+     _TIM2_PAFLG                                1A1       1       1       0   .abs_section_1a1
+     _TIM2_PACNT                                1A2       2       2       0   .abs_section_1a2
+     _PWME                                      1E0       1       1       0   .abs_section_1e0
+     _PWMPOL                                    1E1       1       1       0   .abs_section_1e1
+     _PWMCLK                                    1E2       1       1       0   .abs_section_1e2
+     _PWMPRCLK                                  1E3       1       1       0   .abs_section_1e3
+     _PWMCAE                                    1E4       1       1       0   .abs_section_1e4
+     _PWMCTL                                    1E5       1       1       0   .abs_section_1e5
+     _PWMSCLA                                   1E8       1       1       0   .abs_section_1e8
+     _PWMSCLB                                   1E9       1       1       0   .abs_section_1e9
+     _PWMCNT01                                  1EC       2       2       0   .abs_section_1ec
+     _PWMCNT23                                  1EE       2       2       0   .abs_section_1ee
+     _PWMCNT45                                  1F0       2       2       0   .abs_section_1f0
+     _PWMPER01                                  1F2       2       2       0   .abs_section_1f2
+     _PWMPER23                                  1F4       2       2       0   .abs_section_1f4
+     _PWMPER45                                  1F6       2       2       0   .abs_section_1f6
+     _PWMDTY01                                  1F8       2       2       0   .abs_section_1f8
+     _PWMDTY23                                  1FA       2       2       0   .abs_section_1fa
+     _PWMDTY45                                  1FC       2       2       0   .abs_section_1fc
+     _PWMSDN                                    1FE       1       1       0   .abs_section_1fe
+     _PMFCFG0                                   200       1       1       0   .abs_section_200
+     _PMFCFG1                                   201       1       1       0   .abs_section_201
+     _PMFCFG2                                   202       1       1       0   .abs_section_202
+     _PMFCFG3                                   203       1       1       0   .abs_section_203
+     _PMFFCTL                                   204       1       1       0   .abs_section_204
+     _PMFFPIN                                   205       1       1       0   .abs_section_205
+     _PMFFSTA                                   206       1       1       0   .abs_section_206
+     _PMFQSMP                                   207       1       1       0   .abs_section_207
+     _PMFDMPA                                   208       1       1       0   .abs_section_208
+     _PMFDMPB                                   209       1       1       0   .abs_section_209
+     _PMFDMPC                                   20A       1       1       0   .abs_section_20a
+     _PMFOUTC                                   20C       1       1       0   .abs_section_20c
+     _PMFOUTB                                   20D       1       1       0   .abs_section_20d
+     _PMFDTMS                                   20E       1       1       0   .abs_section_20e
+     _PMFCCTL                                   20F       1       1       0   .abs_section_20f
+     _PMFVAL0                                   210       2       2       0   .abs_section_210
+     _PMFVAL1                                   212       2       2       0   .abs_section_212
+     _PMFVAL2                                   214       2       2       0   .abs_section_214
+     _PMFVAL3                                   216       2       2       0   .abs_section_216
+     _PMFVAL4                                   218       2       2       0   .abs_section_218
+     _PMFVAL5                                   21A       2       2       0   .abs_section_21a
+     _PMFENCA                                   220       1       1       0   .abs_section_220
+     _PMFFQCA                                   221       1       1       0   .abs_section_221
+     _PMFCNTA                                   222       2       2       0   .abs_section_222
+     _PMFMODA                                   224       2       2       0   .abs_section_224
+     _PMFDTMA                                   226       2       2       0   .abs_section_226
+     _PMFENCB                                   228       1       1       0   .abs_section_228
+     _PMFFQCB                                   229       1       1       0   .abs_section_229
+     _PMFCNTB                                   22A       2       2       0   .abs_section_22a
+     _PMFMODB                                   22C       2       2       0   .abs_section_22c
+     _PMFDTMB                                   22E       2       2       0   .abs_section_22e
+     _PMFENCC                                   230       1       1       0   .abs_section_230
+     _PMFFQCC                                   231       1       1       0   .abs_section_231
+     _PMFCNTC                                   232       2       2       0   .abs_section_232
+     _PMFMODC                                   234       2       2       0   .abs_section_234
+     _PMFDTMC                                   236       2       2       0   .abs_section_236
+     _PTT                                       240       1       1       0   .abs_section_240
+     PORT_T                                     240       0       0       3   .text       
+     _PTIT                                      241       1       1       0   .abs_section_241
+     _DDRT                                      242       1       1       0   .abs_section_242
+     DDR_T                                      242       0       0       0   .text       
+     _RDRT                                      243       1       1       0   .abs_section_243
+     _PERT                                      244       1       1       0   .abs_section_244
+     _PPST                                      245       1       1       0   .abs_section_245
+     _PTS                                       248       1       1       0   .abs_section_248
+     PORT_S                                     248       0       0       1   .text       
+     _PTIS                                      249       1       1       0   .abs_section_249
+     _DDRS                                      24A       1       1       0   .abs_section_24a
+     DDR_S                                      24A       0       0       0   .text       
+     _RDRS                                      24B       1       1       0   .abs_section_24b
+     _PERS                                      24C       1       1       0   .abs_section_24c
+     _PPSS                                      24D       1       1       0   .abs_section_24d
+     _WOMS                                      24E       1       1       0   .abs_section_24e
+     _PTM                                       250       1       1       5   .abs_section_250
+     _PTIM                                      251       1       1       0   .abs_section_251
+     _DDRM                                      252       1       1       1   .abs_section_252
+     _RDRM                                      253       1       1       0   .abs_section_253
+     _PERM                                      254       1       1       0   .abs_section_254
+     _PPSM                                      255       1       1       0   .abs_section_255
+     _WOMM                                      256       1       1       0   .abs_section_256
+     _PTP                                       258       1       1       0   .abs_section_258
+     PORT_P                                     258       0       0       1   .text       
+     _PTIP                                      259       1       1       0   .abs_section_259
+     _DDRP                                      25A       1       1       0   .abs_section_25a
+     DDR_P                                      25A       0       0       0   .text       
+     _RDRP                                      25B       1       1       0   .abs_section_25b
+     _PERP                                      25C       1       1       0   .abs_section_25c
+     _PPSP                                      25D       1       1       0   .abs_section_25d
+     _PTQ                                       260       1       1       0   .abs_section_260
+     _PTIQ                                      261       1       1       0   .abs_section_261
+     _DDRQ                                      262       1       1       0   .abs_section_262
+     _RDRQ                                      263       1       1       0   .abs_section_263
+     _PERQ                                      264       1       1       0   .abs_section_264
+     _PPSQ                                      265       1       1       0   .abs_section_265
+     _PTU                                       268       1       1       0   .abs_section_268
+     PORT_U                                     268       0       0       3   .text       
+     _PTIU                                      269       1       1       0   .abs_section_269
+     _DDRU                                      26A       1       1       0   .abs_section_26a
+     _RDRU                                      26B       1       1       0   .abs_section_26b
+     _PERU                                      26C       1       1       0   .abs_section_26c
+     PDR_U                                      26C       0       0       0   .text       
+     _PPSU                                      26D       1       1       0   .abs_section_26d
+     PSR_U                                      26D       0       0       0   .text       
+     _MODRR                                     26E       1       1       0   .abs_section_26e
+     _PTAD                                      270       2       2       4   .abs_section_270
+     _PTIAD                                     272       2       2       0   .abs_section_272
+     _DDRAD                                     274       2       2       1   .abs_section_274
+     _RDRAD                                     276       2       2       0   .abs_section_276
+     _PERAD                                     278       2       2       0   .abs_section_278
+     _PPSAD                                     27A       2       2       0   .abs_section_27a
+     _PIEAD                                     27C       2       2       0   .abs_section_27c
+     _PIFAD                                     27E       2       2       0   .abs_section_27e
+     data                                       500       2       2       4   .bss        
+     disp                                       502      21      33     477   my_variable 
+     password                                   523       8       8      26   my_variable 
+     entered_password                           52B       8       8      18   my_variable 
+     new_password                               533       8       8       0   my_variable 
+     pw_prompt_shown                            53B       1       1       0   my_variable 
+     pw_check                                   53C       1       1       1   my_variable 
+     pw_correct                                 53D       1       1       1   my_variable 
+     pw_set                                     53E       1       1       6   my_variable 
+     pw_incorrect                               53F       1       1       1   my_variable 
+     pw_required                                540       1       1       2   my_variable 
+     pressed_key                                541       1       1       2   my_variable 
+     pressed_num                                542       1       1      43   my_variable 
+     await_key_release                          543       1       1      35   my_variable 
+     await_key_press                            544       1       1       7   my_variable 
+     menu_active                                545       1       1       9   my_variable 
+     toast_timer                                546       2       2       5   my_variable 
+     menu_option_num                            548       1       1       5   my_variable 
+     menu_timer                                 549       2       2       5   my_variable 
+     display_timeout                            54B       1       1       0   my_variable 
+     is_watering                                54C       1       1       8   my_variable 
+     watering_timer                             54D       2       2       6   my_variable 
+     sprinkler_event                            54F       1       1       4   my_variable 
+     sprinkler_timer                            550       1       1       5   my_variable 
+     sprinkler_arr_i                            551       1       1       4   my_variable 
+     show_temperature                           552       1       1       7   my_variable 
+     fan_speed                                  553       1       1       3   my_variable 
+     circulation_count                          554       1       1       4   my_variable 
+     dc_on                                      555       1       1       3   my_variable 
+     display_time                               556       1       1       7   my_variable 
+     current_year                               557       2       2       3   my_variable 
+     current_month                              559       1       1       4   my_variable 
+     current_day                                55A       1       1       4   my_variable 
+     current_hour                               55B       1       1       4   my_variable 
+     current_minute                             55C       1       1       4   my_variable 
+     current_second                             55D       1       1       5   my_variable 
+     wall_timer                                 55E       2       2       6   my_variable 
+     clock_event                                560       1       1       1   my_variable 
+     ms_counter                                 561       2       2       4   my_variable 
+     second_passed                              563       1       1       4   my_variable 
+     setting_wall                               564       1       1       0   my_variable 
+     change_time                                565       1       1       1   my_variable 
+     pw_reset                                   566       1       1       5   my_variable 
+     word_out                                   567       2       2       2   my_variable 
+     byte_out                                   569       1       1       1   my_variable 
+     pot_value                                  56A       2       2       1   .common     
+     seconds_tens                               56C       1       1       2   clock_digits
+     IRQ_ISR                                    56C       0       0       0   IRQ_ISR.asm._SEC000000
+     seconds_ones                               56D       1       1       2   clock_digits
+     minutes_tens                               56E       1       1       0   clock_digits
+     minutes_ones                               56F       1       1       0   clock_digits
+     hours_tens                                 570       1       1       0   clock_digits
+     hours_ones                                 571       1       1       0   clock_digits
+     _Startup                                  C000       0       0       0   .init       
+     Entry                                     C000      BD     189       0   .init       
+     Init                                      C0BD      14      20       0   .init       
+     Main                                      C0D1      21      33       0   .init       
+     delay_ms                                  C0F2      17      23       5   NON_BANKED  
+     init_LCD                                  C109      52      82       1   NON_BANKED  
+     display_string                            C15B      38      56      46   NON_BANKED  
+     Delay                                     C193      1F      31       1   NON_BANKED  
+     epulse                                    C1B2      24      36       3   NON_BANKED  
+     sendCommand                               C1D6       F      15       7   NON_BANKED  
+     read_pot                                  C1E5      18      24       1   NON_BANKED  
+     KVS                                       C1FD      10      16       1   my_constant 
+     SEQUENCE                                  C20D       5       5       1   my_constant 
+     SPRINKLER_ARR                             C212       8       8       1   my_constant 
+     Circulation                               C21A      1B      27       1   circulation.asm._SEC000000
+     PulseOff                                  C235       6       6       0   circulation.asm._SEC000000
+     PrintTemperature                          C23B      B4     180       0   circulation.asm._SEC000000
+     Return                                    C2EF       6       6       0   circulation.asm._SEC000000
+     Debounce                                  C2F5       4       4       1   debounce.asm._SEC000000
+     Loop                                      C2F9       5       5       0   debounce.asm._SEC000000
+     RTI_ISR                                   C2FE      16      22       0   eventloop.asm._SEC000000
+     LessThanSec                               C314      2E      46       0   eventloop.asm._SEC000000
+     FanOff                                    C342       3       3       0   eventloop.asm._SEC000000
+     FanReset                                  C345       9       9       0   eventloop.asm._SEC000000
+     DidMotor                                  C34E      8C     140       0   eventloop.asm._SEC000000
+     CycleMenu                                 C3DA      11      17       0   eventloop.asm._SEC000000
+     StartWatering                             C3EB      23      35       0   eventloop.asm._SEC000000
+     StopWatering                              C40E      1D      29       0   eventloop.asm._SEC000000
+     Sprinkle                                  C42B      15      21       0   eventloop.asm._SEC000000
+     DisplayTemperature                        C440      23      35       0   eventloop.asm._SEC000000
+     HideTemperature                           C463      1B      27       0   eventloop.asm._SEC000000
+     DisplayTime                               C47E      23      35       0   eventloop.asm._SEC000000
+     HideTime                                  C4A1      1B      27       0   eventloop.asm._SEC000000
+     SetTime                                   C4BC       7       7       0   eventloop.asm._SEC000000
+     ResetPassword                             C4C3       7       7       0   eventloop.asm._SEC000000
+     Return                                    C4CA       5       5       0   eventloop.asm._SEC000000
+     Growlights                                C4CF      11      17       1   growlights.asm._SEC000000
+     Menu                                      C4E0       E      14       1   Code        
+     PrintTopLine                              C4EE      86     134       0   Code        
+     PrintOption1                              C574      5F      95       0   Code        
+     PrintOption2                              C5D3      5F      95       0   Code        
+     PrintOption3                              C632      5F      95       0   Code        
+     PrintOption4                              C691      5F      95       0   Code        
+     PrintOption5                              C6F0      5F      95       0   Code        
+     PrintOption6                              C74F      5D      93       0   Code        
+     PrintOption7                              C7AC      5D      93       0   Code        
+     Return                                    C809       6       6       0   Code        
+     Password                                  C80F      22      34       2   Code        
+     PasswordInit                              C831     181     385       0   Code        
+     PasswordReset                             C9B2     35D     861       0   Code        
+     PasswordCheck                             CD0F     1E1     481       0   Code        
+     Return                                    CEF0       B      11       0   Code        
+     Keypad                                    CEFB       7       7      33   Code        
+     ArrayEnd                                  CF02       7       7       0   Code        
+     InitSequence                              CF09       3       3       0   Code        
+     ReadKeypress                              CF0C      1F      31       0   Code        
+     AwaitRelease                              CF2B       9       9       0   Code        
+     InitLookup                                CF34       5       5       0   Code        
+     Lookup                                    CF39       A      10       0   Code        
+     Found                                     CF43       3       3       0   Code        
+     Return                                    CF46       6       6       0   Code        
+     Water                                     CF4C      29      41       1   Variables   
+     Continue                                  CF75      13      19       0   Variables   
+     ShowWatering                              CF88      AB     171       0   Variables   
+     Return                                    D033       6       6       0   Variables   
+     Wall                                      D039     10E     270       1   clock_code  
+     PrintWall                                 D147      CC     204       0   clock_code  
+     Return                                    D213       9       9       0   clock_code  
+
+*********************************************************************************************
+UNUSED-OBJECTS SECTION
+---------------------------------------------------------------------------------------------
+NOT USED VARIABLES
+password.asm.o:
+  pw_char_index pw_char 
+water.asm.o:
+  ARRAY_LENGTH 
+
+*********************************************************************************************
+COPYDOWN SECTION
+---------------------------------------------------------------------------------------------
+
+*********************************************************************************************
+OBJECT-DEPENDENCIES SECTION
+---------------------------------------------------------------------------------------------
+Entry                     USES __SEG_END_SSTACK await_key_release 
+                                await_key_press init_LCD password pw_set pw_incorrect 
+                                pw_correct menu_active menu_option_num menu_timer 
+                                is_watering watering_timer sprinkler_event sprinkler_timer 
+                                sprinkler_arr_i show_temperature change_time pw_reset 
+                                fan_speed circulation_count current_year current_month 
+                                current_day current_hour current_minute current_second 
+                                wall_timer clock_event second_passed ms_counter 
+                                display_time 
+Init                      USES Password pw_set menu_active pressed_num 
+Main                      USES Menu Circulation Water Growlights Wall Password 
+                                await_key_release await_key_press Keypad 
+init_LCD                  USES _DDRAD _PTAD _DDRM delay_ms _PTM data 
+                                sendCommand epulse 
+display_string            USES sendCommand data _PTAD epulse 
+epulse                    USES data _PTM delay_ms 
+sendCommand               USES data _PTAD epulse 
+read_pot                  USES _ATDCTL23 Delay _ATDCTL45 _ATDSTAT0 _ATDDR0 
+                                pot_value 
+Circulation               USES pw_set dc_on PORT_T 
+PulseOff                  USES PORT_T 
+PrintTemperature          USES show_temperature disp display_string 
+RTI_ISR                   USES ms_counter second_passed 
+LessThanSec               USES pw_set read_pot word_out fan_speed 
+                                circulation_count dc_on 
+FanOff                    USES dc_on 
+FanReset                  USES circulation_count 
+DidMotor                  USES pw_reset menu_timer toast_timer watering_timer 
+                                sprinkler_timer wall_timer pressed_num 
+CycleMenu                 USES menu_timer menu_option_num 
+StartWatering             USES watering_timer is_watering show_temperature 
+                                display_time pressed_num menu_active 
+StopWatering              USES watering_timer is_watering menu_active 
+Sprinkle                  USES sprinkler_timer is_watering sprinkler_event 
+DisplayTemperature        USES toast_timer is_watering menu_active 
+                                display_time pressed_num show_temperature 
+HideTemperature           USES toast_timer show_temperature menu_active 
+DisplayTime               USES wall_timer is_watering show_temperature 
+                                menu_active display_time pressed_num 
+HideTime                  USES wall_timer display_time menu_active 
+SetTime                   USES pw_required 
+ResetPassword             USES pw_reset 
+Return                    USES CRGFLG 
+Growlights                USES PORT_T PORT_S 
+Menu                      USES menu_active 
+PrintTopLine              USES disp menu_option_num 
+PrintOption1              USES disp display_string 
+PrintOption2              USES disp display_string 
+PrintOption3              USES disp display_string 
+PrintOption4              USES disp display_string 
+PrintOption5              USES disp display_string 
+PrintOption6              USES disp display_string 
+PrintOption7              USES disp display_string 
+Password                  USES pw_set pw_reset pw_check 
+PasswordInit              USES disp display_string await_key_press 
+                                await_key_release Keypad pressed_num password pw_set 
+PasswordReset             USES disp display_string await_key_press 
+                                await_key_release Keypad pressed_num entered_password password 
+                                pw_reset 
+PasswordCheck             USES disp display_string await_key_press 
+                                await_key_release Keypad pressed_num entered_password password 
+                                pw_required 
+Return                    USES pressed_num 
+ArrayEnd                  USES await_key_press 
+InitSequence              USES SEQUENCE 
+ReadKeypress              USES PORT_U Debounce pressed_key await_key_release 
+AwaitRelease              USES PORT_U 
+InitLookup                USES KVS 
+Lookup                    USES pressed_key 
+Found                     USES pressed_num 
+Water                     USES is_watering sprinkler_event sprinkler_arr_i 
+Continue                  USES SPRINKLER_ARR word_out PORT_P byte_out 
+                                sprinkler_event 
+ShowWatering              USES disp display_string 
+Wall                      USES second_passed current_second current_minute 
+                                current_hour current_day current_month current_year disp 
+PrintWall                 USES display_time current_second seconds_ones 
+                                seconds_tens disp display_string 
+Return                    USES second_passed 
+
+*********************************************************************************************
+DEPENDENCY TREE
+*********************************************************************************************
+ RTI_ISR             
+   
+*********************************************************************************************
+STATISTIC SECTION
+---------------------------------------------------------------------------------------------
+
+ExeFile:
+--------
+Number of blocks to be downloaded: 11
+Total size of all blocks to be downloaded: 4642
+

Final_Project/bin/Project.xpr

@@ -0,0 +1,2 @@
+Data:1 < ADDXPR ONLY_ADD_IF_NEW "main.dbg::disp"
+Data:1 < ADDXPR ONLY_ADD_IF_NEW "main.dbg::pw_incorrect"

Final_Project/bin/RTI_ISR.dbg

@@ -0,0 +1,3 @@
+              XDEF      RTI_ISR
+              
+RTI_ISR:

Final_Project/bin/circulation.dbg

@@ -0,0 +1,92 @@
+ 	XDEF	Circulation
+	XREF	__SEG_END_SSTACK,show_temperature,display_string,disp,dc_on,pw_set,PORT_T,PORT_S
+	
+Circulation: ;push register and accumulator values for retention                   
+            PSHA
+            PSHB
+            PSHD
+            PSHX
+            PSHY
+            
+
+           ;bail if the password is not set
+           LDAA   pw_set
+           CMPA   #$FF
+           LBNE   Return
+            
+           ;
+           ;run the motor and stuff like that here
+           ;(the motor should run whether or not
+           ;the temperature is displayed) 
+           ;
+           LDAA   dc_on
+           CMPA   #$FF
+           BNE    PulseOff
+
+PulseOn:
+            BSET  PORT_T,#$8       ;set bit 3 of Port T
+            ;MOVB  #$0F,PORT_S
+            BRA   PrintTemperature ;exit the interrupt routine
+
+PulseOff:
+            BCLR  PORT_T,#$8       ;clear bit 3 of Port T
+            ;MOVB  #$F0,PORT_S
+            BRA   PrintTemperature ;exit the interrupt 
+             
+PrintTemperature:
+
+           ;check if the temperature should show
+           LDAA  show_temperature
+           CMPA  #$00
+           LBEQ   Return
+           
+          ;print the temperature
+           movb #'T',disp
+           movb #'e',disp+1
+           movb #'m',disp+2
+           movb #'p',disp+3
+           movb #'e',disp+4
+           movb #'r',disp+5
+           movb #'a',disp+6
+           movb #'t',disp+7
+           movb #'u',disp+8
+           movb #'r',disp+9
+           movb #'e',disp+10
+           movb #':',disp+11
+           movb #' ',disp+12
+           movb #' ',disp+13
+           movb #' ',disp+14
+           movb #' ',disp+15
+           ;next line
+           movb #'X',disp+16
+           movb #'Y',disp+17
+           movb #'Z',disp+18
+           movb #' ',disp+19
+           movb #'d',disp+20
+           movb #'e',disp+21
+           movb #'g',disp+22
+           movb #'r',disp+23
+           movb #'e',disp+24
+           movb #'e',disp+25
+           movb #'s',disp+26
+           movb #' ',disp+27
+           movb #' ',disp+28
+           movb #' ',disp+29
+           movb #' ',disp+30
+           movb #' ',disp+31
+           movb #0,disp+32    ;string terminator, acts like '\0'
+           
+           LDD   #disp         ;both of these steps are necessary to
+           jsr  display_string ;print to the LCD screen          
+    
+Return:     ;restore registers and accumulators
+           PULY
+           PULX
+           PULD
+           PULB
+           PULA
+           
+           RTS
+   
+	
+	

Final_Project/bin/debounce.dbg

@@ -0,0 +1,17 @@
+	XDEF	Debounce
+	XREF	__SEG_END_SSTACK	
+	
+Debounce:
+    PSHX          ;save X register                                  
+    LDX   #1000   ;1 ms delay
+    
+Loop:             ;delay loop
+    DEX
+    BNE   Loop
+    
+    PULX          ;restore X register
+    RTS           ;go back
+    
+   
+	
+	

Final_Project/bin/eventloop.dbg

@@ -0,0 +1,328 @@
+  ;export symbols
+	XDEF  RTI_ISR
+		
+	XREF	__SEG_END_SSTACK,disp,CRGFLG,read_pot
+	;clock
+	XREF  display_time,wall_timer
+  ;password
+  XREF  pw_set,pw_reset,pw_required
+  ;keypad
+  XREF  pressed_key,pressed_num
+  ;menu
+  XREF  menu_timer,menu_option_num,menu_active,menu_selection
+  ;circulation
+  XREF  dc_on,circulation_count,fan_speed
+  ;temperature
+  XREF  show_temperature,toast_timer
+  ;watering
+  XREF  is_watering,watering_timer,sprinkler_event,sprinkler_timer
+  ;wall clock
+  XREF  second_passed,ms_counter
+  ;debug
+  XREF  word_out
+   
+RTI_ISR:
+
+EventLoop:
+            ;***************** NOTE ****************
+            ; the menu timer is a general timer for
+            ; what to display
+            ;***************************************
+
+            ; ========= wall clock ==========
+            ;the event loop is configured (in main.asm) to run every 4 milliseconds
+            LDD   ms_counter        ;counts the milliseconds for the wall clock
+            ADDD  #04               ;add 4 milleseconds evey time the event loop runs (effectively the count starts at 4)
+            STD   ms_counter        ;store the ms_counter in memory (mostly for debugging)
+            CPD   #1004             ;check if one second has passed (accounting for the start at 4)
+            BLE   LessThanSec       ;less than one second has passed, continue to other functions
+            ;one second has passed
+            MOVB  #$FF,second_passed  ;this flag is set here and cleared in wall.asm
+            CLR   ms_counter
+            
+LessThanSec:;less than one second has passwed (do not fire a second passed event)              
+            ;don't do anything (except track the time) if the password is not set
+            LDAA  pw_set
+            CMPA  #$FF
+            LBNE   Return
+            
+            ;========= circualtion ===========
+            ;circulation is always happening (if the password is set)
+            ;the motor should spin as soon as the password is set
+            JSR 	read_pot            ;read the value of the pot into D
+            STD   word_out
+            LDX   #8		              ;load the bottom part of the divide (forget what it's called)
+                                      ;dividing 128 pot val. by 8 wields 16 different speeds possible                                  
+            IDIV                      ;value 1 through 16 is now in X
+            XGDX                      ;put the value in D
+            STAB  fan_speed           ;the lower byte of D is the fan speed, higher value for faster speed
+            
+            ;counter is in A
+            LDAA  circulation_count
+            INCA  
+            STAA  circulation_count
+            
+            ;from lab 6.3
+            ;here, fan speed has replaced the pressed value
+            CMPA  fan_speed           ;compare the counter to the fan speed
+            LBGT  FanOff              ;turn the fan off (low PWM)
+FanOn:      ;if the PWM should be high
+            MOVB  #$FF,dc_on          ;set the PWM high
+            BRA   FanReset            ;skip setting the pulse low
+
+            ;LBLE  SpinDC              ;branch to the stepper spinner
+             
+FanOff:     ;turn off the motor's PWM (low cycle)
+            CLR   dc_on            
+
+FanReset:   ;check if the fan counter needsd to be reset            
+            ;acc. A still has the circulation count
+            CMPA  #15                 ;16 is the max value of fan_speed
+            LBLE  DidMotor            ;do not clear the count if the count is in line with the speed       
+            CLR   circulation_count
+
+DidMotor:   ;branch here if the motor PWM has been applied
+
+            ;exit if the password is resetting 
+            LDAA  pw_reset
+            CMPA  #$FF
+            LBEQ  Return
+            
+            ;exit if the password is required
+            ;LDAA  pw_required
+            ;CMPA  #$FF
+            ;LBEQ  Return  
+
+            ;======== menu ===============
+            ;delay the menu change
+            LDX   menu_timer
+            INX
+            STX   menu_timer
+           
+            ;the menu should change here
+            LDX   menu_timer
+            CPX   #300
+            LBGE   CycleMenu
+            
+            ;==========================
+            LDX   toast_timer
+            INX
+            STX   toast_timer
+            
+            LDX   toast_timer
+            CPX   #200
+            LBGE   HideTemperature
+
+            ;====== watering ============
+            ;delay the watering stop
+            LDX  watering_timer
+            INX
+            STX  watering_timer
+ 
+            ;run sprinker
+            LDAA  sprinkler_timer
+            INCA  
+            STAA  sprinkler_timer
+            
+            LDAA  sprinkler_timer
+            CMPA  #7
+            LBGE  Sprinkle
+           
+            ;watering stop
+            LDX  watering_timer
+            CPX  #500
+            LBGE  StopWatering
+            
+            ;======= wall clock display ========
+            
+            LDX   wall_timer
+            INX
+            STX   wall_timer
+            
+            LDX   wall_timer
+            CPX   #200
+            LBGE  HideTime
+            
+            ;======= menu options ===========
+            ;call these here so that the counters can increment
+            ;watering start
+            LDAA  pressed_num
+            CMPA  #$01
+            BEQ   StartWatering
+            
+            ;show temperature
+            LDAA  pressed_num
+            CMPA  #$02
+            LBEQ  DisplayTemperature
+            
+            ;show wall clock
+            LDAA  pressed_num
+            CMPA  #$03
+            LBEQ  DisplayTime
+            
+            ;set time and date
+            LDAA  pressed_num
+            CMPA  #$04
+            LBEQ  SetTime
+            
+            ;trigger password reset
+            LDAA  pressed_num
+            CMPA  #$05
+            LBEQ  ResetPassword
+                  
+            ;======= temperature ========
+            ;delay the temperature display stoppage
+            ;LDX   temp_timer
+            ;INX
+            ;STX   temp_timer
+            
+
+            ;hide temperature
+            ;LDX  watering_timer
+            ;CPX  #750
+            ;BEQ   HideTemperature
+                                  
+            ;
+            ; 
+            ;LDAA  pressed_num         ;input into A for comparison
+            ;==================== menu items ======================
+            ;CMPA  #$01
+            ;BEQ   WaterPlants
+            
+            ;CMPA  #$02                ;pressed_num is the selected menu option
+            ;BEQ   ShowTemperature     ;menu option 1 is temperature
+            ;======================================================
+            ;
+            ;
+            ;
+            
+            ;return by default
+            LBRA   Return
+
+CycleMenu:  
+            ;reset the timer (s) and go to the next menu option
+            MOVW  #$0000,menu_timer     ;reset menu timer
+
+            ;track the menu option (this resets to 1 in menu.asm)
+            LDAA  menu_option_num
+            INCA  
+            STAA  menu_option_num
+            
+            ;exit
+            LBRA   Return  
+            
+            
+StartWatering:
+            ;water for a certain amount of time
+            MOVW  #$0000,watering_timer ;reset the watering timer
+            MOVB  #$FF,is_watering      ;turn on the water
+            
+            ;hide the other options
+            MOVB  #$00,show_temperature
+            MOVB  #$00,display_time
+            
+            MOVB  #$FF,pressed_num      ;clear the pressed number value
+            MOVB  #$00,menu_active      ;turn off the menu (dispay watering...)
+
+            LBRA   Return               ;exit
+            
+StopWatering:
+            MOVW  #$0000,watering_timer ;reset the watering timer
+            
+            LDAA  is_watering            ;check that watering needs to be stopped
+            CMPA  #$00
+            LBEQ  Return
+            
+            MOVB  #$00,is_watering       ;turn off the water
+            MOVB  #$FF,menu_active       ;restore the menu display
+            LBRA   Return                ;exit
+
+Sprinkle:
+            ;the sprinkler timer controls the speed of the stepper motor
+            CLR   sprinkler_timer
+            
+            ;check that the watering state is active before firing an event
+            LDAA  is_watering
+            CMPA  #$FF
+            LBNE   Return
+            
+            ;instruct the watering subroutine to send a signal to the stepper motor
+            MOVB  #$FF,sprinkler_event
+
+            ;exit
+            LBRA   Return
+       
+       
+DisplayTemperature:
+            MOVW  #$0000,toast_timer    ;clear the temperature timer
+            
+            ;do not disrupt watering
+            LDAA  is_watering
+            CMPA  #$FF
+            BEQ   Return
+
+            ;hide the other options
+            MOVB  #$00,menu_active      ;hide the menu
+            MOVB  #$00,display_time     ;hide the time
+            
+            MOVB  #$FF,pressed_num      ;clear the pressed number value
+            MOVB  #$FF,show_temperature ;set the show temperature flag
+            
+            BRA   Return
+            
+HideTemperature:
+            MOVW  #$0000,toast_timer    ;clear the temperature timer
+            
+            LDAA  show_temperature      ;do nothing if temperature is not showing
+            CMPA  #$00
+            LBEQ  Return
+
+            MOVB  #$00,show_temperature ;clear the show temperature flag       
+            MOVB  #$FF,menu_active      ;restore the menu
+            BRA   Return
+            
+DisplayTime:
+            MOVW  #$0000,wall_timer     ;clear the clock display timer
+            
+            ;do not disrupt watering
+            LDAA  is_watering
+            CMPA  #$FF
+            BEQ   Return
+            
+            ;hide the other display options
+            MOVB  #$00,show_temperature ;hide the temperature
+            MOVB  #$00,menu_active      ;hide the menu
+            
+            MOVB  #$FF,display_time     ;set the time display flag
+            MOVB  #$FF,pressed_num      ;clear the pressed number
+            
+            BRA   Return
+            
+HideTime:
+
+            MOVW  #$0000,wall_timer     ;clear the clock display timer
+            
+            LDAA  display_time
+            CMPA  #$00
+            LBEQ  Return
+
+            MOVB  #$00,display_time    ;clear the time display flag
+            MOVB  #$FF,menu_active     ;re-activate the menu
+            
+            BRA   Return
+           
+SetTime:
+            MOVB  #$FF,pw_required
+            BRA   Return
+            
+ResetPassword:
+            MOVB  #$FF,pw_reset
+            BRA   Return                                   
+          
+Return:
+            BSET  CRGFLG,$80
+            RTI
+            
+
+  
+  

Final_Project/bin/growlights.dbg

@@ -0,0 +1,27 @@
+                                                     	XDEF	Growlights
+	XREF	__SEG_END_SSTACK,grow_lights,PORT_T,PORT_S	
+	
+Growlights: ;push register and accumulator values for retention                   
+            PSHA
+            PSHB
+            PSHD
+            PSHX
+            PSHY
+
+            ;simply read the switches at T and output to LED's at S
+            LDAA    PORT_T
+            ;bit 3 is for the MOTOR
+            ;ANDA    #%11110111
+            STAA    PORT_S
+    
+Return:     ;restore registers and accumulators
+            PULY
+            PULX
+            PULD
+            PULB
+            PULA
+            
+            RTS
+   
+	
+	

Final_Project/bin/keypad.dbg

@@ -0,0 +1,97 @@
+          	XDEF	Keypad
+	XREF	__SEG_END_SSTACK,Debounce,KVS,pressed_key,pressed_num,PORT_U,SEQUENCE,PORT_S,await_key_release,keypad_timeout,await_key_press
+	
+Variables:	    	Section
+
+Constants:	      Section
+
+Code:		  	Section
+Keypad:     ;push register and accumulator values for retention                   
+            PSHA
+            PSHB
+            PSHD
+            PSHX
+            PSHY
+            
+            ;do not go to the task at the end of the array
+            ;when first starting i.e. ckip ArrayEnd for now
+            BRA   InitSequence
+
+ArrayEnd:   ;check the flag to await or not (await for passwords)
+            LDAB  await_key_press
+            CMPB  #$00          ;await is false
+            BEQ   Return        ;don't do anything else (do not await a keypress)
+                                ;otherwise re-initialze the sequence
+InitSequence:
+            LDX   #SEQUENCE     ;load the sequence into the X register
+ReadKeypress:
+
+
+            ;check wether or not to await
+            LDAA  1,X+          ;load the value at address in reg X to A
+            CMPA  #$00          ;check the value of A to zero
+            BEQ   ArrayEnd      ;this is the end of the array
+            
+            ;
+            ;
+            ;
+            ;given in instructions
+            STAA  PORT_U        ;output to port U
+            JSR   Debounce      ;delay 1 ms
+            LDAA  PORT_U        ;read port U back into acc. A
+            STAA  pressed_key   ;save the value of acc. A into memory (the value of the KVS array)
+            
+            ANDA  #$0F          ;mask the upper nibble
+            CMPA  #$0F          ;check if masked A == #$0F (no key pressed)
+            BEQ   ReadKeypress  ;send the next item in the sequence
+                        
+            ;
+            ;
+            ;
+            ;skip the release wait if the variable is set
+            LDAA  await_key_release
+            CMPA  #$00
+            BEQ   InitLookup
+            
+AwaitRelease:                   ;a key is pressed
+            LDAA  PORT_U        ;read port U
+            ANDA  #$0F          ;mask the upper nibble
+            CMPA  #$0F          ;check if masked A == #$0F (no key pressed)
+            BNE   AwaitRelease  ;wait for the key to be released
+            
+            
+InitLookup:                     ;check for a match in the lookup table
+            LDY   #KVS          ;load the initital value of KVS array
+            LDAB  #$00          ;iteration counter
+Lookup:
+            LDAA  1,Y+          ;load a value from the lookup table into A
+            CMPA  pressed_key       ;compare the LUT value to the pressed key
+            BEQ   Found         ;pressed key reached/found within LUT
+            INCB                ;increment the counter
+            BRA   Lookup        ;check the value at the next index
+Found:
+            STAB  pressed_num   ;the index of the PRESSED value (the numeral of the pressed key) in the KVS/LUT from B -> memory  
+
+;AwaitPress:
+;            LDAB  await_key_press
+;            CMPB  #$FF
+;            BEQ   InitSequence            
+            
+Return:     
+            ;clear the keypad timeout
+            ;CLR   keypad_timeout
+            ;restore registers and accumulators
+            PULY
+            PULX
+            PULD
+            PULB
+            PULA
+            
+            RTS
+            
+            
+            
+            
+            
+                
+            

Final_Project/bin/main.dbg

@@ -0,0 +1,7607 @@
+                                                                                                                                      ;**************************************************************
+;* This stationery serves as the framework for a              *
+;* user application. For a more comprehensive program that    *
+;* demonstrates the more advanced functionality of this       *
+;* processor, please see the demonstration applications       *
+;* located in the examples subdirectory of the                *
+;* Freescale CodeWarrior for the HC12 Program directory       *
+;**************************************************************
+; Include derivative-specific definitions
+            INCLUDE 'derivative.inc'
+
+ ; Note: This file is recreated by the project wizard whenever the MCU is
+ ;       changed and should not be edited by hand
+ ;
+
+			; include derivative specific macros
+            INCLUDE 'mc9s12e128.inc'
+; Based on CPU DB MC9S12E128_112, version 2.87.542 (RegistersPrg V2.29)
+
+; ###################################################################
+;     Filename  : mc9s12e128.inc
+;     Processor : MC9S12E128BCPV
+;     FileFormat: V2.29
+;     DataSheet : 9S12E-FamilyDGV1/D V01.01
+;     Compiler  : CodeWarrior compiler
+;     Date/Time : 6.8.2009, 10:24
+;     Abstract  :
+;         This header implements the mapping of I/O devices.
+;
+;     Copyright : 1997 - 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+;     
+;     http      : www.freescale.com
+;     mail      : support@freescale.com
+;
+;     CPU Registers Revisions:
+;      - 12.07.2006, V2.87.502:
+;              - Added bit 15 to PMFVALx registers. REASON: Bug-fix (#3494 in Issue Manager)
+;      - 23.08.2006, V2.87.522:
+;              - Renamed register VREGCTRL0 ==> VREGCTRL. REASON: Bug-fix (#<3647> in Issue Manager)
+;      - 12.09.2006, V2.87.526:
+;              - Removed bits PMFVALx_PMFVAL0x. REASON: Bug-fix (#3494 in Issue Manager)
+;      - 6.08.2009, V2.87.542:
+;              - Single bits of PMFCNTx, PMFMODx, PMFDTMx registers merged to PMFCNTx[0:14], PMFMODx[0:14], PMFDTMx[0:14] groups. REASON: Access to individual bits is useless (#7539 in Issue Manager)
+;
+;     File-Format-Revisions:
+;      - 14.11.2005, V2.00 :
+;               - Deprecated symbols added for backward compatibility (section at the end of this file)
+;      - 15.11.2005, V2.01 :
+;               - Fixed invalid instruction in macro __RESET_WATCHDOG for HCS12 family.
+;      - 17.12.2005, V2.02 :
+;               - Arrays (symbols xx_ARR) are defined as pointer to volatile, see issue #2778
+;      - 16.01.2006, V2.03 :
+;               - Fixed declaration of non volatile registers. Now it does not require (but allows) their initialization, see issue #2920.
+;               - "volatile" modifier removed from declaration of non volatile registers (that contain modifier "const")
+;      - 08.03.2006, V2.04 :
+;               - Support for bit(s) names duplicated with any register name in .h header files
+;      - 24.03.2006, V2.05 :
+;               - Fixed macro __RESET_WATCHDOG for HCS12 family - address and correct write order.
+;      - 26.04.2006, V2.06 :
+;               - Changes have not affected this file (because they are related to another family)
+;      - 27.04.2006, V2.07 :
+;               - Fixed macro __RESET_WATCHDOG for HCS12, HCS12X ,HCS08 DZ and HCS08 EN derivatives (write 0x55,0xAA).
+;      - 07.06.2006, V2.08 :
+;               - Changes have not affected this file (because they are related to another family)
+;      - 03.07.2006, V2.09 :
+;               - Changes have not affected this file (because they are related to another family)
+;      - 27.10.2006, V2.10 :
+;               - __RESET_WATCHDOG improved formating and re-definition
+;      - 23.11.2006, V2.11 :
+;               - Changes have not affected this file (because they are related to another family)
+;      - 22.01.2007, V2.12 :
+;               - Fixed declaration of non volatile registers. Now it does not require (but allows) their initialization, see issue #4086.
+;      - 01.03.2007, V2.13 :
+;               - Flash commands constants values converted to HEX format
+;      - 02.03.2007, V2.14 :
+;               - Interrupt vector numbers added into .H, see VectorNumber_*
+;      - 26.03.2007, V2.15 :
+;               - Changes have not affected this file (because they are related to another family)
+;      - 10.05.2007, V2.16 :
+;               - Changes have not affected this file (because they are related to another family)
+;      - 05.06.2007, V2.17 :
+;               - Changes have not affected this file (because they are related to another family)
+;      - 19.07.2007, V2.18 :
+;               - Improved number of blanked lines inside register structures
+;      - 06.08.2007, V2.19 :
+;               - CPUDB revisions generated ahead of the file-format revisions.
+;      - 11.09.2007, V2.20 :
+;               - Added comment about initialization of unbonded pins.
+;      - 02.01.2008, V2.21 :
+;               - Changes have not affected this file (because they are related to another family)
+;      - 13.02.2008, V2.22 :
+;               - Changes have not affected this file (because they are related to another family)
+;      - 20.02.2008, V2.23 :
+;               - Termination of pragma V30toV31Compatible added, #5708
+;      - 03.07.2008, V2.24 :
+;               - Added support for bits with name starting with number (like "1HZ")
+;      - 28.11.2008, V2.25 :
+;               - StandBy RAM array declaration for ANSI-C added
+;      - 1.12.2008, V2.26 :
+;               - Duplication of bit (or bit-group) name with register name is not marked as a problem, is register is internal only and it is not displayed in I/O map.
+;      - 17.3.2009, V2.27 :
+;               - Merged bit-group is not generated, if the name matches with another bit name in the register
+;      - 6.4.2009, V2.28 :
+;               - Fixed generation of merged bits for bit-groups with a digit at the end, if group-name is defined in CPUDB
+;      - 3.8.2009, V2.29 :
+;               - If there is just one bits group matching register name, single bits are not generated
+;
+;     Not all general-purpose I/O pins are available on all packages or on all mask sets of a specific
+;     derivative device. To avoid extra current drain from floating input pins, the user’s reset
+;     initialization routine in the application program must either enable on-chip pull-up devices
+;     or change the direction of unconnected pins to outputs so the pins do not float.
+; ###################################################################
+
+;*** Memory Map and Interrupt Vectors
+;******************************************
+RAMStart:           equ   $00000400
+RAMEnd:             equ   $00001FFF
+ROM_4000Start:      equ   $00004000
+ROM_4000End:        equ   $00007FFF
+ROM_C000Start:      equ   $0000C000
+ROM_C000End:        equ   $0000FEFF
+PAGE_38Start:       equ   $00388000
+PAGE_38End:         equ   $0038BFFF
+PAGE_39Start:       equ   $00398000
+PAGE_39End:         equ   $0039BFFF
+PAGE_3AStart:       equ   $003A8000
+PAGE_3AEnd:         equ   $003ABFFF
+PAGE_3BStart:       equ   $003B8000
+PAGE_3BEnd:         equ   $003BBFFF
+PAGE_3CStart:       equ   $003C8000
+PAGE_3CEnd:         equ   $003CBFFF
+PAGE_3DStart:       equ   $003D8000
+PAGE_3DEnd:         equ   $003DBFFF
+;
+VReserved63:        equ   $0000FF80
+VReserved62:        equ   $0000FF82
+VReserved61:        equ   $0000FF84
+VReserved60:        equ   $0000FF86
+Vpwmesdn:           equ   $0000FF88
+Vvreglvi:           equ   $0000FF8A
+Vpmffault3:         equ   $0000FF8C
+Vpmffault2:         equ   $0000FF8E
+Vpmffault1:         equ   $0000FF90
+Vpmffault0:         equ   $0000FF92
+Vpmfgcr:            equ   $0000FF94
+Vpmfgbr:            equ   $0000FF96
+Vpmfgar:            equ   $0000FF98
+Vtim2paie:          equ   $0000FF9A
+Vtim2paovf:         equ   $0000FF9C
+Vtim2ovf:           equ   $0000FF9E
+Vtim2ch7:           equ   $0000FFA0
+Vtim2ch6:           equ   $0000FFA2
+Vtim2ch5:           equ   $0000FFA4
+Vtim2ch4:           equ   $0000FFA6
+VReserved43:        equ   $0000FFA8
+Vtim1paie:          equ   $0000FFAA
+Vtim1paovf:         equ   $0000FFAC
+Vtim1ovf:           equ   $0000FFAE
+Vtim1ch7:           equ   $0000FFB0
+Vtim1ch6:           equ   $0000FFB2
+Vtim1ch5:           equ   $0000FFB4
+Vtim1ch4:           equ   $0000FFB6
+Vflash:             equ   $0000FFB8
+VReserved34:        equ   $0000FFBA
+VReserved33:        equ   $0000FFBC
+VReserved32:        equ   $0000FFBE
+Viic:               equ   $0000FFC0
+VReserved30:        equ   $0000FFC2
+Vcrgscm:            equ   $0000FFC4
+Vcrgplllck:         equ   $0000FFC6
+VReserved27:        equ   $0000FFC8
+VReserved26:        equ   $0000FFCA
+VReserved25:        equ   $0000FFCC
+Vportad:            equ   $0000FFCE
+Vatd0:              equ   $0000FFD0
+Vsci2:              equ   $0000FFD2
+Vsci1:              equ   $0000FFD4
+Vsci0:              equ   $0000FFD6
+Vspi:               equ   $0000FFD8
+Vtim0paie:          equ   $0000FFDA
+Vtim0paovf:         equ   $0000FFDC
+Vtim0ovf:           equ   $0000FFDE
+Vtim0ch7:           equ   $0000FFE0
+Vtim0ch6:           equ   $0000FFE2
+Vtim0ch5:           equ   $0000FFE4
+Vtim0ch4:           equ   $0000FFE6
+VReserved11:        equ   $0000FFE8
+VReserved10:        equ   $0000FFEA
+VReserved9:         equ   $0000FFEC
+VReserved8:         equ   $0000FFEE
+Vrti:               equ   $0000FFF0
+Virq:               equ   $0000FFF2
+Vxirq:              equ   $0000FFF4
+Vswi:               equ   $0000FFF6
+Vtrap:              equ   $0000FFF8
+Vcop:               equ   $0000FFFA
+Vclkmon:            equ   $0000FFFC
+Vreset:             equ   $0000FFFE
+;
+
+
+;*** PORTAB - Port AB Register; 0x00000000 ***
+PORTAB:             equ    $00000000                                ;*** PORTAB - Port AB Register; 0x00000000 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PORTAB_BIT0:        equ    0                                         ; Port AB Bit 0
+PORTAB_BIT1:        equ    1                                         ; Port AB Bit 1
+PORTAB_BIT2:        equ    2                                         ; Port AB Bit 2
+PORTAB_BIT3:        equ    3                                         ; Port AB Bit 3
+PORTAB_BIT4:        equ    4                                         ; Port AB Bit 4
+PORTAB_BIT5:        equ    5                                         ; Port AB Bit 5
+PORTAB_BIT6:        equ    6                                         ; Port AB Bit 6
+PORTAB_BIT7:        equ    7                                         ; Port AB Bit 7
+PORTAB_BIT8:        equ    8                                         ; Port AB Bit 8
+PORTAB_BIT9:        equ    9                                         ; Port AB Bit 9
+PORTAB_BIT10:       equ    10                                        ; Port AB Bit 10
+PORTAB_BIT11:       equ    11                                        ; Port AB Bit 11
+PORTAB_BIT12:       equ    12                                        ; Port AB Bit 12
+PORTAB_BIT13:       equ    13                                        ; Port AB Bit 13
+PORTAB_BIT14:       equ    14                                        ; Port AB Bit 14
+PORTAB_BIT15:       equ    15                                        ; Port AB Bit 15
+; bit position masks
+mPORTAB_BIT0:       equ    %00000001
+mPORTAB_BIT1:       equ    %00000010
+mPORTAB_BIT2:       equ    %00000100
+mPORTAB_BIT3:       equ    %00001000
+mPORTAB_BIT4:       equ    %00010000
+mPORTAB_BIT5:       equ    %00100000
+mPORTAB_BIT6:       equ    %01000000
+mPORTAB_BIT7:       equ    %10000000
+mPORTAB_BIT8:       equ    %100000000
+mPORTAB_BIT9:       equ    %1000000000
+mPORTAB_BIT10:      equ    %10000000000
+mPORTAB_BIT11:      equ    %100000000000
+mPORTAB_BIT12:      equ    %1000000000000
+mPORTAB_BIT13:      equ    %10000000000000
+mPORTAB_BIT14:      equ    %100000000000000
+mPORTAB_BIT15:      equ    %1000000000000000
+
+
+;*** PORTA - Port A Register; 0x00000000 ***
+PORTA:              equ    $00000000                                ;*** PORTA - Port A Register; 0x00000000 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PORTA_BIT0:         equ    0                                         ; Port A Bit 0
+PORTA_BIT1:         equ    1                                         ; Port A Bit 1
+PORTA_BIT2:         equ    2                                         ; Port A Bit 2
+PORTA_BIT3:         equ    3                                         ; Port A Bit 3
+PORTA_BIT4:         equ    4                                         ; Port A Bit 4
+PORTA_BIT5:         equ    5                                         ; Port A Bit 5
+PORTA_BIT6:         equ    6                                         ; Port A Bit 6
+PORTA_BIT7:         equ    7                                         ; Port A Bit 7
+; bit position masks
+mPORTA_BIT0:        equ    %00000001
+mPORTA_BIT1:        equ    %00000010
+mPORTA_BIT2:        equ    %00000100
+mPORTA_BIT3:        equ    %00001000
+mPORTA_BIT4:        equ    %00010000
+mPORTA_BIT5:        equ    %00100000
+mPORTA_BIT6:        equ    %01000000
+mPORTA_BIT7:        equ    %10000000
+
+
+;*** PORTB - Port B Register; 0x00000001 ***
+PORTB:              equ    $00000001                                ;*** PORTB - Port B Register; 0x00000001 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PORTB_BIT0:         equ    0                                         ; Port B Bit 0
+PORTB_BIT1:         equ    1                                         ; Port B Bit 1
+PORTB_BIT2:         equ    2                                         ; Port B Bit 2
+PORTB_BIT3:         equ    3                                         ; Port B Bit 3
+PORTB_BIT4:         equ    4                                         ; Port B Bit 4
+PORTB_BIT5:         equ    5                                         ; Port B Bit 5
+PORTB_BIT6:         equ    6                                         ; Port B Bit 6
+PORTB_BIT7:         equ    7                                         ; Port B Bit 7
+; bit position masks
+mPORTB_BIT0:        equ    %00000001
+mPORTB_BIT1:        equ    %00000010
+mPORTB_BIT2:        equ    %00000100
+mPORTB_BIT3:        equ    %00001000
+mPORTB_BIT4:        equ    %00010000
+mPORTB_BIT5:        equ    %00100000
+mPORTB_BIT6:        equ    %01000000
+mPORTB_BIT7:        equ    %10000000
+
+
+;*** DDRAB - Port AB Data Direction Register; 0x00000002 ***
+DDRAB:              equ    $00000002                                ;*** DDRAB - Port AB Data Direction Register; 0x00000002 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+DDRAB_BIT0:         equ    0                                         ; Data Direction Port B Bit 0
+DDRAB_BIT1:         equ    1                                         ; Data Direction Port B Bit 1
+DDRAB_BIT2:         equ    2                                         ; Data Direction Port B Bit 2
+DDRAB_BIT3:         equ    3                                         ; Data Direction Port B Bit 3
+DDRAB_BIT4:         equ    4                                         ; Data Direction Port B Bit 4
+DDRAB_BIT5:         equ    5                                         ; Data Direction Port B Bit 5
+DDRAB_BIT6:         equ    6                                         ; Data Direction Port B Bit 6
+DDRAB_BIT7:         equ    7                                         ; Data Direction Port B Bit 7
+DDRAB_BIT8:         equ    8                                         ; Data Direction Port A Bit 8
+DDRAB_BIT9:         equ    9                                         ; Data Direction Port A Bit 9
+DDRAB_BIT10:        equ    10                                        ; Data Direction Port A Bit 10
+DDRAB_BIT11:        equ    11                                        ; Data Direction Port A Bit 11
+DDRAB_BIT12:        equ    12                                        ; Data Direction Port A Bit 12
+DDRAB_BIT13:        equ    13                                        ; Data Direction Port A Bit 13
+DDRAB_BIT14:        equ    14                                        ; Data Direction Port A Bit 14
+DDRAB_BIT15:        equ    15                                        ; Data Direction Port A Bit 15
+; bit position masks
+mDDRAB_BIT0:        equ    %00000001
+mDDRAB_BIT1:        equ    %00000010
+mDDRAB_BIT2:        equ    %00000100
+mDDRAB_BIT3:        equ    %00001000
+mDDRAB_BIT4:        equ    %00010000
+mDDRAB_BIT5:        equ    %00100000
+mDDRAB_BIT6:        equ    %01000000
+mDDRAB_BIT7:        equ    %10000000
+mDDRAB_BIT8:        equ    %100000000
+mDDRAB_BIT9:        equ    %1000000000
+mDDRAB_BIT10:       equ    %10000000000
+mDDRAB_BIT11:       equ    %100000000000
+mDDRAB_BIT12:       equ    %1000000000000
+mDDRAB_BIT13:       equ    %10000000000000
+mDDRAB_BIT14:       equ    %100000000000000
+mDDRAB_BIT15:       equ    %1000000000000000
+
+
+;*** DDRA - Port A Data Direction Register; 0x00000002 ***
+DDRA:               equ    $00000002                                ;*** DDRA - Port A Data Direction Register; 0x00000002 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+DDRA_BIT0:          equ    0                                         ; Data Direction Port A Bit 0
+DDRA_BIT1:          equ    1                                         ; Data Direction Port A Bit 1
+DDRA_BIT2:          equ    2                                         ; Data Direction Port A Bit 2
+DDRA_BIT3:          equ    3                                         ; Data Direction Port A Bit 3
+DDRA_BIT4:          equ    4                                         ; Data Direction Port A Bit 4
+DDRA_BIT5:          equ    5                                         ; Data Direction Port A Bit 5
+DDRA_BIT6:          equ    6                                         ; Data Direction Port A Bit 6
+DDRA_BIT7:          equ    7                                         ; Data Direction Port A Bit 7
+; bit position masks
+mDDRA_BIT0:         equ    %00000001
+mDDRA_BIT1:         equ    %00000010
+mDDRA_BIT2:         equ    %00000100
+mDDRA_BIT3:         equ    %00001000
+mDDRA_BIT4:         equ    %00010000
+mDDRA_BIT5:         equ    %00100000
+mDDRA_BIT6:         equ    %01000000
+mDDRA_BIT7:         equ    %10000000
+
+
+;*** DDRB - Port B Data Direction Register; 0x00000003 ***
+DDRB:               equ    $00000003                                ;*** DDRB - Port B Data Direction Register; 0x00000003 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+DDRB_BIT0:          equ    0                                         ; Data Direction Port B Bit 0
+DDRB_BIT1:          equ    1                                         ; Data Direction Port B Bit 1
+DDRB_BIT2:          equ    2                                         ; Data Direction Port B Bit 2
+DDRB_BIT3:          equ    3                                         ; Data Direction Port B Bit 3
+DDRB_BIT4:          equ    4                                         ; Data Direction Port B Bit 4
+DDRB_BIT5:          equ    5                                         ; Data Direction Port B Bit 5
+DDRB_BIT6:          equ    6                                         ; Data Direction Port B Bit 6
+DDRB_BIT7:          equ    7                                         ; Data Direction Port B Bit 7
+; bit position masks
+mDDRB_BIT0:         equ    %00000001
+mDDRB_BIT1:         equ    %00000010
+mDDRB_BIT2:         equ    %00000100
+mDDRB_BIT3:         equ    %00001000
+mDDRB_BIT4:         equ    %00010000
+mDDRB_BIT5:         equ    %00100000
+mDDRB_BIT6:         equ    %01000000
+mDDRB_BIT7:         equ    %10000000
+
+
+;*** PORTE - Port E Register; 0x00000008 ***
+PORTE:              equ    $00000008                                ;*** PORTE - Port E Register; 0x00000008 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PORTE_BIT0:         equ    0                                         ; Port E Bit 0
+PORTE_BIT1:         equ    1                                         ; Port E Bit 1
+PORTE_BIT2:         equ    2                                         ; Port E Bit 2
+PORTE_BIT3:         equ    3                                         ; Port E Bit 3
+PORTE_BIT4:         equ    4                                         ; Port E Bit 4
+PORTE_BIT5:         equ    5                                         ; Port E Bit 5
+PORTE_BIT6:         equ    6                                         ; Port E Bit 6
+PORTE_BIT7:         equ    7                                         ; Port E Bit 7
+; bit position masks
+mPORTE_BIT0:        equ    %00000001
+mPORTE_BIT1:        equ    %00000010
+mPORTE_BIT2:        equ    %00000100
+mPORTE_BIT3:        equ    %00001000
+mPORTE_BIT4:        equ    %00010000
+mPORTE_BIT5:        equ    %00100000
+mPORTE_BIT6:        equ    %01000000
+mPORTE_BIT7:        equ    %10000000
+
+
+;*** DDRE - Port E Data Direction Register; 0x00000009 ***
+DDRE:               equ    $00000009                                ;*** DDRE - Port E Data Direction Register; 0x00000009 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+DDRE_BIT2:          equ    2                                         ; Data Direction Port E Bit 2
+DDRE_BIT3:          equ    3                                         ; Data Direction Port E Bit 3
+DDRE_BIT4:          equ    4                                         ; Data Direction Port E Bit 4
+DDRE_BIT5:          equ    5                                         ; Data Direction Port E Bit 5
+DDRE_BIT6:          equ    6                                         ; Data Direction Port E Bit 6
+DDRE_BIT7:          equ    7                                         ; Data Direction Port E Bit 7
+; bit position masks
+mDDRE_BIT2:         equ    %00000100
+mDDRE_BIT3:         equ    %00001000
+mDDRE_BIT4:         equ    %00010000
+mDDRE_BIT5:         equ    %00100000
+mDDRE_BIT6:         equ    %01000000
+mDDRE_BIT7:         equ    %10000000
+
+
+;*** PEAR - Port E Assignment Register; 0x0000000A ***
+PEAR:               equ    $0000000A                                ;*** PEAR - Port E Assignment Register; 0x0000000A ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PEAR_RDWE:          equ    2                                         ; Read / Write Enable
+PEAR_LSTRE:         equ    3                                         ; Low Strobe (LSTRB) Enable
+PEAR_NECLK:         equ    4                                         ; No External E Clock
+PEAR_PIPOE:         equ    5                                         ; Pipe Status Signal Output Enable
+PEAR_NOACCE:        equ    7                                         ; CPU No Access Output Enable
+; bit position masks
+mPEAR_RDWE:         equ    %00000100
+mPEAR_LSTRE:        equ    %00001000
+mPEAR_NECLK:        equ    %00010000
+mPEAR_PIPOE:        equ    %00100000
+mPEAR_NOACCE:       equ    %10000000
+
+
+;*** MODE - Mode Register; 0x0000000B ***
+MODE:               equ    $0000000B                                ;*** MODE - Mode Register; 0x0000000B ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+MODE_EME:           equ    0                                         ; Emulate Port E
+MODE_EMK:           equ    1                                         ; Emulate Port K
+MODE_IVIS:          equ    3                                         ; Internal Visibility
+MODE_MODA:          equ    5                                         ; Mode Select Bit A
+MODE_MODB:          equ    6                                         ; Mode Select Bit B
+MODE_MODC:          equ    7                                         ; Mode Select Bit C
+; bit position masks
+mMODE_EME:          equ    %00000001
+mMODE_EMK:          equ    %00000010
+mMODE_IVIS:         equ    %00001000
+mMODE_MODA:         equ    %00100000
+mMODE_MODB:         equ    %01000000
+mMODE_MODC:         equ    %10000000
+
+
+;*** PUCR - Pull-Up Control Register; 0x0000000C ***
+PUCR:               equ    $0000000C                                ;*** PUCR - Pull-Up Control Register; 0x0000000C ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PUCR_PUPAE:         equ    0                                         ; Pull-Up Port A Enable
+PUCR_PUPBE:         equ    1                                         ; Pull-Up Port B Enable
+PUCR_PUPEE:         equ    4                                         ; Pull-Up Port E Enable
+PUCR_PUPKE:         equ    7                                         ; Pull-Up Port K Enable
+; bit position masks
+mPUCR_PUPAE:        equ    %00000001
+mPUCR_PUPBE:        equ    %00000010
+mPUCR_PUPEE:        equ    %00010000
+mPUCR_PUPKE:        equ    %10000000
+
+
+;*** RDRIV - Reduced Drive of I/O Lines; 0x0000000D ***
+RDRIV:              equ    $0000000D                                ;*** RDRIV - Reduced Drive of I/O Lines; 0x0000000D ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+RDRIV_RDPA:         equ    0                                         ; Reduced Drive of Port A
+RDRIV_RDPB:         equ    1                                         ; Reduced Drive of Port B
+RDRIV_RDPE:         equ    4                                         ; Reduced Drive of Port E
+RDRIV_RDPK:         equ    7                                         ; Reduced Drive of Port K
+; bit position masks
+mRDRIV_RDPA:        equ    %00000001
+mRDRIV_RDPB:        equ    %00000010
+mRDRIV_RDPE:        equ    %00010000
+mRDRIV_RDPK:        equ    %10000000
+
+
+;*** EBICTL - External Bus Interface Control; 0x0000000E ***
+EBICTL:             equ    $0000000E                                ;*** EBICTL - External Bus Interface Control; 0x0000000E ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+EBICTL_ESTR:        equ    0                                         ; E Stretches
+; bit position masks
+mEBICTL_ESTR:       equ    %00000001
+
+
+;*** INITRM - Initialization of Internal RAM Position Register; 0x00000010 ***
+INITRM:             equ    $00000010                                ;*** INITRM - Initialization of Internal RAM Position Register; 0x00000010 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+INITRM_RAMHAL:      equ    0                                         ; Internal RAM map alignment
+INITRM_RAM11:       equ    3                                         ; Internal RAM map position Bit 11
+INITRM_RAM12:       equ    4                                         ; Internal RAM map position Bit 12
+INITRM_RAM13:       equ    5                                         ; Internal RAM map position Bit 13
+INITRM_RAM14:       equ    6                                         ; Internal RAM map position Bit 14
+INITRM_RAM15:       equ    7                                         ; Internal RAM map position Bit 15
+; bit position masks
+mINITRM_RAMHAL:     equ    %00000001
+mINITRM_RAM11:      equ    %00001000
+mINITRM_RAM12:      equ    %00010000
+mINITRM_RAM13:      equ    %00100000
+mINITRM_RAM14:      equ    %01000000
+mINITRM_RAM15:      equ    %10000000
+
+
+;*** INITRG - Initialization of Internal Registers Position Register; 0x00000011 ***
+INITRG:             equ    $00000011                                ;*** INITRG - Initialization of Internal Registers Position Register; 0x00000011 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+INITRG_REG11:       equ    3                                         ; Internal Registers Map Position Bit 11
+INITRG_REG12:       equ    4                                         ; Internal Registers Map Position Bit 12
+INITRG_REG13:       equ    5                                         ; Internal Registers Map Position Bit 13
+INITRG_REG14:       equ    6                                         ; Internal Registers Map Position Bit 14
+; bit position masks
+mINITRG_REG11:      equ    %00001000
+mINITRG_REG12:      equ    %00010000
+mINITRG_REG13:      equ    %00100000
+mINITRG_REG14:      equ    %01000000
+
+
+;*** MISC - Miscellaneous System Control Register; 0x00000013 ***
+MISC:               equ    $00000013                                ;*** MISC - Miscellaneous System Control Register; 0x00000013 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+MISC_ROMON:         equ    0                                         ; Enable Flash EEPROM
+MISC_ROMHM:         equ    1                                         ; Flash EEPROM only in second half of memory map
+MISC_EXSTR0:        equ    2                                         ; External Access Stretch Bit 0
+MISC_EXSTR1:        equ    3                                         ; External Access Stretch Bit 1
+; bit position masks
+mMISC_ROMON:        equ    %00000001
+mMISC_ROMHM:        equ    %00000010
+mMISC_EXSTR0:       equ    %00000100
+mMISC_EXSTR1:       equ    %00001000
+
+
+;*** ITCR - Interrupt Test Control Register; 0x00000015 ***
+ITCR:               equ    $00000015                                ;*** ITCR - Interrupt Test Control Register; 0x00000015 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+ITCR_ADR0:          equ    0                                         ; Test register select Bit 0
+ITCR_ADR1:          equ    1                                         ; Test register select Bit 1
+ITCR_ADR2:          equ    2                                         ; Test register select Bit 2
+ITCR_ADR3:          equ    3                                         ; Test register select Bit 3
+ITCR_WRTINT:        equ    4                                         ; Write to the Interrupt Test Registers
+; bit position masks
+mITCR_ADR0:         equ    %00000001
+mITCR_ADR1:         equ    %00000010
+mITCR_ADR2:         equ    %00000100
+mITCR_ADR3:         equ    %00001000
+mITCR_WRTINT:       equ    %00010000
+
+
+;*** ITEST - Interrupt Test Register; 0x00000016 ***
+ITEST:              equ    $00000016                                ;*** ITEST - Interrupt Test Register; 0x00000016 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+ITEST_INT0:         equ    0                                         ; Interrupt Test Register Bit 0
+ITEST_INT2:         equ    1                                         ; Interrupt Test Register Bit 1
+ITEST_INT4:         equ    2                                         ; Interrupt Test Register Bit 2
+ITEST_INT6:         equ    3                                         ; Interrupt Test Register Bit 3
+ITEST_INT8:         equ    4                                         ; Interrupt Test Register Bit 4
+ITEST_INTA:         equ    5                                         ; Interrupt Test Register Bit 5
+ITEST_INTC:         equ    6                                         ; Interrupt Test Register Bit 6
+ITEST_INTE:         equ    7                                         ; Interrupt Test Register Bit 7
+; bit position masks
+mITEST_INT0:        equ    %00000001
+mITEST_INT2:        equ    %00000010
+mITEST_INT4:        equ    %00000100
+mITEST_INT6:        equ    %00001000
+mITEST_INT8:        equ    %00010000
+mITEST_INTA:        equ    %00100000
+mITEST_INTC:        equ    %01000000
+mITEST_INTE:        equ    %10000000
+
+
+;*** VREGCTRL - VREG_3V3 - Control Register; 0x00000019 ***
+VREGCTRL:           equ    $00000019                                ;*** VREGCTRL - VREG_3V3 - Control Register; 0x00000019 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+VREGCTRL_LVIF:      equ    0                                         ; Low Voltage Interrupt Flag
+VREGCTRL_LVIE:      equ    1                                         ; Low Voltage Interrupt Enable Bit
+VREGCTRL_LVDS:      equ    2                                         ; Low Voltage Detect Status Bit
+; bit position masks
+mVREGCTRL_LVIF:     equ    %00000001
+mVREGCTRL_LVIE:     equ    %00000010
+mVREGCTRL_LVDS:     equ    %00000100
+
+
+;*** PARTID - Part ID Register; 0x0000001A ***
+PARTID:             equ    $0000001A                                ;*** PARTID - Part ID Register; 0x0000001A ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PARTID_ID0:         equ    0                                         ; Part ID Register Bit 0
+PARTID_ID1:         equ    1                                         ; Part ID Register Bit 1
+PARTID_ID2:         equ    2                                         ; Part ID Register Bit 2
+PARTID_ID3:         equ    3                                         ; Part ID Register Bit 3
+PARTID_ID4:         equ    4                                         ; Part ID Register Bit 4
+PARTID_ID5:         equ    5                                         ; Part ID Register Bit 5
+PARTID_ID6:         equ    6                                         ; Part ID Register Bit 6
+PARTID_ID7:         equ    7                                         ; Part ID Register Bit 7
+PARTID_ID8:         equ    8                                         ; Part ID Register Bit 8
+PARTID_ID9:         equ    9                                         ; Part ID Register Bit 9
+PARTID_ID10:        equ    10                                        ; Part ID Register Bit 10
+PARTID_ID11:        equ    11                                        ; Part ID Register Bit 11
+PARTID_ID12:        equ    12                                        ; Part ID Register Bit 12
+PARTID_ID13:        equ    13                                        ; Part ID Register Bit 13
+PARTID_ID14:        equ    14                                        ; Part ID Register Bit 14
+PARTID_ID15:        equ    15                                        ; Part ID Register Bit 15
+; bit position masks
+mPARTID_ID0:        equ    %00000001
+mPARTID_ID1:        equ    %00000010
+mPARTID_ID2:        equ    %00000100
+mPARTID_ID3:        equ    %00001000
+mPARTID_ID4:        equ    %00010000
+mPARTID_ID5:        equ    %00100000
+mPARTID_ID6:        equ    %01000000
+mPARTID_ID7:        equ    %10000000
+mPARTID_ID8:        equ    %100000000
+mPARTID_ID9:        equ    %1000000000
+mPARTID_ID10:       equ    %10000000000
+mPARTID_ID11:       equ    %100000000000
+mPARTID_ID12:       equ    %1000000000000
+mPARTID_ID13:       equ    %10000000000000
+mPARTID_ID14:       equ    %100000000000000
+mPARTID_ID15:       equ    %1000000000000000
+
+
+;*** PARTIDH - Part ID Register High; 0x0000001A ***
+PARTIDH:            equ    $0000001A                                ;*** PARTIDH - Part ID Register High; 0x0000001A ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PARTIDH_ID8:        equ    0                                         ; Part ID Register Bit 8
+PARTIDH_ID9:        equ    1                                         ; Part ID Register Bit 9
+PARTIDH_ID10:       equ    2                                         ; Part ID Register Bit 10
+PARTIDH_ID11:       equ    3                                         ; Part ID Register Bit 11
+PARTIDH_ID12:       equ    4                                         ; Part ID Register Bit 12
+PARTIDH_ID13:       equ    5                                         ; Part ID Register Bit 13
+PARTIDH_ID14:       equ    6                                         ; Part ID Register Bit 14
+PARTIDH_ID15:       equ    7                                         ; Part ID Register Bit 15
+; bit position masks
+mPARTIDH_ID8:       equ    %00000001
+mPARTIDH_ID9:       equ    %00000010
+mPARTIDH_ID10:      equ    %00000100
+mPARTIDH_ID11:      equ    %00001000
+mPARTIDH_ID12:      equ    %00010000
+mPARTIDH_ID13:      equ    %00100000
+mPARTIDH_ID14:      equ    %01000000
+mPARTIDH_ID15:      equ    %10000000
+
+
+;*** PARTIDL - Part ID Register Low; 0x0000001B ***
+PARTIDL:            equ    $0000001B                                ;*** PARTIDL - Part ID Register Low; 0x0000001B ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PARTIDL_ID0:        equ    0                                         ; Part ID Register Bit 0
+PARTIDL_ID1:        equ    1                                         ; Part ID Register Bit 1
+PARTIDL_ID2:        equ    2                                         ; Part ID Register Bit 2
+PARTIDL_ID3:        equ    3                                         ; Part ID Register Bit 3
+PARTIDL_ID4:        equ    4                                         ; Part ID Register Bit 4
+PARTIDL_ID5:        equ    5                                         ; Part ID Register Bit 5
+PARTIDL_ID6:        equ    6                                         ; Part ID Register Bit 6
+PARTIDL_ID7:        equ    7                                         ; Part ID Register Bit 7
+; bit position masks
+mPARTIDL_ID0:       equ    %00000001
+mPARTIDL_ID1:       equ    %00000010
+mPARTIDL_ID2:       equ    %00000100
+mPARTIDL_ID3:       equ    %00001000
+mPARTIDL_ID4:       equ    %00010000
+mPARTIDL_ID5:       equ    %00100000
+mPARTIDL_ID6:       equ    %01000000
+mPARTIDL_ID7:       equ    %10000000
+
+
+;*** MEMSIZ0 - Memory Size Register Zero; 0x0000001C ***
+MEMSIZ0:            equ    $0000001C                                ;*** MEMSIZ0 - Memory Size Register Zero; 0x0000001C ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+MEMSIZ0_ram_sw0:    equ    0                                         ; Allocated System RAM Memory Space Bit 0
+MEMSIZ0_ram_sw1:    equ    1                                         ; Allocated System RAM Memory Space Bit 1
+MEMSIZ0_ram_sw2:    equ    2                                         ; Allocated System RAM Memory Space Bit 2
+MEMSIZ0_eep_sw0:    equ    4                                         ; Allocated EEPROM Memory Space Bit 0
+MEMSIZ0_eep_sw1:    equ    5                                         ; Allocated EEPROM Memory Space Bit 1
+MEMSIZ0_reg_sw0:    equ    7                                         ; Allocated System Register Space
+; bit position masks
+mMEMSIZ0_ram_sw0:   equ    %00000001
+mMEMSIZ0_ram_sw1:   equ    %00000010
+mMEMSIZ0_ram_sw2:   equ    %00000100
+mMEMSIZ0_eep_sw0:   equ    %00010000
+mMEMSIZ0_eep_sw1:   equ    %00100000
+mMEMSIZ0_reg_sw0:   equ    %10000000
+
+
+;*** MEMSIZ1 - Memory Size Register One; 0x0000001D ***
+MEMSIZ1:            equ    $0000001D                                ;*** MEMSIZ1 - Memory Size Register One; 0x0000001D ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+MEMSIZ1_pag_sw0:    equ    0                                         ; Allocated Off-Chip Memory Options Bit 0
+MEMSIZ1_pag_sw1:    equ    1                                         ; Allocated Off-Chip Memory Options Bit 1
+MEMSIZ1_rom_sw0:    equ    6                                         ; Allocated Flash EEPROM/ROM Physical Memory Space Bit 0
+MEMSIZ1_rom_sw1:    equ    7                                         ; Allocated Flash EEPROM/ROM Physical Memory Space Bit 1
+; bit position masks
+mMEMSIZ1_pag_sw0:   equ    %00000001
+mMEMSIZ1_pag_sw1:   equ    %00000010
+mMEMSIZ1_rom_sw0:   equ    %01000000
+mMEMSIZ1_rom_sw1:   equ    %10000000
+
+
+;*** INTCR - Interrupt Control Register; 0x0000001E ***
+INTCR:              equ    $0000001E                                ;*** INTCR - Interrupt Control Register; 0x0000001E ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+INTCR_IRQEN:        equ    6                                         ; External IRQ Enable
+INTCR_IRQE:         equ    7                                         ; IRQ Select Edge Sensitive Only
+; bit position masks
+mINTCR_IRQEN:       equ    %01000000
+mINTCR_IRQE:        equ    %10000000
+
+
+;*** HPRIO - Highest Priority I Interrupt; 0x0000001F ***
+HPRIO:              equ    $0000001F                                ;*** HPRIO - Highest Priority I Interrupt; 0x0000001F ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+HPRIO_PSEL1:        equ    1                                         ; Highest Priority I Interrupt Bit 1
+HPRIO_PSEL2:        equ    2                                         ; Highest Priority I Interrupt Bit 2
+HPRIO_PSEL3:        equ    3                                         ; Highest Priority I Interrupt Bit 3
+HPRIO_PSEL4:        equ    4                                         ; Highest Priority I Interrupt Bit 4
+HPRIO_PSEL5:        equ    5                                         ; Highest Priority I Interrupt Bit 5
+HPRIO_PSEL6:        equ    6                                         ; Highest Priority I Interrupt Bit 6
+HPRIO_PSEL7:        equ    7                                         ; Highest Priority I Interrupt Bit 7
+; bit position masks
+mHPRIO_PSEL1:       equ    %00000010
+mHPRIO_PSEL2:       equ    %00000100
+mHPRIO_PSEL3:       equ    %00001000
+mHPRIO_PSEL4:       equ    %00010000
+mHPRIO_PSEL5:       equ    %00100000
+mHPRIO_PSEL6:       equ    %01000000
+mHPRIO_PSEL7:       equ    %10000000
+
+
+;*** DBGC1 - Debug Control Register 1; 0x00000020 ***
+DBGC1:              equ    $00000020                                ;*** DBGC1 - Debug Control Register 1; 0x00000020 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+DBGC1_CAPMOD0:      equ    0                                         ; Capture Mode Field, bit 0
+DBGC1_CAPMOD1:      equ    1                                         ; Capture Mode Field, bit 1
+DBGC1_DBGBRK:       equ    3                                         ; DBG Breakpoint Enable Bit
+DBGC1_BEGIN:        equ    4                                         ; Begin/End Trigger Bit
+DBGC1_TRGSEL:       equ    5                                         ; Trigger Selection Bit
+DBGC1_ARM:          equ    6                                         ; Arm Bit
+DBGC1_DBGEN:        equ    7                                         ; DBG Mode Enable Bit
+; bit position masks
+mDBGC1_CAPMOD0:     equ    %00000001
+mDBGC1_CAPMOD1:     equ    %00000010
+mDBGC1_DBGBRK:      equ    %00001000
+mDBGC1_BEGIN:       equ    %00010000
+mDBGC1_TRGSEL:      equ    %00100000
+mDBGC1_ARM:         equ    %01000000
+mDBGC1_DBGEN:       equ    %10000000
+
+
+;*** DBGSC - Debug Status and Control Register; 0x00000021 ***
+DBGSC:              equ    $00000021                                ;*** DBGSC - Debug Status and Control Register; 0x00000021 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+DBGSC_TRG0:         equ    0                                         ; Trigger Mode Bits, bit 0
+DBGSC_TRG1:         equ    1                                         ; Trigger Mode Bits, bit 1
+DBGSC_TRG2:         equ    2                                         ; Trigger Mode Bits, bit 2
+DBGSC_TRG3:         equ    3                                         ; Trigger Mode Bits, bit 3
+DBGSC_CF:           equ    5                                         ; Comparator C Match Flag
+DBGSC_BF:           equ    6                                         ; Trigger B Match Flag
+DBGSC_AF:           equ    7                                         ; Trigger A Match Flag
+; bit position masks
+mDBGSC_TRG0:        equ    %00000001
+mDBGSC_TRG1:        equ    %00000010
+mDBGSC_TRG2:        equ    %00000100
+mDBGSC_TRG3:        equ    %00001000
+mDBGSC_CF:          equ    %00100000
+mDBGSC_BF:          equ    %01000000
+mDBGSC_AF:          equ    %10000000
+
+
+;*** DBGTB - Debug Trace Buffer Register; 0x00000022 ***
+DBGTB:              equ    $00000022                                ;*** DBGTB - Debug Trace Buffer Register; 0x00000022 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+DBGTB_BIT0:         equ    0                                         ; Trace Buffer Data Bit 0
+DBGTB_BIT1:         equ    1                                         ; Trace Buffer Data Bit 1
+DBGTB_BIT2:         equ    2                                         ; Trace Buffer Data Bit 2
+DBGTB_BIT3:         equ    3                                         ; Trace Buffer Data Bit 3
+DBGTB_BIT4:         equ    4                                         ; Trace Buffer Data Bit 4
+DBGTB_BIT5:         equ    5                                         ; Trace Buffer Data Bit 5
+DBGTB_BIT6:         equ    6                                         ; Trace Buffer Data Bit 6
+DBGTB_BIT7:         equ    7                                         ; Trace Buffer Data Bit 7
+DBGTB_BIT8:         equ    8                                         ; Trace Buffer Data Bit 8
+DBGTB_BIT9:         equ    9                                         ; Trace Buffer Data Bit 9
+DBGTB_BIT10:        equ    10                                        ; Trace Buffer Data Bit 10
+DBGTB_BIT11:        equ    11                                        ; Trace Buffer Data Bit 11
+DBGTB_BIT12:        equ    12                                        ; Trace Buffer Data Bit 12
+DBGTB_BIT13:        equ    13                                        ; Trace Buffer Data Bit 13
+DBGTB_BIT14:        equ    14                                        ; Trace Buffer Data Bit 14
+DBGTB_BIT15:        equ    15                                        ; Trace Buffer Data Bit 15
+; bit position masks
+mDBGTB_BIT0:        equ    %00000001
+mDBGTB_BIT1:        equ    %00000010
+mDBGTB_BIT2:        equ    %00000100
+mDBGTB_BIT3:        equ    %00001000
+mDBGTB_BIT4:        equ    %00010000
+mDBGTB_BIT5:        equ    %00100000
+mDBGTB_BIT6:        equ    %01000000
+mDBGTB_BIT7:        equ    %10000000
+mDBGTB_BIT8:        equ    %100000000
+mDBGTB_BIT9:        equ    %1000000000
+mDBGTB_BIT10:       equ    %10000000000
+mDBGTB_BIT11:       equ    %100000000000
+mDBGTB_BIT12:       equ    %1000000000000
+mDBGTB_BIT13:       equ    %10000000000000
+mDBGTB_BIT14:       equ    %100000000000000
+mDBGTB_BIT15:       equ    %1000000000000000
+
+
+;*** DBGTBH - Debug Trace Buffer Register High; 0x00000022 ***
+DBGTBH:             equ    $00000022                                ;*** DBGTBH - Debug Trace Buffer Register High; 0x00000022 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+DBGTBH_BIT8:        equ    0                                         ; Trace Buffer Data Bit 8
+DBGTBH_BIT9:        equ    1                                         ; Trace Buffer Data Bit 9
+DBGTBH_BIT10:       equ    2                                         ; Trace Buffer Data Bit 10
+DBGTBH_BIT11:       equ    3                                         ; Trace Buffer Data Bit 11
+DBGTBH_BIT12:       equ    4                                         ; Trace Buffer Data Bit 12
+DBGTBH_BIT13:       equ    5                                         ; Trace Buffer Data Bit 13
+DBGTBH_BIT14:       equ    6                                         ; Trace Buffer Data Bit 14
+DBGTBH_BIT15:       equ    7                                         ; Trace Buffer Data Bit 15
+; bit position masks
+mDBGTBH_BIT8:       equ    %00000001
+mDBGTBH_BIT9:       equ    %00000010
+mDBGTBH_BIT10:      equ    %00000100
+mDBGTBH_BIT11:      equ    %00001000
+mDBGTBH_BIT12:      equ    %00010000
+mDBGTBH_BIT13:      equ    %00100000
+mDBGTBH_BIT14:      equ    %01000000
+mDBGTBH_BIT15:      equ    %10000000
+
+
+;*** DBGTBL - Debug Trace Buffer Register Low; 0x00000023 ***
+DBGTBL:             equ    $00000023                                ;*** DBGTBL - Debug Trace Buffer Register Low; 0x00000023 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+DBGTBL_BIT0:        equ    0                                         ; Trace Buffer Data Bit 0
+DBGTBL_BIT1:        equ    1                                         ; Trace Buffer Data Bit 1
+DBGTBL_BIT2:        equ    2                                         ; Trace Buffer Data Bit 2
+DBGTBL_BIT3:        equ    3                                         ; Trace Buffer Data Bit 3
+DBGTBL_BIT4:        equ    4                                         ; Trace Buffer Data Bit 4
+DBGTBL_BIT5:        equ    5                                         ; Trace Buffer Data Bit 5
+DBGTBL_BIT6:        equ    6                                         ; Trace Buffer Data Bit 6
+DBGTBL_BIT7:        equ    7                                         ; Trace Buffer Data Bit 7
+; bit position masks
+mDBGTBL_BIT0:       equ    %00000001
+mDBGTBL_BIT1:       equ    %00000010
+mDBGTBL_BIT2:       equ    %00000100
+mDBGTBL_BIT3:       equ    %00001000
+mDBGTBL_BIT4:       equ    %00010000
+mDBGTBL_BIT5:       equ    %00100000
+mDBGTBL_BIT6:       equ    %01000000
+mDBGTBL_BIT7:       equ    %10000000
+
+
+;*** DBGCNT - Debug Count Register; 0x00000024 ***
+DBGCNT:             equ    $00000024                                ;*** DBGCNT - Debug Count Register; 0x00000024 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+DBGCNT_CNT0:        equ    0                                         ; Count Value, bit 0
+DBGCNT_CNT1:        equ    1                                         ; Count Value, bit 1
+DBGCNT_CNT2:        equ    2                                         ; Count Value, bit 2
+DBGCNT_CNT3:        equ    3                                         ; Count Value, bit 3
+DBGCNT_CNT4:        equ    4                                         ; Count Value, bit 4
+DBGCNT_CNT5:        equ    5                                         ; Count Value, bit 5
+DBGCNT_TBF:         equ    7                                         ; Trace Buffer Full
+; bit position masks
+mDBGCNT_CNT0:       equ    %00000001
+mDBGCNT_CNT1:       equ    %00000010
+mDBGCNT_CNT2:       equ    %00000100
+mDBGCNT_CNT3:       equ    %00001000
+mDBGCNT_CNT4:       equ    %00010000
+mDBGCNT_CNT5:       equ    %00100000
+mDBGCNT_TBF:        equ    %10000000
+
+
+;*** DBGCCX - Debug Comparator C Extended Register; 0x00000025 ***
+DBGCCX:             equ    $00000025                                ;*** DBGCCX - Debug Comparator C Extended Register; 0x00000025 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+DBGCCX_EXTCMP0:     equ    0                                         ; Comparator C Extended Compare Bits, bit 0
+DBGCCX_EXTCMP1:     equ    1                                         ; Comparator C Extended Compare Bits, bit 1
+DBGCCX_EXTCMP2:     equ    2                                         ; Comparator C Extended Compare Bits, bit 2
+DBGCCX_EXTCMP3:     equ    3                                         ; Comparator C Extended Compare Bits, bit 3
+DBGCCX_EXTCMP4:     equ    4                                         ; Comparator C Extended Compare Bits, bit 4
+DBGCCX_EXTCMP5:     equ    5                                         ; Comparator C Extended Compare Bits, bit 5
+DBGCCX_PAGSEL0:     equ    6                                         ; Page Selector Field, bit 0
+DBGCCX_PAGSEL1:     equ    7                                         ; Page Selector Field, bit 1
+; bit position masks
+mDBGCCX_EXTCMP0:    equ    %00000001
+mDBGCCX_EXTCMP1:    equ    %00000010
+mDBGCCX_EXTCMP2:    equ    %00000100
+mDBGCCX_EXTCMP3:    equ    %00001000
+mDBGCCX_EXTCMP4:    equ    %00010000
+mDBGCCX_EXTCMP5:    equ    %00100000
+mDBGCCX_PAGSEL0:    equ    %01000000
+mDBGCCX_PAGSEL1:    equ    %10000000
+
+
+;*** DBGCC - Debug Comparator C Register; 0x00000026 ***
+DBGCC:              equ    $00000026                                ;*** DBGCC - Debug Comparator C Register; 0x00000026 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+DBGCC_BIT0:         equ    0                                         ; Comparator C Compare Bit 0
+DBGCC_BIT1:         equ    1                                         ; Comparator C Compare Bit 1
+DBGCC_BIT2:         equ    2                                         ; Comparator C Compare Bit 2
+DBGCC_BIT3:         equ    3                                         ; Comparator C Compare Bit 3
+DBGCC_BIT4:         equ    4                                         ; Comparator C Compare Bit 4
+DBGCC_BIT5:         equ    5                                         ; Comparator C Compare Bit 5
+DBGCC_BIT6:         equ    6                                         ; Comparator C Compare Bit 6
+DBGCC_BIT7:         equ    7                                         ; Comparator C Compare Bit 7
+DBGCC_BIT8:         equ    8                                         ; Comparator C Compare Bit 8
+DBGCC_BIT9:         equ    9                                         ; Comparator C Compare Bit 9
+DBGCC_BIT10:        equ    10                                        ; Comparator C Compare Bit 10
+DBGCC_BIT11:        equ    11                                        ; Comparator C Compare Bit 11
+DBGCC_BIT12:        equ    12                                        ; Comparator C Compare Bit 12
+DBGCC_BIT13:        equ    13                                        ; Comparator C Compare Bit 13
+DBGCC_BIT14:        equ    14                                        ; Comparator C Compare Bit 14
+DBGCC_BIT15:        equ    15                                        ; Comparator C Compare Bit 15
+; bit position masks
+mDBGCC_BIT0:        equ    %00000001
+mDBGCC_BIT1:        equ    %00000010
+mDBGCC_BIT2:        equ    %00000100
+mDBGCC_BIT3:        equ    %00001000
+mDBGCC_BIT4:        equ    %00010000
+mDBGCC_BIT5:        equ    %00100000
+mDBGCC_BIT6:        equ    %01000000
+mDBGCC_BIT7:        equ    %10000000
+mDBGCC_BIT8:        equ    %100000000
+mDBGCC_BIT9:        equ    %1000000000
+mDBGCC_BIT10:       equ    %10000000000
+mDBGCC_BIT11:       equ    %100000000000
+mDBGCC_BIT12:       equ    %1000000000000
+mDBGCC_BIT13:       equ    %10000000000000
+mDBGCC_BIT14:       equ    %100000000000000
+mDBGCC_BIT15:       equ    %1000000000000000
+
+
+;*** DBGCCH - Debug Comparator C Register High; 0x00000026 ***
+DBGCCH:             equ    $00000026                                ;*** DBGCCH - Debug Comparator C Register High; 0x00000026 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+DBGCCH_BIT8:        equ    0                                         ; Comparator C Compare Bit 8
+DBGCCH_BIT9:        equ    1                                         ; Comparator C Compare Bit 9
+DBGCCH_BIT10:       equ    2                                         ; Comparator C Compare Bit 10
+DBGCCH_BIT11:       equ    3                                         ; Comparator C Compare Bit 11
+DBGCCH_BIT12:       equ    4                                         ; Comparator C Compare Bit 12
+DBGCCH_BIT13:       equ    5                                         ; Comparator C Compare Bit 13
+DBGCCH_BIT14:       equ    6                                         ; Comparator C Compare Bit 14
+DBGCCH_BIT15:       equ    7                                         ; Comparator C Compare Bit 15
+; bit position masks
+mDBGCCH_BIT8:       equ    %00000001
+mDBGCCH_BIT9:       equ    %00000010
+mDBGCCH_BIT10:      equ    %00000100
+mDBGCCH_BIT11:      equ    %00001000
+mDBGCCH_BIT12:      equ    %00010000
+mDBGCCH_BIT13:      equ    %00100000
+mDBGCCH_BIT14:      equ    %01000000
+mDBGCCH_BIT15:      equ    %10000000
+
+
+;*** DBGCCL - Debug Comparator C Register Low; 0x00000027 ***
+DBGCCL:             equ    $00000027                                ;*** DBGCCL - Debug Comparator C Register Low; 0x00000027 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+DBGCCL_BIT0:        equ    0                                         ; Comparator C Compare Bit 0
+DBGCCL_BIT1:        equ    1                                         ; Comparator C Compare Bit 1
+DBGCCL_BIT2:        equ    2                                         ; Comparator C Compare Bit 2
+DBGCCL_BIT3:        equ    3                                         ; Comparator C Compare Bit 3
+DBGCCL_BIT4:        equ    4                                         ; Comparator C Compare Bit 4
+DBGCCL_BIT5:        equ    5                                         ; Comparator C Compare Bit 5
+DBGCCL_BIT6:        equ    6                                         ; Comparator C Compare Bit 6
+DBGCCL_BIT7:        equ    7                                         ; Comparator C Compare Bit 7
+; bit position masks
+mDBGCCL_BIT0:       equ    %00000001
+mDBGCCL_BIT1:       equ    %00000010
+mDBGCCL_BIT2:       equ    %00000100
+mDBGCCL_BIT3:       equ    %00001000
+mDBGCCL_BIT4:       equ    %00010000
+mDBGCCL_BIT5:       equ    %00100000
+mDBGCCL_BIT6:       equ    %01000000
+mDBGCCL_BIT7:       equ    %10000000
+
+
+;*** DBGC2 - Debug Control Register 2; 0x00000028 ***
+DBGC2:              equ    $00000028                                ;*** DBGC2 - Debug Control Register 2; 0x00000028 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+DBGC2_RWC:          equ    0                                         ; Read/Write Comparator C Value Bit
+DBGC2_RWCEN:        equ    1                                         ; Read/Write Comparator C Enable Bit
+DBGC2_TAGC:         equ    2                                         ; Comparator C Tag Select
+DBGC2_BKCEN:        equ    3                                         ; Breakpoint Comparator C Enable Bit
+DBGC2_TAGAB:        equ    4                                         ; Comparator A/B Tag Select
+DBGC2_BDM:          equ    5                                         ; Background Debug Mode Enable
+DBGC2_FULL:         equ    6                                         ; Full Breakpoint Mode Enable
+DBGC2_BKABEN:       equ    7                                         ; Breakpoint Using Comparator A and B Enable
+; bit position masks
+mDBGC2_RWC:         equ    %00000001
+mDBGC2_RWCEN:       equ    %00000010
+mDBGC2_TAGC:        equ    %00000100
+mDBGC2_BKCEN:       equ    %00001000
+mDBGC2_TAGAB:       equ    %00010000
+mDBGC2_BDM:         equ    %00100000
+mDBGC2_FULL:        equ    %01000000
+mDBGC2_BKABEN:      equ    %10000000
+
+
+;*** DBGC3 - Debug Control Register 3; 0x00000029 ***
+DBGC3:              equ    $00000029                                ;*** DBGC3 - Debug Control Register 3; 0x00000029 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+DBGC3_RWB:          equ    0                                         ; Read/Write Comparator B Value Bit
+DBGC3_RWBEN:        equ    1                                         ; Read/Write Comparator B Enable Bit
+DBGC3_RWA:          equ    2                                         ; Read/Write Comparator A Value Bit
+DBGC3_RWAEN:        equ    3                                         ; Read/Write Comparator A Enable Bit
+DBGC3_BKBMBL:       equ    4                                         ; Breakpoint Mask Low Byte for Second Address
+DBGC3_BKBMBH:       equ    5                                         ; Breakpoint Mask High Byte for Second Address
+DBGC3_BKAMBL:       equ    6                                         ; Breakpoint Mask Low Byte for First Address
+DBGC3_BKAMBH:       equ    7                                         ; Breakpoint Mask High Byte for First Address
+; bit position masks
+mDBGC3_RWB:         equ    %00000001
+mDBGC3_RWBEN:       equ    %00000010
+mDBGC3_RWA:         equ    %00000100
+mDBGC3_RWAEN:       equ    %00001000
+mDBGC3_BKBMBL:      equ    %00010000
+mDBGC3_BKBMBH:      equ    %00100000
+mDBGC3_BKAMBL:      equ    %01000000
+mDBGC3_BKAMBH:      equ    %10000000
+
+
+;*** DBGCAX - Debug Comparator A Extended Register; 0x0000002A ***
+DBGCAX:             equ    $0000002A                                ;*** DBGCAX - Debug Comparator A Extended Register; 0x0000002A ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+DBGCAX_EXTCMP0:     equ    0                                         ; Comparator A Extended Compare Bits, bit 0
+DBGCAX_EXTCMP1:     equ    1                                         ; Comparator A Extended Compare Bits, bit 1
+DBGCAX_EXTCMP2:     equ    2                                         ; Comparator A Extended Compare Bits, bit 2
+DBGCAX_EXTCMP3:     equ    3                                         ; Comparator A Extended Compare Bits, bit 3
+DBGCAX_EXTCMP4:     equ    4                                         ; Comparator A Extended Compare Bits, bit 4
+DBGCAX_EXTCMP5:     equ    5                                         ; Comparator A Extended Compare Bits, bit 5
+DBGCAX_PAGSEL0:     equ    6                                         ; Page Selector Field, bit 0
+DBGCAX_PAGSEL1:     equ    7                                         ; Page Selector Field, bit 1
+; bit position masks
+mDBGCAX_EXTCMP0:    equ    %00000001
+mDBGCAX_EXTCMP1:    equ    %00000010
+mDBGCAX_EXTCMP2:    equ    %00000100
+mDBGCAX_EXTCMP3:    equ    %00001000
+mDBGCAX_EXTCMP4:    equ    %00010000
+mDBGCAX_EXTCMP5:    equ    %00100000
+mDBGCAX_PAGSEL0:    equ    %01000000
+mDBGCAX_PAGSEL1:    equ    %10000000
+
+
+;*** DBGCA - Debug Comparator A Register; 0x0000002B ***
+DBGCA:              equ    $0000002B                                ;*** DBGCA - Debug Comparator A Register; 0x0000002B ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+DBGCA_BIT0:         equ    0                                         ; Comparator A Compare Bit 0
+DBGCA_BIT1:         equ    1                                         ; Comparator A Compare Bit 1
+DBGCA_BIT2:         equ    2                                         ; Comparator A Compare Bit 2
+DBGCA_BIT3:         equ    3                                         ; Comparator A Compare Bit 3
+DBGCA_BIT4:         equ    4                                         ; Comparator A Compare Bit 4
+DBGCA_BIT5:         equ    5                                         ; Comparator A Compare Bit 5
+DBGCA_BIT6:         equ    6                                         ; Comparator A Compare Bit 6
+DBGCA_BIT7:         equ    7                                         ; Comparator A Compare Bit 7
+DBGCA_BIT8:         equ    8                                         ; Comparator A Compare Bit 8
+DBGCA_BIT9:         equ    9                                         ; Comparator A Compare Bit 9
+DBGCA_BIT10:        equ    10                                        ; Comparator A Compare Bit 10
+DBGCA_BIT11:        equ    11                                        ; Comparator A Compare Bit 11
+DBGCA_BIT12:        equ    12                                        ; Comparator A Compare Bit 12
+DBGCA_BIT13:        equ    13                                        ; Comparator A Compare Bit 13
+DBGCA_BIT14:        equ    14                                        ; Comparator A Compare Bit 14
+DBGCA_BIT15:        equ    15                                        ; Comparator A Compare Bit 15
+; bit position masks
+mDBGCA_BIT0:        equ    %00000001
+mDBGCA_BIT1:        equ    %00000010
+mDBGCA_BIT2:        equ    %00000100
+mDBGCA_BIT3:        equ    %00001000
+mDBGCA_BIT4:        equ    %00010000
+mDBGCA_BIT5:        equ    %00100000
+mDBGCA_BIT6:        equ    %01000000
+mDBGCA_BIT7:        equ    %10000000
+mDBGCA_BIT8:        equ    %100000000
+mDBGCA_BIT9:        equ    %1000000000
+mDBGCA_BIT10:       equ    %10000000000
+mDBGCA_BIT11:       equ    %100000000000
+mDBGCA_BIT12:       equ    %1000000000000
+mDBGCA_BIT13:       equ    %10000000000000
+mDBGCA_BIT14:       equ    %100000000000000
+mDBGCA_BIT15:       equ    %1000000000000000
+
+
+;*** DBGCAH - Debug Comparator A Register High; 0x0000002B ***
+DBGCAH:             equ    $0000002B                                ;*** DBGCAH - Debug Comparator A Register High; 0x0000002B ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+DBGCAH_BIT8:        equ    0                                         ; Comparator A Compare Bit 8
+DBGCAH_BIT9:        equ    1                                         ; Comparator A Compare Bit 9
+DBGCAH_BIT10:       equ    2                                         ; Comparator A Compare Bit 10
+DBGCAH_BIT11:       equ    3                                         ; Comparator A Compare Bit 11
+DBGCAH_BIT12:       equ    4                                         ; Comparator A Compare Bit 12
+DBGCAH_BIT13:       equ    5                                         ; Comparator A Compare Bit 13
+DBGCAH_BIT14:       equ    6                                         ; Comparator A Compare Bit 14
+DBGCAH_BIT15:       equ    7                                         ; Comparator A Compare Bit 15
+; bit position masks
+mDBGCAH_BIT8:       equ    %00000001
+mDBGCAH_BIT9:       equ    %00000010
+mDBGCAH_BIT10:      equ    %00000100
+mDBGCAH_BIT11:      equ    %00001000
+mDBGCAH_BIT12:      equ    %00010000
+mDBGCAH_BIT13:      equ    %00100000
+mDBGCAH_BIT14:      equ    %01000000
+mDBGCAH_BIT15:      equ    %10000000
+
+
+;*** DBGCAL - Debug Comparator A Register Low; 0x0000002C ***
+DBGCAL:             equ    $0000002C                                ;*** DBGCAL - Debug Comparator A Register Low; 0x0000002C ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+DBGCAL_BIT0:        equ    0                                         ; Comparator A Compare Bit 0
+DBGCAL_BIT1:        equ    1                                         ; Comparator A Compare Bit 1
+DBGCAL_BIT2:        equ    2                                         ; Comparator A Compare Bit 2
+DBGCAL_BIT3:        equ    3                                         ; Comparator A Compare Bit 3
+DBGCAL_BIT4:        equ    4                                         ; Comparator A Compare Bit 4
+DBGCAL_BIT5:        equ    5                                         ; Comparator A Compare Bit 5
+DBGCAL_BIT6:        equ    6                                         ; Comparator A Compare Bit 6
+DBGCAL_BIT7:        equ    7                                         ; Comparator A Compare Bit 7
+; bit position masks
+mDBGCAL_BIT0:       equ    %00000001
+mDBGCAL_BIT1:       equ    %00000010
+mDBGCAL_BIT2:       equ    %00000100
+mDBGCAL_BIT3:       equ    %00001000
+mDBGCAL_BIT4:       equ    %00010000
+mDBGCAL_BIT5:       equ    %00100000
+mDBGCAL_BIT6:       equ    %01000000
+mDBGCAL_BIT7:       equ    %10000000
+
+
+;*** DBGCBX - Debug Comparator B Extended Register; 0x0000002D ***
+DBGCBX:             equ    $0000002D                                ;*** DBGCBX - Debug Comparator B Extended Register; 0x0000002D ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+DBGCBX_EXTCMP0:     equ    0                                         ; Comparator B Extended Compare Bits, bit 0
+DBGCBX_EXTCMP1:     equ    1                                         ; Comparator B Extended Compare Bits, bit 1
+DBGCBX_EXTCMP2:     equ    2                                         ; Comparator B Extended Compare Bits, bit 2
+DBGCBX_EXTCMP3:     equ    3                                         ; Comparator B Extended Compare Bits, bit 3
+DBGCBX_EXTCMP4:     equ    4                                         ; Comparator B Extended Compare Bits, bit 4
+DBGCBX_EXTCMP5:     equ    5                                         ; Comparator B Extended Compare Bits, bit 5
+DBGCBX_PAGSEL0:     equ    6                                         ; Page Selector Field, bit 0
+DBGCBX_PAGSEL1:     equ    7                                         ; Page Selector Field, bit 1
+; bit position masks
+mDBGCBX_EXTCMP0:    equ    %00000001
+mDBGCBX_EXTCMP1:    equ    %00000010
+mDBGCBX_EXTCMP2:    equ    %00000100
+mDBGCBX_EXTCMP3:    equ    %00001000
+mDBGCBX_EXTCMP4:    equ    %00010000
+mDBGCBX_EXTCMP5:    equ    %00100000
+mDBGCBX_PAGSEL0:    equ    %01000000
+mDBGCBX_PAGSEL1:    equ    %10000000
+
+
+;*** DBGCB - Debug Comparator B Register; 0x0000002E ***
+DBGCB:              equ    $0000002E                                ;*** DBGCB - Debug Comparator B Register; 0x0000002E ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+DBGCB_BIT0:         equ    0                                         ; Comparator B High Compare Bit 0
+DBGCB_BIT1:         equ    1                                         ; Comparator B High Compare Bit 1
+DBGCB_BIT2:         equ    2                                         ; Comparator B High Compare Bit 2
+DBGCB_BIT3:         equ    3                                         ; Comparator B High Compare Bit 3
+DBGCB_BIT4:         equ    4                                         ; Comparator B High Compare Bit 4
+DBGCB_BIT5:         equ    5                                         ; Comparator B High Compare Bit 5
+DBGCB_BIT6:         equ    6                                         ; Comparator B High Compare Bit 6
+DBGCB_BIT7:         equ    7                                         ; Comparator B High Compare Bit 7
+DBGCB_BIT8:         equ    8                                         ; Comparator B High Compare Bit 8
+DBGCB_BIT9:         equ    9                                         ; Comparator B High Compare Bit 9
+DBGCB_BIT10:        equ    10                                        ; Comparator B High Compare Bit 10
+DBGCB_BIT11:        equ    11                                        ; Comparator B High Compare Bit 11
+DBGCB_BIT12:        equ    12                                        ; Comparator B High Compare Bit 12
+DBGCB_BIT13:        equ    13                                        ; Comparator B High Compare Bit 13
+DBGCB_BIT14:        equ    14                                        ; Comparator B High Compare Bit 14
+DBGCB_BIT15:        equ    15                                        ; Comparator B High Compare Bit 15
+; bit position masks
+mDBGCB_BIT0:        equ    %00000001
+mDBGCB_BIT1:        equ    %00000010
+mDBGCB_BIT2:        equ    %00000100
+mDBGCB_BIT3:        equ    %00001000
+mDBGCB_BIT4:        equ    %00010000
+mDBGCB_BIT5:        equ    %00100000
+mDBGCB_BIT6:        equ    %01000000
+mDBGCB_BIT7:        equ    %10000000
+mDBGCB_BIT8:        equ    %100000000
+mDBGCB_BIT9:        equ    %1000000000
+mDBGCB_BIT10:       equ    %10000000000
+mDBGCB_BIT11:       equ    %100000000000
+mDBGCB_BIT12:       equ    %1000000000000
+mDBGCB_BIT13:       equ    %10000000000000
+mDBGCB_BIT14:       equ    %100000000000000
+mDBGCB_BIT15:       equ    %1000000000000000
+
+
+;*** DBGCBH - Debug Comparator B Register High; 0x0000002E ***
+DBGCBH:             equ    $0000002E                                ;*** DBGCBH - Debug Comparator B Register High; 0x0000002E ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+DBGCBH_BIT8:        equ    0                                         ; Comparator B High Compare Bit 8
+DBGCBH_BIT9:        equ    1                                         ; Comparator B High Compare Bit 9
+DBGCBH_BIT10:       equ    2                                         ; Comparator B High Compare Bit 10
+DBGCBH_BIT11:       equ    3                                         ; Comparator B High Compare Bit 11
+DBGCBH_BIT12:       equ    4                                         ; Comparator B High Compare Bit 12
+DBGCBH_BIT13:       equ    5                                         ; Comparator B High Compare Bit 13
+DBGCBH_BIT14:       equ    6                                         ; Comparator B High Compare Bit 14
+DBGCBH_BIT15:       equ    7                                         ; Comparator B High Compare Bit 15
+; bit position masks
+mDBGCBH_BIT8:       equ    %00000001
+mDBGCBH_BIT9:       equ    %00000010
+mDBGCBH_BIT10:      equ    %00000100
+mDBGCBH_BIT11:      equ    %00001000
+mDBGCBH_BIT12:      equ    %00010000
+mDBGCBH_BIT13:      equ    %00100000
+mDBGCBH_BIT14:      equ    %01000000
+mDBGCBH_BIT15:      equ    %10000000
+
+
+;*** DBGCBL - Debug Comparator B Register Low; 0x0000002F ***
+DBGCBL:             equ    $0000002F                                ;*** DBGCBL - Debug Comparator B Register Low; 0x0000002F ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+DBGCBL_BIT0:        equ    0                                         ; Comparator B High Compare Bit 0
+DBGCBL_BIT1:        equ    1                                         ; Comparator B High Compare Bit 1
+DBGCBL_BIT2:        equ    2                                         ; Comparator B High Compare Bit 2
+DBGCBL_BIT3:        equ    3                                         ; Comparator B High Compare Bit 3
+DBGCBL_BIT4:        equ    4                                         ; Comparator B High Compare Bit 4
+DBGCBL_BIT5:        equ    5                                         ; Comparator B High Compare Bit 5
+DBGCBL_BIT6:        equ    6                                         ; Comparator B High Compare Bit 6
+DBGCBL_BIT7:        equ    7                                         ; Comparator B High Compare Bit 7
+; bit position masks
+mDBGCBL_BIT0:       equ    %00000001
+mDBGCBL_BIT1:       equ    %00000010
+mDBGCBL_BIT2:       equ    %00000100
+mDBGCBL_BIT3:       equ    %00001000
+mDBGCBL_BIT4:       equ    %00010000
+mDBGCBL_BIT5:       equ    %00100000
+mDBGCBL_BIT6:       equ    %01000000
+mDBGCBL_BIT7:       equ    %10000000
+
+
+;*** PPAGE - Page Index Register; 0x00000030 ***
+PPAGE:              equ    $00000030                                ;*** PPAGE - Page Index Register; 0x00000030 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PPAGE_PIX0:         equ    0                                         ; Page Index Register Bit 0
+PPAGE_PIX1:         equ    1                                         ; Page Index Register Bit 1
+PPAGE_PIX2:         equ    2                                         ; Page Index Register Bit 2
+PPAGE_PIX3:         equ    3                                         ; Page Index Register Bit 3
+PPAGE_PIX4:         equ    4                                         ; Page Index Register Bit 4
+PPAGE_PIX5:         equ    5                                         ; Page Index Register Bit 5
+; bit position masks
+mPPAGE_PIX0:        equ    %00000001
+mPPAGE_PIX1:        equ    %00000010
+mPPAGE_PIX2:        equ    %00000100
+mPPAGE_PIX3:        equ    %00001000
+mPPAGE_PIX4:        equ    %00010000
+mPPAGE_PIX5:        equ    %00100000
+
+
+;*** PORTK - Port K Data Register; 0x00000032 ***
+PORTK:              equ    $00000032                                ;*** PORTK - Port K Data Register; 0x00000032 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PORTK_BIT0:         equ    0                                         ; Port K Bit 0
+PORTK_BIT1:         equ    1                                         ; Port K Bit 1
+PORTK_BIT2:         equ    2                                         ; Port K Bit 2
+PORTK_BIT3:         equ    3                                         ; Port K Bit 3
+PORTK_BIT4:         equ    4                                         ; Port K Bit 4
+PORTK_BIT5:         equ    5                                         ; Port K Bit 5
+PORTK_BIT6:         equ    6                                         ; Port K Bit 6
+PORTK_BIT7:         equ    7                                         ; Port K Bit 7
+; bit position masks
+mPORTK_BIT0:        equ    %00000001
+mPORTK_BIT1:        equ    %00000010
+mPORTK_BIT2:        equ    %00000100
+mPORTK_BIT3:        equ    %00001000
+mPORTK_BIT4:        equ    %00010000
+mPORTK_BIT5:        equ    %00100000
+mPORTK_BIT6:        equ    %01000000
+mPORTK_BIT7:        equ    %10000000
+
+
+;*** DDRK - Port K Data Direction Register; 0x00000033 ***
+DDRK:               equ    $00000033                                ;*** DDRK - Port K Data Direction Register; 0x00000033 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+DDRK_BIT0:          equ    0                                         ; Port K Data Direction Bit 0
+DDRK_BIT1:          equ    1                                         ; Port K Data Direction Bit 1
+DDRK_BIT2:          equ    2                                         ; Port K Data Direction Bit 2
+DDRK_BIT3:          equ    3                                         ; Port K Data Direction Bit 3
+DDRK_BIT4:          equ    4                                         ; Port K Data Direction Bit 4
+DDRK_BIT5:          equ    5                                         ; Port K Data Direction Bit 5
+DDRK_BIT6:          equ    6                                         ; Port K Data Direction Bit 6
+DDRK_BIT7:          equ    7                                         ; Port K Data Direction Bit 7
+; bit position masks
+mDDRK_BIT0:         equ    %00000001
+mDDRK_BIT1:         equ    %00000010
+mDDRK_BIT2:         equ    %00000100
+mDDRK_BIT3:         equ    %00001000
+mDDRK_BIT4:         equ    %00010000
+mDDRK_BIT5:         equ    %00100000
+mDDRK_BIT6:         equ    %01000000
+mDDRK_BIT7:         equ    %10000000
+
+
+;*** SYNR - CRG Synthesizer Register; 0x00000034 ***
+SYNR:               equ    $00000034                                ;*** SYNR - CRG Synthesizer Register; 0x00000034 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+SYNR_SYN0:          equ    0                                         ; CRG Synthesizer Bit 0
+SYNR_SYN1:          equ    1                                         ; CRG Synthesizer Bit 1
+SYNR_SYN2:          equ    2                                         ; CRG Synthesizer Bit 2
+SYNR_SYN3:          equ    3                                         ; CRG Synthesizer Bit 3
+SYNR_SYN4:          equ    4                                         ; CRG Synthesizer Bit 4
+SYNR_SYN5:          equ    5                                         ; CRG Synthesizer Bit 5
+; bit position masks
+mSYNR_SYN0:         equ    %00000001
+mSYNR_SYN1:         equ    %00000010
+mSYNR_SYN2:         equ    %00000100
+mSYNR_SYN3:         equ    %00001000
+mSYNR_SYN4:         equ    %00010000
+mSYNR_SYN5:         equ    %00100000
+
+
+;*** REFDV - CRG Reference Divider Register; 0x00000035 ***
+REFDV:              equ    $00000035                                ;*** REFDV - CRG Reference Divider Register; 0x00000035 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+REFDV_REFDV0:       equ    0                                         ; CRG Reference Divider Bit 0
+REFDV_REFDV1:       equ    1                                         ; CRG Reference Divider Bit 1
+REFDV_REFDV2:       equ    2                                         ; CRG Reference Divider Bit 2
+REFDV_REFDV3:       equ    3                                         ; CRG Reference Divider Bit 3
+; bit position masks
+mREFDV_REFDV0:      equ    %00000001
+mREFDV_REFDV1:      equ    %00000010
+mREFDV_REFDV2:      equ    %00000100
+mREFDV_REFDV3:      equ    %00001000
+
+
+;*** CRGFLG - CRG Flags Register; 0x00000037 ***
+CRGFLG:             equ    $00000037                                ;*** CRGFLG - CRG Flags Register; 0x00000037 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+CRGFLG_SCM:         equ    0                                         ; Self-clock mode Status
+CRGFLG_SCMIF:       equ    1                                         ; Self-clock mode Interrupt Flag
+CRGFLG_TRACK:       equ    2                                         ; Track Status
+CRGFLG_LOCK:        equ    3                                         ; Lock Status
+CRGFLG_LOCKIF:      equ    4                                         ; PLL Lock Interrupt Flag
+CRGFLG_LVRF:        equ    5                                         ; Low Voltage Reset Flag
+CRGFLG_PORF:        equ    6                                         ; Power on Reset Flag
+CRGFLG_RTIF:        equ    7                                         ; Real Time Interrupt Flag
+; bit position masks
+mCRGFLG_SCM:        equ    %00000001
+mCRGFLG_SCMIF:      equ    %00000010
+mCRGFLG_TRACK:      equ    %00000100
+mCRGFLG_LOCK:       equ    %00001000
+mCRGFLG_LOCKIF:     equ    %00010000
+mCRGFLG_LVRF:       equ    %00100000
+mCRGFLG_PORF:       equ    %01000000
+mCRGFLG_RTIF:       equ    %10000000
+
+
+;*** CRGINT - CRG Interrupt Enable Register; 0x00000038 ***
+CRGINT:             equ    $00000038                                ;*** CRGINT - CRG Interrupt Enable Register; 0x00000038 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+CRGINT_SCMIE:       equ    1                                         ; Self-clock mode Interrupt Enable
+CRGINT_LOCKIE:      equ    4                                         ; Lock Interrupt Enable
+CRGINT_RTIE:        equ    7                                         ; Real Time Interrupt Enable
+; bit position masks
+mCRGINT_SCMIE:      equ    %00000010
+mCRGINT_LOCKIE:     equ    %00010000
+mCRGINT_RTIE:       equ    %10000000
+
+
+;*** CLKSEL - CRG Clock Select Register; 0x00000039 ***
+CLKSEL:             equ    $00000039                                ;*** CLKSEL - CRG Clock Select Register; 0x00000039 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+CLKSEL_COPWAI:      equ    0                                         ; COP stops in WAIT mode
+CLKSEL_RTIWAI:      equ    1                                         ; RTI stops in WAIT mode
+CLKSEL_CWAI:        equ    2                                         ; CLK24 and CLK23 stop in WAIT mode
+CLKSEL_PLLWAI:      equ    3                                         ; PLL stops in WAIT mode
+CLKSEL_ROAWAI:      equ    4                                         ; Reduced Oscillator Amplitude in WAIT mode
+CLKSEL_SYSWAI:      equ    5                                         ; System clocks stop in WAIT mode
+CLKSEL_PSTP:        equ    6                                         ; Pseudo Stop
+CLKSEL_PLLSEL:      equ    7                                         ; PLL selected for system clock
+; bit position masks
+mCLKSEL_COPWAI:     equ    %00000001
+mCLKSEL_RTIWAI:     equ    %00000010
+mCLKSEL_CWAI:       equ    %00000100
+mCLKSEL_PLLWAI:     equ    %00001000
+mCLKSEL_ROAWAI:     equ    %00010000
+mCLKSEL_SYSWAI:     equ    %00100000
+mCLKSEL_PSTP:       equ    %01000000
+mCLKSEL_PLLSEL:     equ    %10000000
+
+
+;*** PLLCTL - CRG PLL Control Register; 0x0000003A ***
+PLLCTL:             equ    $0000003A                                ;*** PLLCTL - CRG PLL Control Register; 0x0000003A ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PLLCTL_SCME:        equ    0                                         ; Self-clock mode enable
+PLLCTL_PCE:         equ    1                                         ; COP Enable during Pseudo Stop Bit
+PLLCTL_PRE:         equ    2                                         ; RTI Enable during Pseudo Stop Bit
+PLLCTL_ACQ:         equ    4                                         ; Acquisition
+PLLCTL_AUTO:        equ    5                                         ; Automatic Bandwidth Control
+PLLCTL_PLLON:       equ    6                                         ; Phase Lock Loop On
+PLLCTL_CME:         equ    7                                         ; Clock Monitor Enable
+; bit position masks
+mPLLCTL_SCME:       equ    %00000001
+mPLLCTL_PCE:        equ    %00000010
+mPLLCTL_PRE:        equ    %00000100
+mPLLCTL_ACQ:        equ    %00010000
+mPLLCTL_AUTO:       equ    %00100000
+mPLLCTL_PLLON:      equ    %01000000
+mPLLCTL_CME:        equ    %10000000
+
+
+;*** RTICTL - CRG RTI Control Register; 0x0000003B ***
+RTICTL:             equ    $0000003B                                ;*** RTICTL - CRG RTI Control Register; 0x0000003B ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+RTICTL_RTR0:        equ    0                                         ; Real Time Interrupt Modulus Counter Select Bit 0
+RTICTL_RTR1:        equ    1                                         ; Real Time Interrupt Modulus Counter Select Bit 1
+RTICTL_RTR2:        equ    2                                         ; Real Time Interrupt Modulus Counter Select Bit 2
+RTICTL_RTR3:        equ    3                                         ; Real Time Interrupt Modulus Counter Select Bit 3
+RTICTL_RTR4:        equ    4                                         ; Real Time Interrupt Prescale Rate Select Bit 4
+RTICTL_RTR5:        equ    5                                         ; Real Time Interrupt Prescale Rate Select Bit 5
+RTICTL_RTR6:        equ    6                                         ; Real Time Interrupt Prescale Rate Select Bit 6
+; bit position masks
+mRTICTL_RTR0:       equ    %00000001
+mRTICTL_RTR1:       equ    %00000010
+mRTICTL_RTR2:       equ    %00000100
+mRTICTL_RTR3:       equ    %00001000
+mRTICTL_RTR4:       equ    %00010000
+mRTICTL_RTR5:       equ    %00100000
+mRTICTL_RTR6:       equ    %01000000
+
+
+;*** COPCTL - CRG COP Control Register; 0x0000003C ***
+COPCTL:             equ    $0000003C                                ;*** COPCTL - CRG COP Control Register; 0x0000003C ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+COPCTL_CR0:         equ    0                                         ; COP Watchdog Timer Rate select Bit 0
+COPCTL_CR1:         equ    1                                         ; COP Watchdog Timer Rate select Bit 1
+COPCTL_CR2:         equ    2                                         ; COP Watchdog Timer Rate select Bit 2
+COPCTL_RSBCK:       equ    6                                         ; COP and RTI stop in Active BDM mode Bit
+COPCTL_WCOP:        equ    7                                         ; Window COP mode
+; bit position masks
+mCOPCTL_CR0:        equ    %00000001
+mCOPCTL_CR1:        equ    %00000010
+mCOPCTL_CR2:        equ    %00000100
+mCOPCTL_RSBCK:      equ    %01000000
+mCOPCTL_WCOP:       equ    %10000000
+
+
+;*** ARMCOP - CRG COP Timer Arm/Reset Register; 0x0000003F ***
+ARMCOP:             equ    $0000003F                                ;*** ARMCOP - CRG COP Timer Arm/Reset Register; 0x0000003F ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+ARMCOP_BIT0:        equ    0                                         ; CRG COP Timer Arm/Reset Bit 0
+ARMCOP_BIT1:        equ    1                                         ; CRG COP Timer Arm/Reset Bit 1
+ARMCOP_BIT2:        equ    2                                         ; CRG COP Timer Arm/Reset Bit 2
+ARMCOP_BIT3:        equ    3                                         ; CRG COP Timer Arm/Reset Bit 3
+ARMCOP_BIT4:        equ    4                                         ; CRG COP Timer Arm/Reset Bit 4
+ARMCOP_BIT5:        equ    5                                         ; CRG COP Timer Arm/Reset Bit 5
+ARMCOP_BIT6:        equ    6                                         ; CRG COP Timer Arm/Reset Bit 6
+ARMCOP_BIT7:        equ    7                                         ; CRG COP Timer Arm/Reset Bit 7
+; bit position masks
+mARMCOP_BIT0:       equ    %00000001
+mARMCOP_BIT1:       equ    %00000010
+mARMCOP_BIT2:       equ    %00000100
+mARMCOP_BIT3:       equ    %00001000
+mARMCOP_BIT4:       equ    %00010000
+mARMCOP_BIT5:       equ    %00100000
+mARMCOP_BIT6:       equ    %01000000
+mARMCOP_BIT7:       equ    %10000000
+
+
+;*** TIM0_TIOS - TIM0 Timer Input Capture/Output Compare Select; 0x00000040 ***
+TIM0_TIOS:          equ    $00000040                                ;*** TIM0_TIOS - TIM0 Timer Input Capture/Output Compare Select; 0x00000040 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+TIM0_TIOS_IOS4:     equ    4                                         ; Input Capture or Output Compare Channel Configuration Bit 4
+TIM0_TIOS_IOS5:     equ    5                                         ; Input Capture or Output Compare Channel Configuration Bit 5
+TIM0_TIOS_IOS6:     equ    6                                         ; Input Capture or Output Compare Channel Configuration Bit 6
+TIM0_TIOS_IOS7:     equ    7                                         ; Input Capture or Output Compare Channel Configuration Bit 7
+; bit position masks
+mTIM0_TIOS_IOS4:    equ    %00010000
+mTIM0_TIOS_IOS5:    equ    %00100000
+mTIM0_TIOS_IOS6:    equ    %01000000
+mTIM0_TIOS_IOS7:    equ    %10000000
+
+
+;*** TIM0_CFORC - TIM0 Timer Compare Force Register; 0x00000041 ***
+TIM0_CFORC:         equ    $00000041                                ;*** TIM0_CFORC - TIM0 Timer Compare Force Register; 0x00000041 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+TIM0_CFORC_FOC4:    equ    4                                         ; Force Output Compare Action for Channel 4
+TIM0_CFORC_FOC5:    equ    5                                         ; Force Output Compare Action for Channel 5
+TIM0_CFORC_FOC6:    equ    6                                         ; Force Output Compare Action for Channel 6
+TIM0_CFORC_FOC7:    equ    7                                         ; Force Output Compare Action for Channel 7
+; bit position masks
+mTIM0_CFORC_FOC4:   equ    %00010000
+mTIM0_CFORC_FOC5:   equ    %00100000
+mTIM0_CFORC_FOC6:   equ    %01000000
+mTIM0_CFORC_FOC7:   equ    %10000000
+
+
+;*** TIM0_OC7M - TIM0 Output Compare 7 Mask Register; 0x00000042 ***
+TIM0_OC7M:          equ    $00000042                                ;*** TIM0_OC7M - TIM0 Output Compare 7 Mask Register; 0x00000042 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+TIM0_OC7M_OC7M4:    equ    4                                         ; Output Compare 7 Mask Bit 4
+TIM0_OC7M_OC7M5:    equ    5                                         ; Output Compare 7 Mask Bit 5
+TIM0_OC7M_OC7M6:    equ    6                                         ; Output Compare 7 Mask Bit 6
+TIM0_OC7M_OC7M7:    equ    7                                         ; Output Compare 7 Mask Bit 7
+; bit position masks
+mTIM0_OC7M_OC7M4:   equ    %00010000
+mTIM0_OC7M_OC7M5:   equ    %00100000
+mTIM0_OC7M_OC7M6:   equ    %01000000
+mTIM0_OC7M_OC7M7:   equ    %10000000
+
+
+;*** TIM0_OC7D - TIM0 Output Compare 7 Data Register; 0x00000043 ***
+TIM0_OC7D:          equ    $00000043                                ;*** TIM0_OC7D - TIM0 Output Compare 7 Data Register; 0x00000043 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+TIM0_OC7D_OC7D4:    equ    4                                         ; Output Compare 7 Bit 4
+TIM0_OC7D_OC7D5:    equ    5                                         ; Output Compare 7 Bit 5
+TIM0_OC7D_OC7D6:    equ    6                                         ; Output Compare 7 Bit 6
+TIM0_OC7D_OC7D7:    equ    7                                         ; Output Compare 7 Bit 7
+; bit position masks
+mTIM0_OC7D_OC7D4:   equ    %00010000
+mTIM0_OC7D_OC7D5:   equ    %00100000
+mTIM0_OC7D_OC7D6:   equ    %01000000
+mTIM0_OC7D_OC7D7:   equ    %10000000
+
+
+;*** TIM0_TCNT - TIM0 Timer Count Register; 0x00000044 ***
+TIM0_TCNT:          equ    $00000044                                ;*** TIM0_TCNT - TIM0 Timer Count Register; 0x00000044 ***
+
+
+;*** TIM0_TCNTHi - TIM0 Timer Count Register High; 0x00000044 ***
+TIM0_TCNTHi:        equ    $00000044                                ;*** TIM0_TCNTHi - TIM0 Timer Count Register High; 0x00000044 ***
+
+
+;*** TIM0_TCNTLo - TIM0 Timer Count Register Low; 0x00000045 ***
+TIM0_TCNTLo:        equ    $00000045                                ;*** TIM0_TCNTLo - TIM0 Timer Count Register Low; 0x00000045 ***
+
+
+;*** TIM0_TSCR1 - TIM0 Timer System Control Register1; 0x00000046 ***
+TIM0_TSCR1:         equ    $00000046                                ;*** TIM0_TSCR1 - TIM0 Timer System Control Register1; 0x00000046 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+TIM0_TSCR1_TFFCA:   equ    4                                         ; Timer Fast Flag Clear All
+TIM0_TSCR1_TSFRZ:   equ    5                                         ; Timer and Modulus Counter Stop While in Freeze Mode
+TIM0_TSCR1_TSWAI:   equ    6                                         ; Timer Module Stops While in Wait
+TIM0_TSCR1_TEN:     equ    7                                         ; Timer Enable
+; bit position masks
+mTIM0_TSCR1_TFFCA:  equ    %00010000
+mTIM0_TSCR1_TSFRZ:  equ    %00100000
+mTIM0_TSCR1_TSWAI:  equ    %01000000
+mTIM0_TSCR1_TEN:    equ    %10000000
+
+
+;*** TIM0_TTOV - TIM0 Timer Toggle On Overflow Register; 0x00000047 ***
+TIM0_TTOV:          equ    $00000047                                ;*** TIM0_TTOV - TIM0 Timer Toggle On Overflow Register; 0x00000047 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+TIM0_TTOV_TOV4:     equ    4                                         ; Toggle On Overflow Bit 4
+TIM0_TTOV_TOV5:     equ    5                                         ; Toggle On Overflow Bit 5
+TIM0_TTOV_TOV6:     equ    6                                         ; Toggle On Overflow Bit 6
+TIM0_TTOV_TOV7:     equ    7                                         ; Toggle On Overflow Bit 7
+; bit position masks
+mTIM0_TTOV_TOV4:    equ    %00010000
+mTIM0_TTOV_TOV5:    equ    %00100000
+mTIM0_TTOV_TOV6:    equ    %01000000
+mTIM0_TTOV_TOV7:    equ    %10000000
+
+
+;*** TIM0_TCTL1 - TIM0 Timer Control Register 1; 0x00000048 ***
+TIM0_TCTL1:         equ    $00000048                                ;*** TIM0_TCTL1 - TIM0 Timer Control Register 1; 0x00000048 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+TIM0_TCTL1_OL4:     equ    0                                         ; Output Level Bit 4
+TIM0_TCTL1_OM4:     equ    1                                         ; Output Mode Bit 4
+TIM0_TCTL1_OL5:     equ    2                                         ; Output Level Bit 5
+TIM0_TCTL1_OM5:     equ    3                                         ; Output Mode Bit 5
+TIM0_TCTL1_OL6:     equ    4                                         ; Output Level Bit 6
+TIM0_TCTL1_OM6:     equ    5                                         ; Output Mode Bit 6
+TIM0_TCTL1_OL7:     equ    6                                         ; Output Level Bit 7
+TIM0_TCTL1_OM7:     equ    7                                         ; Output Mode Bit 7
+; bit position masks
+mTIM0_TCTL1_OL4:    equ    %00000001
+mTIM0_TCTL1_OM4:    equ    %00000010
+mTIM0_TCTL1_OL5:    equ    %00000100
+mTIM0_TCTL1_OM5:    equ    %00001000
+mTIM0_TCTL1_OL6:    equ    %00010000
+mTIM0_TCTL1_OM6:    equ    %00100000
+mTIM0_TCTL1_OL7:    equ    %01000000
+mTIM0_TCTL1_OM7:    equ    %10000000
+
+
+;*** TIM0_TCTL3 - TIM0 Timer Control Register 3; 0x0000004A ***
+TIM0_TCTL3:         equ    $0000004A                                ;*** TIM0_TCTL3 - TIM0 Timer Control Register 3; 0x0000004A ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+TIM0_TCTL3_EDG4A:   equ    0                                         ; Input Capture Edge Control 4A
+TIM0_TCTL3_EDG4B:   equ    1                                         ; Input Capture Edge Control 4B
+TIM0_TCTL3_EDG5A:   equ    2                                         ; Input Capture Edge Control 5A
+TIM0_TCTL3_EDG5B:   equ    3                                         ; Input Capture Edge Control 5B
+TIM0_TCTL3_EDG6A:   equ    4                                         ; Input Capture Edge Control 6A
+TIM0_TCTL3_EDG6B:   equ    5                                         ; Input Capture Edge Control 6B
+TIM0_TCTL3_EDG7A:   equ    6                                         ; Input Capture Edge Control 7A
+TIM0_TCTL3_EDG7B:   equ    7                                         ; Input Capture Edge Control 7B
+; bit position masks
+mTIM0_TCTL3_EDG4A:  equ    %00000001
+mTIM0_TCTL3_EDG4B:  equ    %00000010
+mTIM0_TCTL3_EDG5A:  equ    %00000100
+mTIM0_TCTL3_EDG5B:  equ    %00001000
+mTIM0_TCTL3_EDG6A:  equ    %00010000
+mTIM0_TCTL3_EDG6B:  equ    %00100000
+mTIM0_TCTL3_EDG7A:  equ    %01000000
+mTIM0_TCTL3_EDG7B:  equ    %10000000
+
+
+;*** TIM0_TIE - TIM0 Timer Interrupt Enable Register; 0x0000004C ***
+TIM0_TIE:           equ    $0000004C                                ;*** TIM0_TIE - TIM0 Timer Interrupt Enable Register; 0x0000004C ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+TIM0_TIE_C4I:       equ    4                                         ; Input Capture/Output Compare Interrupt Enable Bit 4
+TIM0_TIE_C5I:       equ    5                                         ; Input Capture/Output Compare Interrupt Enable Bit 5
+TIM0_TIE_C6I:       equ    6                                         ; Input Capture/Output Compare Interrupt Enable Bit 6
+TIM0_TIE_C7I:       equ    7                                         ; Input Capture/Output Compare Interrupt Enable Bit 7
+; bit position masks
+mTIM0_TIE_C4I:      equ    %00010000
+mTIM0_TIE_C5I:      equ    %00100000
+mTIM0_TIE_C6I:      equ    %01000000
+mTIM0_TIE_C7I:      equ    %10000000
+
+
+;*** TIM0_TSCR2 - TIM0 Timer System Control Register 2; 0x0000004D ***
+TIM0_TSCR2:         equ    $0000004D                                ;*** TIM0_TSCR2 - TIM0 Timer System Control Register 2; 0x0000004D ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+TIM0_TSCR2_PR0:     equ    0                                         ; Timer Prescaler Select Bit 0
+TIM0_TSCR2_PR1:     equ    1                                         ; Timer Prescaler Select Bit 1
+TIM0_TSCR2_PR2:     equ    2                                         ; Timer Prescaler Select Bit 2
+TIM0_TSCR2_TCRE:    equ    3                                         ; Timer Counter Reset Enable
+TIM0_TSCR2_TOI:     equ    7                                         ; Timer Overflow Interrupt Enable
+; bit position masks
+mTIM0_TSCR2_PR0:    equ    %00000001
+mTIM0_TSCR2_PR1:    equ    %00000010
+mTIM0_TSCR2_PR2:    equ    %00000100
+mTIM0_TSCR2_TCRE:   equ    %00001000
+mTIM0_TSCR2_TOI:    equ    %10000000
+
+
+;*** TIM0_TFLG1 - TIM0 Main Timer Interrupt Flag 1; 0x0000004E ***
+TIM0_TFLG1:         equ    $0000004E                                ;*** TIM0_TFLG1 - TIM0 Main Timer Interrupt Flag 1; 0x0000004E ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+TIM0_TFLG1_C4F:     equ    4                                         ; Input Capture/Output Compare Channel Flag 4
+TIM0_TFLG1_C5F:     equ    5                                         ; Input Capture/Output Compare Channel Flag 5
+TIM0_TFLG1_C6F:     equ    6                                         ; Input Capture/Output Compare Channel Flag 6
+TIM0_TFLG1_C7F:     equ    7                                         ; Input Capture/Output Compare Channel Flag 7
+; bit position masks
+mTIM0_TFLG1_C4F:    equ    %00010000
+mTIM0_TFLG1_C5F:    equ    %00100000
+mTIM0_TFLG1_C6F:    equ    %01000000
+mTIM0_TFLG1_C7F:    equ    %10000000
+
+
+;*** TIM0_TFLG2 - TIM0 Main Timer Interrupt Flag 2; 0x0000004F ***
+TIM0_TFLG2:         equ    $0000004F                                ;*** TIM0_TFLG2 - TIM0 Main Timer Interrupt Flag 2; 0x0000004F ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+TIM0_TFLG2_TOF:     equ    7                                         ; Timer Overflow Flag
+; bit position masks
+mTIM0_TFLG2_TOF:    equ    %10000000
+
+
+;*** TIM0_TC4 - TIM0 Timer Input Capture/Output Compare Register 4; 0x00000058 ***
+TIM0_TC4:           equ    $00000058                                ;*** TIM0_TC4 - TIM0 Timer Input Capture/Output Compare Register 4; 0x00000058 ***
+
+
+;*** TIM0_TC4Hi - TIM0 Timer Input Capture/Output Compare Register 4 High; 0x00000058 ***
+TIM0_TC4Hi:         equ    $00000058                                ;*** TIM0_TC4Hi - TIM0 Timer Input Capture/Output Compare Register 4 High; 0x00000058 ***
+
+
+;*** TIM0_TC4Lo - TIM0 Timer Input Capture/Output Compare Register 4 Low; 0x00000059 ***
+TIM0_TC4Lo:         equ    $00000059                                ;*** TIM0_TC4Lo - TIM0 Timer Input Capture/Output Compare Register 4 Low; 0x00000059 ***
+
+
+;*** TIM0_TC5 - TIM0 Timer Input Capture/Output Compare Register 5; 0x0000005A ***
+TIM0_TC5:           equ    $0000005A                                ;*** TIM0_TC5 - TIM0 Timer Input Capture/Output Compare Register 5; 0x0000005A ***
+
+
+;*** TIM0_TC5Hi - TIM0 Timer Input Capture/Output Compare Register 5 High; 0x0000005A ***
+TIM0_TC5Hi:         equ    $0000005A                                ;*** TIM0_TC5Hi - TIM0 Timer Input Capture/Output Compare Register 5 High; 0x0000005A ***
+
+
+;*** TIM0_TC5Lo - TIM0 Timer Input Capture/Output Compare Register 5 Low; 0x0000005B ***
+TIM0_TC5Lo:         equ    $0000005B                                ;*** TIM0_TC5Lo - TIM0 Timer Input Capture/Output Compare Register 5 Low; 0x0000005B ***
+
+
+;*** TIM0_TC6 - TIM0 Timer Input Capture/Output Compare Register 6; 0x0000005C ***
+TIM0_TC6:           equ    $0000005C                                ;*** TIM0_TC6 - TIM0 Timer Input Capture/Output Compare Register 6; 0x0000005C ***
+
+
+;*** TIM0_TC6Hi - TIM0 Timer Input Capture/Output Compare Register 6 High; 0x0000005C ***
+TIM0_TC6Hi:         equ    $0000005C                                ;*** TIM0_TC6Hi - TIM0 Timer Input Capture/Output Compare Register 6 High; 0x0000005C ***
+
+
+;*** TIM0_TC6Lo - TIM0 Timer Input Capture/Output Compare Register 6 Low; 0x0000005D ***
+TIM0_TC6Lo:         equ    $0000005D                                ;*** TIM0_TC6Lo - TIM0 Timer Input Capture/Output Compare Register 6 Low; 0x0000005D ***
+
+
+;*** TIM0_TC7 - TIM0 Timer Input Capture/Output Compare Register 7; 0x0000005E ***
+TIM0_TC7:           equ    $0000005E                                ;*** TIM0_TC7 - TIM0 Timer Input Capture/Output Compare Register 7; 0x0000005E ***
+
+
+;*** TIM0_TC7Hi - TIM0 Timer Input Capture/Output Compare Register 7 High; 0x0000005E ***
+TIM0_TC7Hi:         equ    $0000005E                                ;*** TIM0_TC7Hi - TIM0 Timer Input Capture/Output Compare Register 7 High; 0x0000005E ***
+
+
+;*** TIM0_TC7Lo - TIM0 Timer Input Capture/Output Compare Register 7 Low; 0x0000005F ***
+TIM0_TC7Lo:         equ    $0000005F                                ;*** TIM0_TC7Lo - TIM0 Timer Input Capture/Output Compare Register 7 Low; 0x0000005F ***
+
+
+;*** TIM0_PACTL - TIM0 16-Bit Pulse Accumulator A Control Register; 0x00000060 ***
+TIM0_PACTL:         equ    $00000060                                ;*** TIM0_PACTL - TIM0 16-Bit Pulse Accumulator A Control Register; 0x00000060 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+TIM0_PACTL_PAI:     equ    0                                         ; Pulse Accumulator Input Interrupt enable
+TIM0_PACTL_PAOVI:   equ    1                                         ; Pulse Accumulator A Overflow Interrupt enable
+TIM0_PACTL_CLK0:    equ    2                                         ; Clock Select Bit 0
+TIM0_PACTL_CLK1:    equ    3                                         ; Clock Select Bit 1
+TIM0_PACTL_PEDGE:   equ    4                                         ; Pulse Accumulator Edge Control
+TIM0_PACTL_PAMOD:   equ    5                                         ; Pulse Accumulator Mode
+TIM0_PACTL_PAEN:    equ    6                                         ; Pulse Accumulator A System Enable
+; bit position masks
+mTIM0_PACTL_PAI:    equ    %00000001
+mTIM0_PACTL_PAOVI:  equ    %00000010
+mTIM0_PACTL_CLK0:   equ    %00000100
+mTIM0_PACTL_CLK1:   equ    %00001000
+mTIM0_PACTL_PEDGE:  equ    %00010000
+mTIM0_PACTL_PAMOD:  equ    %00100000
+mTIM0_PACTL_PAEN:   equ    %01000000
+
+
+;*** TIM0_PAFLG - TIM0 Pulse Accumulator A Flag Register; 0x00000061 ***
+TIM0_PAFLG:         equ    $00000061                                ;*** TIM0_PAFLG - TIM0 Pulse Accumulator A Flag Register; 0x00000061 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+TIM0_PAFLG_PAIF:    equ    0                                         ; Pulse Accumulator Input edge Flag
+TIM0_PAFLG_PAOVF:   equ    1                                         ; Pulse Accumulator A Overflow Flag
+; bit position masks
+mTIM0_PAFLG_PAIF:   equ    %00000001
+mTIM0_PAFLG_PAOVF:  equ    %00000010
+
+
+;*** TIM0_PACNT - TIM0 Pulse Accumulators Count Register; 0x00000062 ***
+TIM0_PACNT:         equ    $00000062                                ;*** TIM0_PACNT - TIM0 Pulse Accumulators Count Register; 0x00000062 ***
+
+
+;*** ATDCTL23 - ATD Control Register 23; 0x00000082 ***
+ATDCTL23:           equ    $00000082                                ;*** ATDCTL23 - ATD Control Register 23; 0x00000082 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+ATDCTL23_FRZ0:      equ    0                                         ; Background Debug Freeze Enable Bit 0
+ATDCTL23_FRZ1:      equ    1                                         ; Background Debug Freeze Enable Bit 1
+ATDCTL23_FIFO:      equ    2                                         ; Result Register FIFO Mode
+ATDCTL23_S1C:       equ    3                                         ; Conversion Sequence Length 1
+ATDCTL23_S2C:       equ    4                                         ; Conversion Sequence Length 2
+ATDCTL23_S4C:       equ    5                                         ; Conversion Sequence Length 4
+ATDCTL23_S8C:       equ    6                                         ; Conversion Sequence Length 8
+ATDCTL23_ASCIF:     equ    8                                         ; ATD Sequence Complete Interrupt Flag
+ATDCTL23_ASCIE:     equ    9                                         ; ATD Sequence Complete Interrupt Enable
+ATDCTL23_ETRIGE:    equ    10                                        ; External Trigger Mode enable
+ATDCTL23_ETRIGP:    equ    11                                        ; External Trigger Polarity
+ATDCTL23_ETRIGLE:   equ    12                                        ; External Trigger Level/Edge control
+ATDCTL23_AWAI:      equ    13                                        ; ATD Power Down in Wait Mode
+ATDCTL23_AFFC:      equ    14                                        ; ATD Fast Conversion Complete Flag Clear
+ATDCTL23_ADPU:      equ    15                                        ; ATD Disable / Power Down
+; bit position masks
+mATDCTL23_FRZ0:     equ    %00000001
+mATDCTL23_FRZ1:     equ    %00000010
+mATDCTL23_FIFO:     equ    %00000100
+mATDCTL23_S1C:      equ    %00001000
+mATDCTL23_S2C:      equ    %00010000
+mATDCTL23_S4C:      equ    %00100000
+mATDCTL23_S8C:      equ    %01000000
+mATDCTL23_ASCIF:    equ    %100000000
+mATDCTL23_ASCIE:    equ    %1000000000
+mATDCTL23_ETRIGE:   equ    %10000000000
+mATDCTL23_ETRIGP:   equ    %100000000000
+mATDCTL23_ETRIGLE:  equ    %1000000000000
+mATDCTL23_AWAI:     equ    %10000000000000
+mATDCTL23_AFFC:     equ    %100000000000000
+mATDCTL23_ADPU:     equ    %1000000000000000
+
+
+;*** ATDCTL2 - ATD Control Register 2; 0x00000082 ***
+ATDCTL2:            equ    $00000082                                ;*** ATDCTL2 - ATD Control Register 2; 0x00000082 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+ATDCTL2_ASCIF:      equ    0                                         ; ATD Sequence Complete Interrupt Flag
+ATDCTL2_ASCIE:      equ    1                                         ; ATD Sequence Complete Interrupt Enable
+ATDCTL2_ETRIGE:     equ    2                                         ; External Trigger Mode enable
+ATDCTL2_ETRIGP:     equ    3                                         ; External Trigger Polarity
+ATDCTL2_ETRIGLE:    equ    4                                         ; External Trigger Level/Edge control
+ATDCTL2_AWAI:       equ    5                                         ; ATD Power Down in Wait Mode
+ATDCTL2_AFFC:       equ    6                                         ; ATD Fast Conversion Complete Flag Clear
+ATDCTL2_ADPU:       equ    7                                         ; ATD Disable / Power Down
+; bit position masks
+mATDCTL2_ASCIF:     equ    %00000001
+mATDCTL2_ASCIE:     equ    %00000010
+mATDCTL2_ETRIGE:    equ    %00000100
+mATDCTL2_ETRIGP:    equ    %00001000
+mATDCTL2_ETRIGLE:   equ    %00010000
+mATDCTL2_AWAI:      equ    %00100000
+mATDCTL2_AFFC:      equ    %01000000
+mATDCTL2_ADPU:      equ    %10000000
+
+
+;*** ATDCTL3 - ATD Control Register 3; 0x00000083 ***
+ATDCTL3:            equ    $00000083                                ;*** ATDCTL3 - ATD Control Register 3; 0x00000083 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+ATDCTL3_FRZ0:       equ    0                                         ; Background Debug Freeze Enable Bit 0
+ATDCTL3_FRZ1:       equ    1                                         ; Background Debug Freeze Enable Bit 1
+ATDCTL3_FIFO:       equ    2                                         ; Result Register FIFO Mode
+ATDCTL3_S1C:        equ    3                                         ; Conversion Sequence Length 1
+ATDCTL3_S2C:        equ    4                                         ; Conversion Sequence Length 2
+ATDCTL3_S4C:        equ    5                                         ; Conversion Sequence Length 4
+ATDCTL3_S8C:        equ    6                                         ; Conversion Sequence Length 8
+; bit position masks
+mATDCTL3_FRZ0:      equ    %00000001
+mATDCTL3_FRZ1:      equ    %00000010
+mATDCTL3_FIFO:      equ    %00000100
+mATDCTL3_S1C:       equ    %00001000
+mATDCTL3_S2C:       equ    %00010000
+mATDCTL3_S4C:       equ    %00100000
+mATDCTL3_S8C:       equ    %01000000
+
+
+;*** ATDCTL45 - ATD Control Register 45; 0x00000084 ***
+ATDCTL45:           equ    $00000084                                ;*** ATDCTL45 - ATD Control Register 45; 0x00000084 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+ATDCTL45_CA:        equ    0                                         ; Analog Input Channel Select Code A
+ATDCTL45_CB:        equ    1                                         ; Analog Input Channel Select Code B
+ATDCTL45_CC:        equ    2                                         ; Analog Input Channel Select Code C
+ATDCTL45_CD:        equ    3                                         ; Analog Input Channel Select Code D
+ATDCTL45_MULT:      equ    4                                         ; Multi-Channel Sample Mode
+ATDCTL45_SCAN:      equ    5                                         ; Continuous Conversion Sequence Mode
+ATDCTL45_DSGN:      equ    6                                         ; Signed/Unsigned Result Data Mode
+ATDCTL45_DJM:       equ    7                                         ; Result Register Data Justification Mode
+ATDCTL45_PRS0:      equ    8                                         ; ATD Clock Prescaler 0
+ATDCTL45_PRS1:      equ    9                                         ; ATD Clock Prescaler 1
+ATDCTL45_PRS2:      equ    10                                        ; ATD Clock Prescaler 2
+ATDCTL45_PRS3:      equ    11                                        ; ATD Clock Prescaler 3
+ATDCTL45_PRS4:      equ    12                                        ; ATD Clock Prescaler 4
+ATDCTL45_SMP0:      equ    13                                        ; Sample Time Select 0
+ATDCTL45_SMP1:      equ    14                                        ; Sample Time Select 1
+ATDCTL45_SRES8:     equ    15                                        ; ATD Resolution Select
+; bit position masks
+mATDCTL45_CA:       equ    %00000001
+mATDCTL45_CB:       equ    %00000010
+mATDCTL45_CC:       equ    %00000100
+mATDCTL45_CD:       equ    %00001000
+mATDCTL45_MULT:     equ    %00010000
+mATDCTL45_SCAN:     equ    %00100000
+mATDCTL45_DSGN:     equ    %01000000
+mATDCTL45_DJM:      equ    %10000000
+mATDCTL45_PRS0:     equ    %100000000
+mATDCTL45_PRS1:     equ    %1000000000
+mATDCTL45_PRS2:     equ    %10000000000
+mATDCTL45_PRS3:     equ    %100000000000
+mATDCTL45_PRS4:     equ    %1000000000000
+mATDCTL45_SMP0:     equ    %10000000000000
+mATDCTL45_SMP1:     equ    %100000000000000
+mATDCTL45_SRES8:    equ    %1000000000000000
+
+
+;*** ATDCTL4 - ATD Control Register 4; 0x00000084 ***
+ATDCTL4:            equ    $00000084                                ;*** ATDCTL4 - ATD Control Register 4; 0x00000084 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+ATDCTL4_PRS0:       equ    0                                         ; ATD Clock Prescaler 0
+ATDCTL4_PRS1:       equ    1                                         ; ATD Clock Prescaler 1
+ATDCTL4_PRS2:       equ    2                                         ; ATD Clock Prescaler 2
+ATDCTL4_PRS3:       equ    3                                         ; ATD Clock Prescaler 3
+ATDCTL4_PRS4:       equ    4                                         ; ATD Clock Prescaler 4
+ATDCTL4_SMP0:       equ    5                                         ; Sample Time Select 0
+ATDCTL4_SMP1:       equ    6                                         ; Sample Time Select 1
+ATDCTL4_SRES8:      equ    7                                         ; ATD Resolution Select
+; bit position masks
+mATDCTL4_PRS0:      equ    %00000001
+mATDCTL4_PRS1:      equ    %00000010
+mATDCTL4_PRS2:      equ    %00000100
+mATDCTL4_PRS3:      equ    %00001000
+mATDCTL4_PRS4:      equ    %00010000
+mATDCTL4_SMP0:      equ    %00100000
+mATDCTL4_SMP1:      equ    %01000000
+mATDCTL4_SRES8:     equ    %10000000
+
+
+;*** ATDCTL5 - ATD Control Register 5; 0x00000085 ***
+ATDCTL5:            equ    $00000085                                ;*** ATDCTL5 - ATD Control Register 5; 0x00000085 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+ATDCTL5_CA:         equ    0                                         ; Analog Input Channel Select Code A
+ATDCTL5_CB:         equ    1                                         ; Analog Input Channel Select Code B
+ATDCTL5_CC:         equ    2                                         ; Analog Input Channel Select Code C
+ATDCTL5_CD:         equ    3                                         ; Analog Input Channel Select Code D
+ATDCTL5_MULT:       equ    4                                         ; Multi-Channel Sample Mode
+ATDCTL5_SCAN:       equ    5                                         ; Continuous Conversion Sequence Mode
+ATDCTL5_DSGN:       equ    6                                         ; Signed/Unsigned Result Data Mode
+ATDCTL5_DJM:        equ    7                                         ; Result Register Data Justification Mode
+; bit position masks
+mATDCTL5_CA:        equ    %00000001
+mATDCTL5_CB:        equ    %00000010
+mATDCTL5_CC:        equ    %00000100
+mATDCTL5_CD:        equ    %00001000
+mATDCTL5_MULT:      equ    %00010000
+mATDCTL5_SCAN:      equ    %00100000
+mATDCTL5_DSGN:      equ    %01000000
+mATDCTL5_DJM:       equ    %10000000
+
+
+;*** ATDSTAT0 - ATD Status Register 0; 0x00000086 ***
+ATDSTAT0:           equ    $00000086                                ;*** ATDSTAT0 - ATD Status Register 0; 0x00000086 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+ATDSTAT0_CC0:       equ    0                                         ; Conversion Counter 0
+ATDSTAT0_CC1:       equ    1                                         ; Conversion Counter 1
+ATDSTAT0_CC2:       equ    2                                         ; Conversion Counter 2
+ATDSTAT0_CC3:       equ    3                                         ; Conversion Counter 3
+ATDSTAT0_FIFOR:     equ    4                                         ; FIFO Over Run Flag
+ATDSTAT0_ETORF:     equ    5                                         ; External Trigger Overrun Flag
+ATDSTAT0_SCF:       equ    7                                         ; Sequence Complete Flag
+; bit position masks
+mATDSTAT0_CC0:      equ    %00000001
+mATDSTAT0_CC1:      equ    %00000010
+mATDSTAT0_CC2:      equ    %00000100
+mATDSTAT0_CC3:      equ    %00001000
+mATDSTAT0_FIFOR:    equ    %00010000
+mATDSTAT0_ETORF:    equ    %00100000
+mATDSTAT0_SCF:      equ    %10000000
+
+
+;*** ATDTEST1 - ATD Test Register; 0x00000089 ***
+ATDTEST1:           equ    $00000089                                ;*** ATDTEST1 - ATD Test Register; 0x00000089 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+ATDTEST1_SC:        equ    0                                         ; Special Channel Conversion Bit
+; bit position masks
+mATDTEST1_SC:       equ    %00000001
+
+
+;*** ATDSTAT2 - ATD Status Register 2; 0x0000008A ***
+ATDSTAT2:           equ    $0000008A                                ;*** ATDSTAT2 - ATD Status Register 2; 0x0000008A ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+ATDSTAT2_CCF8:      equ    0                                         ; Conversion Complete Flag 8
+ATDSTAT2_CCF9:      equ    1                                         ; Conversion Complete Flag 9
+ATDSTAT2_CCF10:     equ    2                                         ; Conversion Complete Flag 10
+ATDSTAT2_CCF11:     equ    3                                         ; Conversion Complete Flag 11
+ATDSTAT2_CCF12:     equ    4                                         ; Conversion Complete Flag 12
+ATDSTAT2_CCF13:     equ    5                                         ; Conversion Complete Flag 13
+ATDSTAT2_CCF14:     equ    6                                         ; Conversion Complete Flag 14
+ATDSTAT2_CCF15:     equ    7                                         ; Conversion Complete Flag 15
+; bit position masks
+mATDSTAT2_CCF8:     equ    %00000001
+mATDSTAT2_CCF9:     equ    %00000010
+mATDSTAT2_CCF10:    equ    %00000100
+mATDSTAT2_CCF11:    equ    %00001000
+mATDSTAT2_CCF12:    equ    %00010000
+mATDSTAT2_CCF13:    equ    %00100000
+mATDSTAT2_CCF14:    equ    %01000000
+mATDSTAT2_CCF15:    equ    %10000000
+
+
+;*** ATDSTAT1 - ATD Status Register 1; 0x0000008B ***
+ATDSTAT1:           equ    $0000008B                                ;*** ATDSTAT1 - ATD Status Register 1; 0x0000008B ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+ATDSTAT1_CCF0:      equ    0                                         ; Conversion Complete Flag 0
+ATDSTAT1_CCF1:      equ    1                                         ; Conversion Complete Flag 1
+ATDSTAT1_CCF2:      equ    2                                         ; Conversion Complete Flag 2
+ATDSTAT1_CCF3:      equ    3                                         ; Conversion Complete Flag 3
+ATDSTAT1_CCF4:      equ    4                                         ; Conversion Complete Flag 4
+ATDSTAT1_CCF5:      equ    5                                         ; Conversion Complete Flag 5
+ATDSTAT1_CCF6:      equ    6                                         ; Conversion Complete Flag 6
+ATDSTAT1_CCF7:      equ    7                                         ; Conversion Complete Flag 7
+; bit position masks
+mATDSTAT1_CCF0:     equ    %00000001
+mATDSTAT1_CCF1:     equ    %00000010
+mATDSTAT1_CCF2:     equ    %00000100
+mATDSTAT1_CCF3:     equ    %00001000
+mATDSTAT1_CCF4:     equ    %00010000
+mATDSTAT1_CCF5:     equ    %00100000
+mATDSTAT1_CCF6:     equ    %01000000
+mATDSTAT1_CCF7:     equ    %10000000
+
+
+;*** ATDDIEN - ATD Input Enable Register; 0x0000008C ***
+ATDDIEN:            equ    $0000008C                                ;*** ATDDIEN - ATD Input Enable Register; 0x0000008C ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+ATDDIEN_IEN0:       equ    0                                         ; ATD Digital Input Enable on channel 0
+ATDDIEN_IEN1:       equ    1                                         ; ATD Digital Input Enable on channel 1
+ATDDIEN_IEN2:       equ    2                                         ; ATD Digital Input Enable on channel 2
+ATDDIEN_IEN3:       equ    3                                         ; ATD Digital Input Enable on channel 3
+ATDDIEN_IEN4:       equ    4                                         ; ATD Digital Input Enable on channel 4
+ATDDIEN_IEN5:       equ    5                                         ; ATD Digital Input Enable on channel 5
+ATDDIEN_IEN6:       equ    6                                         ; ATD Digital Input Enable on channel 6
+ATDDIEN_IEN7:       equ    7                                         ; ATD Digital Input Enable on channel 7
+ATDDIEN_IEN8:       equ    8                                         ; ATD Digital Input Enable on channel 8
+ATDDIEN_IEN9:       equ    9                                         ; ATD Digital Input Enable on channel 9
+ATDDIEN_IEN10:      equ    10                                        ; ATD Digital Input Enable on channel 10
+ATDDIEN_IEN11:      equ    11                                        ; ATD Digital Input Enable on channel 11
+ATDDIEN_IEN12:      equ    12                                        ; ATD Digital Input Enable on channel 12
+ATDDIEN_IEN13:      equ    13                                        ; ATD Digital Input Enable on channel 13
+ATDDIEN_IEN14:      equ    14                                        ; ATD Digital Input Enable on channel 14
+ATDDIEN_IEN15:      equ    15                                        ; ATD Digital Input Enable on channel 15
+; bit position masks
+mATDDIEN_IEN0:      equ    %00000001
+mATDDIEN_IEN1:      equ    %00000010
+mATDDIEN_IEN2:      equ    %00000100
+mATDDIEN_IEN3:      equ    %00001000
+mATDDIEN_IEN4:      equ    %00010000
+mATDDIEN_IEN5:      equ    %00100000
+mATDDIEN_IEN6:      equ    %01000000
+mATDDIEN_IEN7:      equ    %10000000
+mATDDIEN_IEN8:      equ    %100000000
+mATDDIEN_IEN9:      equ    %1000000000
+mATDDIEN_IEN10:     equ    %10000000000
+mATDDIEN_IEN11:     equ    %100000000000
+mATDDIEN_IEN12:     equ    %1000000000000
+mATDDIEN_IEN13:     equ    %10000000000000
+mATDDIEN_IEN14:     equ    %100000000000000
+mATDDIEN_IEN15:     equ    %1000000000000000
+
+
+;*** ATDDIEN0 - ATD Input Enable Register 0; 0x0000008C ***
+ATDDIEN0:           equ    $0000008C                                ;*** ATDDIEN0 - ATD Input Enable Register 0; 0x0000008C ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+ATDDIEN0_IEN8:      equ    0                                         ; ATD Digital Input Enable on channel 8
+ATDDIEN0_IEN9:      equ    1                                         ; ATD Digital Input Enable on channel 9
+ATDDIEN0_IEN10:     equ    2                                         ; ATD Digital Input Enable on channel 10
+ATDDIEN0_IEN11:     equ    3                                         ; ATD Digital Input Enable on channel 11
+ATDDIEN0_IEN12:     equ    4                                         ; ATD Digital Input Enable on channel 12
+ATDDIEN0_IEN13:     equ    5                                         ; ATD Digital Input Enable on channel 13
+ATDDIEN0_IEN14:     equ    6                                         ; ATD Digital Input Enable on channel 14
+ATDDIEN0_IEN15:     equ    7                                         ; ATD Digital Input Enable on channel 15
+; bit position masks
+mATDDIEN0_IEN8:     equ    %00000001
+mATDDIEN0_IEN9:     equ    %00000010
+mATDDIEN0_IEN10:    equ    %00000100
+mATDDIEN0_IEN11:    equ    %00001000
+mATDDIEN0_IEN12:    equ    %00010000
+mATDDIEN0_IEN13:    equ    %00100000
+mATDDIEN0_IEN14:    equ    %01000000
+mATDDIEN0_IEN15:    equ    %10000000
+
+
+;*** ATDDIEN1 - ATD Input Enable Register 1; 0x0000008D ***
+ATDDIEN1:           equ    $0000008D                                ;*** ATDDIEN1 - ATD Input Enable Register 1; 0x0000008D ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+ATDDIEN1_IEN0:      equ    0                                         ; ATD Digital Input Enable on channel 0
+ATDDIEN1_IEN1:      equ    1                                         ; ATD Digital Input Enable on channel 1
+ATDDIEN1_IEN2:      equ    2                                         ; ATD Digital Input Enable on channel 2
+ATDDIEN1_IEN3:      equ    3                                         ; ATD Digital Input Enable on channel 3
+ATDDIEN1_IEN4:      equ    4                                         ; ATD Digital Input Enable on channel 4
+ATDDIEN1_IEN5:      equ    5                                         ; ATD Digital Input Enable on channel 5
+ATDDIEN1_IEN6:      equ    6                                         ; ATD Digital Input Enable on channel 6
+ATDDIEN1_IEN7:      equ    7                                         ; ATD Digital Input Enable on channel 7
+; bit position masks
+mATDDIEN1_IEN0:     equ    %00000001
+mATDDIEN1_IEN1:     equ    %00000010
+mATDDIEN1_IEN2:     equ    %00000100
+mATDDIEN1_IEN3:     equ    %00001000
+mATDDIEN1_IEN4:     equ    %00010000
+mATDDIEN1_IEN5:     equ    %00100000
+mATDDIEN1_IEN6:     equ    %01000000
+mATDDIEN1_IEN7:     equ    %10000000
+
+
+;*** PORTAD0 - Port AD0 Register; 0x0000008E ***
+PORTAD0:            equ    $0000008E                                ;*** PORTAD0 - Port AD0 Register; 0x0000008E ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PORTAD0_PTAD8:      equ    0                                         ; Port AD Bit 8
+PORTAD0_PTAD9:      equ    1                                         ; Port AD Bit 9
+PORTAD0_PTAD10:     equ    2                                         ; Port AD Bit 10
+PORTAD0_PTAD11:     equ    3                                         ; Port AD Bit 11
+PORTAD0_PTAD12:     equ    4                                         ; Port AD Bit 12
+PORTAD0_PTAD13:     equ    5                                         ; Port AD Bit 13
+PORTAD0_PTAD14:     equ    6                                         ; Port AD Bit 14
+PORTAD0_PTAD15:     equ    7                                         ; Port AD Bit 15
+; bit position masks
+mPORTAD0_PTAD8:     equ    %00000001
+mPORTAD0_PTAD9:     equ    %00000010
+mPORTAD0_PTAD10:    equ    %00000100
+mPORTAD0_PTAD11:    equ    %00001000
+mPORTAD0_PTAD12:    equ    %00010000
+mPORTAD0_PTAD13:    equ    %00100000
+mPORTAD0_PTAD14:    equ    %01000000
+mPORTAD0_PTAD15:    equ    %10000000
+
+
+;*** PORTAD1 - Port AD1 Register; 0x0000008F ***
+PORTAD1:            equ    $0000008F                                ;*** PORTAD1 - Port AD1 Register; 0x0000008F ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PORTAD1_PTAD0:      equ    0                                         ; Port AD Bit 0
+PORTAD1_PTAD1:      equ    1                                         ; Port AD Bit 1
+PORTAD1_PTAD2:      equ    2                                         ; Port AD Bit 2
+PORTAD1_PTAD3:      equ    3                                         ; Port AD Bit 3
+PORTAD1_PTAD4:      equ    4                                         ; Port AD Bit 4
+PORTAD1_PTAD5:      equ    5                                         ; Port AD Bit 5
+PORTAD1_PTAD6:      equ    6                                         ; Port AD Bit 6
+PORTAD1_PTAD7:      equ    7                                         ; Port AD Bit 7
+; bit position masks
+mPORTAD1_PTAD0:     equ    %00000001
+mPORTAD1_PTAD1:     equ    %00000010
+mPORTAD1_PTAD2:     equ    %00000100
+mPORTAD1_PTAD3:     equ    %00001000
+mPORTAD1_PTAD4:     equ    %00010000
+mPORTAD1_PTAD5:     equ    %00100000
+mPORTAD1_PTAD6:     equ    %01000000
+mPORTAD1_PTAD7:     equ    %10000000
+
+
+;*** ATDDR0 - ATD Conversion Result Register 0; 0x00000090 ***
+ATDDR0:             equ    $00000090                                ;*** ATDDR0 - ATD Conversion Result Register 0; 0x00000090 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+ATDDR0_BIT6:        equ    6                                         ; Bit 6
+ATDDR0_BIT7:        equ    7                                         ; Bit 7
+ATDDR0_BIT8:        equ    8                                         ; Bit 8
+ATDDR0_BIT9:        equ    9                                         ; Bit 9
+ATDDR0_BIT10:       equ    10                                        ; Bit 10
+ATDDR0_BIT11:       equ    11                                        ; Bit 11
+ATDDR0_BIT12:       equ    12                                        ; Bit 12
+ATDDR0_BIT13:       equ    13                                        ; Bit 13
+ATDDR0_BIT14:       equ    14                                        ; Bit 14
+ATDDR0_BIT15:       equ    15                                        ; Bit 15
+; bit position masks
+mATDDR0_BIT6:       equ    %01000000
+mATDDR0_BIT7:       equ    %10000000
+mATDDR0_BIT8:       equ    %100000000
+mATDDR0_BIT9:       equ    %1000000000
+mATDDR0_BIT10:      equ    %10000000000
+mATDDR0_BIT11:      equ    %100000000000
+mATDDR0_BIT12:      equ    %1000000000000
+mATDDR0_BIT13:      equ    %10000000000000
+mATDDR0_BIT14:      equ    %100000000000000
+mATDDR0_BIT15:      equ    %1000000000000000
+
+
+;*** ATDDR0H - ATD Conversion Result Register 0 High; 0x00000090 ***
+ATDDR0H:            equ    $00000090                                ;*** ATDDR0H - ATD Conversion Result Register 0 High; 0x00000090 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+ATDDR0H_BIT8:       equ    0                                         ; Bit 8
+ATDDR0H_BIT9:       equ    1                                         ; Bit 9
+ATDDR0H_BIT10:      equ    2                                         ; Bit 10
+ATDDR0H_BIT11:      equ    3                                         ; Bit 11
+ATDDR0H_BIT12:      equ    4                                         ; Bit 12
+ATDDR0H_BIT13:      equ    5                                         ; Bit 13
+ATDDR0H_BIT14:      equ    6                                         ; Bit 14
+ATDDR0H_BIT15:      equ    7                                         ; Bit 15
+; bit position masks
+mATDDR0H_BIT8:      equ    %00000001
+mATDDR0H_BIT9:      equ    %00000010
+mATDDR0H_BIT10:     equ    %00000100
+mATDDR0H_BIT11:     equ    %00001000
+mATDDR0H_BIT12:     equ    %00010000
+mATDDR0H_BIT13:     equ    %00100000
+mATDDR0H_BIT14:     equ    %01000000
+mATDDR0H_BIT15:     equ    %10000000
+
+
+;*** ATDDR0L - ATD Conversion Result Register 0 Low; 0x00000091 ***
+ATDDR0L:            equ    $00000091                                ;*** ATDDR0L - ATD Conversion Result Register 0 Low; 0x00000091 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+ATDDR0L_BIT6:       equ    6                                         ; Bit 6
+ATDDR0L_BIT7:       equ    7                                         ; Bit 7
+; bit position masks
+mATDDR0L_BIT6:      equ    %01000000
+mATDDR0L_BIT7:      equ    %10000000
+
+
+;*** ATDDR1 - ATD Conversion Result Register 1; 0x00000092 ***
+ATDDR1:             equ    $00000092                                ;*** ATDDR1 - ATD Conversion Result Register 1; 0x00000092 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+ATDDR1_BIT6:        equ    6                                         ; Bit 6
+ATDDR1_BIT7:        equ    7                                         ; Bit 7
+ATDDR1_BIT8:        equ    8                                         ; Bit 8
+ATDDR1_BIT9:        equ    9                                         ; Bit 9
+ATDDR1_BIT10:       equ    10                                        ; Bit 10
+ATDDR1_BIT11:       equ    11                                        ; Bit 11
+ATDDR1_BIT12:       equ    12                                        ; Bit 12
+ATDDR1_BIT13:       equ    13                                        ; Bit 13
+ATDDR1_BIT14:       equ    14                                        ; Bit 14
+ATDDR1_BIT15:       equ    15                                        ; Bit 15
+; bit position masks
+mATDDR1_BIT6:       equ    %01000000
+mATDDR1_BIT7:       equ    %10000000
+mATDDR1_BIT8:       equ    %100000000
+mATDDR1_BIT9:       equ    %1000000000
+mATDDR1_BIT10:      equ    %10000000000
+mATDDR1_BIT11:      equ    %100000000000
+mATDDR1_BIT12:      equ    %1000000000000
+mATDDR1_BIT13:      equ    %10000000000000
+mATDDR1_BIT14:      equ    %100000000000000
+mATDDR1_BIT15:      equ    %1000000000000000
+
+
+;*** ATDDR1H - ATD Conversion Result Register 1 High; 0x00000092 ***
+ATDDR1H:            equ    $00000092                                ;*** ATDDR1H - ATD Conversion Result Register 1 High; 0x00000092 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+ATDDR1H_BIT8:       equ    0                                         ; Bit 8
+ATDDR1H_BIT9:       equ    1                                         ; Bit 9
+ATDDR1H_BIT10:      equ    2                                         ; Bit 10
+ATDDR1H_BIT11:      equ    3                                         ; Bit 11
+ATDDR1H_BIT12:      equ    4                                         ; Bit 12
+ATDDR1H_BIT13:      equ    5                                         ; Bit 13
+ATDDR1H_BIT14:      equ    6                                         ; Bit 14
+ATDDR1H_BIT15:      equ    7                                         ; Bit 15
+; bit position masks
+mATDDR1H_BIT8:      equ    %00000001
+mATDDR1H_BIT9:      equ    %00000010
+mATDDR1H_BIT10:     equ    %00000100
+mATDDR1H_BIT11:     equ    %00001000
+mATDDR1H_BIT12:     equ    %00010000
+mATDDR1H_BIT13:     equ    %00100000
+mATDDR1H_BIT14:     equ    %01000000
+mATDDR1H_BIT15:     equ    %10000000
+
+
+;*** ATDDR1L - ATD Conversion Result Register 1 Low; 0x00000093 ***
+ATDDR1L:            equ    $00000093                                ;*** ATDDR1L - ATD Conversion Result Register 1 Low; 0x00000093 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+ATDDR1L_BIT6:       equ    6                                         ; Bit 6
+ATDDR1L_BIT7:       equ    7                                         ; Bit 7
+; bit position masks
+mATDDR1L_BIT6:      equ    %01000000
+mATDDR1L_BIT7:      equ    %10000000
+
+
+;*** ATDDR2 - ATD Conversion Result Register 2; 0x00000094 ***
+ATDDR2:             equ    $00000094                                ;*** ATDDR2 - ATD Conversion Result Register 2; 0x00000094 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+ATDDR2_BIT6:        equ    6                                         ; Bit 6
+ATDDR2_BIT7:        equ    7                                         ; Bit 7
+ATDDR2_BIT8:        equ    8                                         ; Bit 8
+ATDDR2_BIT9:        equ    9                                         ; Bit 9
+ATDDR2_BIT10:       equ    10                                        ; Bit 10
+ATDDR2_BIT11:       equ    11                                        ; Bit 11
+ATDDR2_BIT12:       equ    12                                        ; Bit 12
+ATDDR2_BIT13:       equ    13                                        ; Bit 13
+ATDDR2_BIT14:       equ    14                                        ; Bit 14
+ATDDR2_BIT15:       equ    15                                        ; Bit 15
+; bit position masks
+mATDDR2_BIT6:       equ    %01000000
+mATDDR2_BIT7:       equ    %10000000
+mATDDR2_BIT8:       equ    %100000000
+mATDDR2_BIT9:       equ    %1000000000
+mATDDR2_BIT10:      equ    %10000000000
+mATDDR2_BIT11:      equ    %100000000000
+mATDDR2_BIT12:      equ    %1000000000000
+mATDDR2_BIT13:      equ    %10000000000000
+mATDDR2_BIT14:      equ    %100000000000000
+mATDDR2_BIT15:      equ    %1000000000000000
+
+
+;*** ATDDR2H - ATD Conversion Result Register 2 High; 0x00000094 ***
+ATDDR2H:            equ    $00000094                                ;*** ATDDR2H - ATD Conversion Result Register 2 High; 0x00000094 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+ATDDR2H_BIT8:       equ    0                                         ; Bit 8
+ATDDR2H_BIT9:       equ    1                                         ; Bit 9
+ATDDR2H_BIT10:      equ    2                                         ; Bit 10
+ATDDR2H_BIT11:      equ    3                                         ; Bit 11
+ATDDR2H_BIT12:      equ    4                                         ; Bit 12
+ATDDR2H_BIT13:      equ    5                                         ; Bit 13
+ATDDR2H_BIT14:      equ    6                                         ; Bit 14
+ATDDR2H_BIT15:      equ    7                                         ; Bit 15
+; bit position masks
+mATDDR2H_BIT8:      equ    %00000001
+mATDDR2H_BIT9:      equ    %00000010
+mATDDR2H_BIT10:     equ    %00000100
+mATDDR2H_BIT11:     equ    %00001000
+mATDDR2H_BIT12:     equ    %00010000
+mATDDR2H_BIT13:     equ    %00100000
+mATDDR2H_BIT14:     equ    %01000000
+mATDDR2H_BIT15:     equ    %10000000
+
+
+;*** ATDDR2L - ATD Conversion Result Register 2 Low; 0x00000095 ***
+ATDDR2L:            equ    $00000095                                ;*** ATDDR2L - ATD Conversion Result Register 2 Low; 0x00000095 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+ATDDR2L_BIT6:       equ    6                                         ; Bit 6
+ATDDR2L_BIT7:       equ    7                                         ; Bit 7
+; bit position masks
+mATDDR2L_BIT6:      equ    %01000000
+mATDDR2L_BIT7:      equ    %10000000
+
+
+;*** ATDDR3 - ATD Conversion Result Register 3; 0x00000096 ***
+ATDDR3:             equ    $00000096                                ;*** ATDDR3 - ATD Conversion Result Register 3; 0x00000096 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+ATDDR3_BIT6:        equ    6                                         ; Bit 6
+ATDDR3_BIT7:        equ    7                                         ; Bit 7
+ATDDR3_BIT8:        equ    8                                         ; Bit 8
+ATDDR3_BIT9:        equ    9                                         ; Bit 9
+ATDDR3_BIT10:       equ    10                                        ; Bit 10
+ATDDR3_BIT11:       equ    11                                        ; Bit 11
+ATDDR3_BIT12:       equ    12                                        ; Bit 12
+ATDDR3_BIT13:       equ    13                                        ; Bit 13
+ATDDR3_BIT14:       equ    14                                        ; Bit 14
+ATDDR3_BIT15:       equ    15                                        ; Bit 15
+; bit position masks
+mATDDR3_BIT6:       equ    %01000000
+mATDDR3_BIT7:       equ    %10000000
+mATDDR3_BIT8:       equ    %100000000
+mATDDR3_BIT9:       equ    %1000000000
+mATDDR3_BIT10:      equ    %10000000000
+mATDDR3_BIT11:      equ    %100000000000
+mATDDR3_BIT12:      equ    %1000000000000
+mATDDR3_BIT13:      equ    %10000000000000
+mATDDR3_BIT14:      equ    %100000000000000
+mATDDR3_BIT15:      equ    %1000000000000000
+
+
+;*** ATDDR3H - ATD Conversion Result Register 3 High; 0x00000096 ***
+ATDDR3H:            equ    $00000096                                ;*** ATDDR3H - ATD Conversion Result Register 3 High; 0x00000096 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+ATDDR3H_BIT8:       equ    0                                         ; Bit 8
+ATDDR3H_BIT9:       equ    1                                         ; Bit 9
+ATDDR3H_BIT10:      equ    2                                         ; Bit 10
+ATDDR3H_BIT11:      equ    3                                         ; Bit 11
+ATDDR3H_BIT12:      equ    4                                         ; Bit 12
+ATDDR3H_BIT13:      equ    5                                         ; Bit 13
+ATDDR3H_BIT14:      equ    6                                         ; Bit 14
+ATDDR3H_BIT15:      equ    7                                         ; Bit 15
+; bit position masks
+mATDDR3H_BIT8:      equ    %00000001
+mATDDR3H_BIT9:      equ    %00000010
+mATDDR3H_BIT10:     equ    %00000100
+mATDDR3H_BIT11:     equ    %00001000
+mATDDR3H_BIT12:     equ    %00010000
+mATDDR3H_BIT13:     equ    %00100000
+mATDDR3H_BIT14:     equ    %01000000
+mATDDR3H_BIT15:     equ    %10000000
+
+
+;*** ATDDR3L - ATD Conversion Result Register 3 Low; 0x00000097 ***
+ATDDR3L:            equ    $00000097                                ;*** ATDDR3L - ATD Conversion Result Register 3 Low; 0x00000097 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+ATDDR3L_BIT6:       equ    6                                         ; Bit 6
+ATDDR3L_BIT7:       equ    7                                         ; Bit 7
+; bit position masks
+mATDDR3L_BIT6:      equ    %01000000
+mATDDR3L_BIT7:      equ    %10000000
+
+
+;*** ATDDR4 - ATD Conversion Result Register 4; 0x00000098 ***
+ATDDR4:             equ    $00000098                                ;*** ATDDR4 - ATD Conversion Result Register 4; 0x00000098 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+ATDDR4_BIT6:        equ    6                                         ; Bit 6
+ATDDR4_BIT7:        equ    7                                         ; Bit 7
+ATDDR4_BIT8:        equ    8                                         ; Bit 8
+ATDDR4_BIT9:        equ    9                                         ; Bit 9
+ATDDR4_BIT10:       equ    10                                        ; Bit 10
+ATDDR4_BIT11:       equ    11                                        ; Bit 11
+ATDDR4_BIT12:       equ    12                                        ; Bit 12
+ATDDR4_BIT13:       equ    13                                        ; Bit 13
+ATDDR4_BIT14:       equ    14                                        ; Bit 14
+ATDDR4_BIT15:       equ    15                                        ; Bit 15
+; bit position masks
+mATDDR4_BIT6:       equ    %01000000
+mATDDR4_BIT7:       equ    %10000000
+mATDDR4_BIT8:       equ    %100000000
+mATDDR4_BIT9:       equ    %1000000000
+mATDDR4_BIT10:      equ    %10000000000
+mATDDR4_BIT11:      equ    %100000000000
+mATDDR4_BIT12:      equ    %1000000000000
+mATDDR4_BIT13:      equ    %10000000000000
+mATDDR4_BIT14:      equ    %100000000000000
+mATDDR4_BIT15:      equ    %1000000000000000
+
+
+;*** ATDDR4H - ATD Conversion Result Register 4 High; 0x00000098 ***
+ATDDR4H:            equ    $00000098                                ;*** ATDDR4H - ATD Conversion Result Register 4 High; 0x00000098 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+ATDDR4H_BIT8:       equ    0                                         ; Bit 8
+ATDDR4H_BIT9:       equ    1                                         ; Bit 9
+ATDDR4H_BIT10:      equ    2                                         ; Bit 10
+ATDDR4H_BIT11:      equ    3                                         ; Bit 11
+ATDDR4H_BIT12:      equ    4                                         ; Bit 12
+ATDDR4H_BIT13:      equ    5                                         ; Bit 13
+ATDDR4H_BIT14:      equ    6                                         ; Bit 14
+ATDDR4H_BIT15:      equ    7                                         ; Bit 15
+; bit position masks
+mATDDR4H_BIT8:      equ    %00000001
+mATDDR4H_BIT9:      equ    %00000010
+mATDDR4H_BIT10:     equ    %00000100
+mATDDR4H_BIT11:     equ    %00001000
+mATDDR4H_BIT12:     equ    %00010000
+mATDDR4H_BIT13:     equ    %00100000
+mATDDR4H_BIT14:     equ    %01000000
+mATDDR4H_BIT15:     equ    %10000000
+
+
+;*** ATDDR4L - ATD Conversion Result Register 4 Low; 0x00000099 ***
+ATDDR4L:            equ    $00000099                                ;*** ATDDR4L - ATD Conversion Result Register 4 Low; 0x00000099 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+ATDDR4L_BIT6:       equ    6                                         ; Bit 6
+ATDDR4L_BIT7:       equ    7                                         ; Bit 7
+; bit position masks
+mATDDR4L_BIT6:      equ    %01000000
+mATDDR4L_BIT7:      equ    %10000000
+
+
+;*** ATDDR5 - ATD Conversion Result Register 5; 0x0000009A ***
+ATDDR5:             equ    $0000009A                                ;*** ATDDR5 - ATD Conversion Result Register 5; 0x0000009A ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+ATDDR5_BIT6:        equ    6                                         ; Bit 6
+ATDDR5_BIT7:        equ    7                                         ; Bit 7
+ATDDR5_BIT8:        equ    8                                         ; Bit 8
+ATDDR5_BIT9:        equ    9                                         ; Bit 9
+ATDDR5_BIT10:       equ    10                                        ; Bit 10
+ATDDR5_BIT11:       equ    11                                        ; Bit 11
+ATDDR5_BIT12:       equ    12                                        ; Bit 12
+ATDDR5_BIT13:       equ    13                                        ; Bit 13
+ATDDR5_BIT14:       equ    14                                        ; Bit 14
+ATDDR5_BIT15:       equ    15                                        ; Bit 15
+; bit position masks
+mATDDR5_BIT6:       equ    %01000000
+mATDDR5_BIT7:       equ    %10000000
+mATDDR5_BIT8:       equ    %100000000
+mATDDR5_BIT9:       equ    %1000000000
+mATDDR5_BIT10:      equ    %10000000000
+mATDDR5_BIT11:      equ    %100000000000
+mATDDR5_BIT12:      equ    %1000000000000
+mATDDR5_BIT13:      equ    %10000000000000
+mATDDR5_BIT14:      equ    %100000000000000
+mATDDR5_BIT15:      equ    %1000000000000000
+
+
+;*** ATDDR5H - ATD Conversion Result Register 5 High; 0x0000009A ***
+ATDDR5H:            equ    $0000009A                                ;*** ATDDR5H - ATD Conversion Result Register 5 High; 0x0000009A ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+ATDDR5H_BIT8:       equ    0                                         ; Bit 8
+ATDDR5H_BIT9:       equ    1                                         ; Bit 9
+ATDDR5H_BIT10:      equ    2                                         ; Bit 10
+ATDDR5H_BIT11:      equ    3                                         ; Bit 11
+ATDDR5H_BIT12:      equ    4                                         ; Bit 12
+ATDDR5H_BIT13:      equ    5                                         ; Bit 13
+ATDDR5H_BIT14:      equ    6                                         ; Bit 14
+ATDDR5H_BIT15:      equ    7                                         ; Bit 15
+; bit position masks
+mATDDR5H_BIT8:      equ    %00000001
+mATDDR5H_BIT9:      equ    %00000010
+mATDDR5H_BIT10:     equ    %00000100
+mATDDR5H_BIT11:     equ    %00001000
+mATDDR5H_BIT12:     equ    %00010000
+mATDDR5H_BIT13:     equ    %00100000
+mATDDR5H_BIT14:     equ    %01000000
+mATDDR5H_BIT15:     equ    %10000000
+
+
+;*** ATDDR5L - ATD Conversion Result Register 5 Low; 0x0000009B ***
+ATDDR5L:            equ    $0000009B                                ;*** ATDDR5L - ATD Conversion Result Register 5 Low; 0x0000009B ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+ATDDR5L_BIT6:       equ    6                                         ; Bit 6
+ATDDR5L_BIT7:       equ    7                                         ; Bit 7
+; bit position masks
+mATDDR5L_BIT6:      equ    %01000000
+mATDDR5L_BIT7:      equ    %10000000
+
+
+;*** ATDDR6 - ATD Conversion Result Register 6; 0x0000009C ***
+ATDDR6:             equ    $0000009C                                ;*** ATDDR6 - ATD Conversion Result Register 6; 0x0000009C ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+ATDDR6_BIT6:        equ    6                                         ; Bit 6
+ATDDR6_BIT7:        equ    7                                         ; Bit 7
+ATDDR6_BIT8:        equ    8                                         ; Bit 8
+ATDDR6_BIT9:        equ    9                                         ; Bit 9
+ATDDR6_BIT10:       equ    10                                        ; Bit 10
+ATDDR6_BIT11:       equ    11                                        ; Bit 11
+ATDDR6_BIT12:       equ    12                                        ; Bit 12
+ATDDR6_BIT13:       equ    13                                        ; Bit 13
+ATDDR6_BIT14:       equ    14                                        ; Bit 14
+ATDDR6_BIT15:       equ    15                                        ; Bit 15
+; bit position masks
+mATDDR6_BIT6:       equ    %01000000
+mATDDR6_BIT7:       equ    %10000000
+mATDDR6_BIT8:       equ    %100000000
+mATDDR6_BIT9:       equ    %1000000000
+mATDDR6_BIT10:      equ    %10000000000
+mATDDR6_BIT11:      equ    %100000000000
+mATDDR6_BIT12:      equ    %1000000000000
+mATDDR6_BIT13:      equ    %10000000000000
+mATDDR6_BIT14:      equ    %100000000000000
+mATDDR6_BIT15:      equ    %1000000000000000
+
+
+;*** ATDDR6H - ATD Conversion Result Register 6 High; 0x0000009C ***
+ATDDR6H:            equ    $0000009C                                ;*** ATDDR6H - ATD Conversion Result Register 6 High; 0x0000009C ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+ATDDR6H_BIT8:       equ    0                                         ; Bit 8
+ATDDR6H_BIT9:       equ    1                                         ; Bit 9
+ATDDR6H_BIT10:      equ    2                                         ; Bit 10
+ATDDR6H_BIT11:      equ    3                                         ; Bit 11
+ATDDR6H_BIT12:      equ    4                                         ; Bit 12
+ATDDR6H_BIT13:      equ    5                                         ; Bit 13
+ATDDR6H_BIT14:      equ    6                                         ; Bit 14
+ATDDR6H_BIT15:      equ    7                                         ; Bit 15
+; bit position masks
+mATDDR6H_BIT8:      equ    %00000001
+mATDDR6H_BIT9:      equ    %00000010
+mATDDR6H_BIT10:     equ    %00000100
+mATDDR6H_BIT11:     equ    %00001000
+mATDDR6H_BIT12:     equ    %00010000
+mATDDR6H_BIT13:     equ    %00100000
+mATDDR6H_BIT14:     equ    %01000000
+mATDDR6H_BIT15:     equ    %10000000
+
+
+;*** ATDDR6L - ATD Conversion Result Register 6 Low; 0x0000009D ***
+ATDDR6L:            equ    $0000009D                                ;*** ATDDR6L - ATD Conversion Result Register 6 Low; 0x0000009D ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+ATDDR6L_BIT6:       equ    6                                         ; Bit 6
+ATDDR6L_BIT7:       equ    7                                         ; Bit 7
+; bit position masks
+mATDDR6L_BIT6:      equ    %01000000
+mATDDR6L_BIT7:      equ    %10000000
+
+
+;*** ATDDR7 - ATD Conversion Result Register 7; 0x0000009E ***
+ATDDR7:             equ    $0000009E                                ;*** ATDDR7 - ATD Conversion Result Register 7; 0x0000009E ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+ATDDR7_BIT6:        equ    6                                         ; Bit 6
+ATDDR7_BIT7:        equ    7                                         ; Bit 7
+ATDDR7_BIT8:        equ    8                                         ; Bit 8
+ATDDR7_BIT9:        equ    9                                         ; Bit 9
+ATDDR7_BIT10:       equ    10                                        ; Bit 10
+ATDDR7_BIT11:       equ    11                                        ; Bit 11
+ATDDR7_BIT12:       equ    12                                        ; Bit 12
+ATDDR7_BIT13:       equ    13                                        ; Bit 13
+ATDDR7_BIT14:       equ    14                                        ; Bit 14
+ATDDR7_BIT15:       equ    15                                        ; Bit 15
+; bit position masks
+mATDDR7_BIT6:       equ    %01000000
+mATDDR7_BIT7:       equ    %10000000
+mATDDR7_BIT8:       equ    %100000000
+mATDDR7_BIT9:       equ    %1000000000
+mATDDR7_BIT10:      equ    %10000000000
+mATDDR7_BIT11:      equ    %100000000000
+mATDDR7_BIT12:      equ    %1000000000000
+mATDDR7_BIT13:      equ    %10000000000000
+mATDDR7_BIT14:      equ    %100000000000000
+mATDDR7_BIT15:      equ    %1000000000000000
+
+
+;*** ATDDR7H - ATD Conversion Result Register 7 High; 0x0000009E ***
+ATDDR7H:            equ    $0000009E                                ;*** ATDDR7H - ATD Conversion Result Register 7 High; 0x0000009E ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+ATDDR7H_BIT8:       equ    0                                         ; Bit 8
+ATDDR7H_BIT9:       equ    1                                         ; Bit 9
+ATDDR7H_BIT10:      equ    2                                         ; Bit 10
+ATDDR7H_BIT11:      equ    3                                         ; Bit 11
+ATDDR7H_BIT12:      equ    4                                         ; Bit 12
+ATDDR7H_BIT13:      equ    5                                         ; Bit 13
+ATDDR7H_BIT14:      equ    6                                         ; Bit 14
+ATDDR7H_BIT15:      equ    7                                         ; Bit 15
+; bit position masks
+mATDDR7H_BIT8:      equ    %00000001
+mATDDR7H_BIT9:      equ    %00000010
+mATDDR7H_BIT10:     equ    %00000100
+mATDDR7H_BIT11:     equ    %00001000
+mATDDR7H_BIT12:     equ    %00010000
+mATDDR7H_BIT13:     equ    %00100000
+mATDDR7H_BIT14:     equ    %01000000
+mATDDR7H_BIT15:     equ    %10000000
+
+
+;*** ATDDR7L - ATD Conversion Result Register 7 Low; 0x0000009F ***
+ATDDR7L:            equ    $0000009F                                ;*** ATDDR7L - ATD Conversion Result Register 7 Low; 0x0000009F ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+ATDDR7L_BIT6:       equ    6                                         ; Bit 6
+ATDDR7L_BIT7:       equ    7                                         ; Bit 7
+; bit position masks
+mATDDR7L_BIT6:      equ    %01000000
+mATDDR7L_BIT7:      equ    %10000000
+
+
+;*** ATDDR8 - ATD Conversion Result Register 8; 0x000000A0 ***
+ATDDR8:             equ    $000000A0                                ;*** ATDDR8 - ATD Conversion Result Register 8; 0x000000A0 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+ATDDR8_BIT6:        equ    6                                         ; Bit 6
+ATDDR8_BIT7:        equ    7                                         ; Bit 7
+ATDDR8_BIT8:        equ    8                                         ; Bit 8
+ATDDR8_BIT9:        equ    9                                         ; Bit 9
+ATDDR8_BIT10:       equ    10                                        ; Bit 10
+ATDDR8_BIT11:       equ    11                                        ; Bit 11
+ATDDR8_BIT12:       equ    12                                        ; Bit 12
+ATDDR8_BIT13:       equ    13                                        ; Bit 13
+ATDDR8_BIT14:       equ    14                                        ; Bit 14
+ATDDR8_BIT15:       equ    15                                        ; Bit 15
+; bit position masks
+mATDDR8_BIT6:       equ    %01000000
+mATDDR8_BIT7:       equ    %10000000
+mATDDR8_BIT8:       equ    %100000000
+mATDDR8_BIT9:       equ    %1000000000
+mATDDR8_BIT10:      equ    %10000000000
+mATDDR8_BIT11:      equ    %100000000000
+mATDDR8_BIT12:      equ    %1000000000000
+mATDDR8_BIT13:      equ    %10000000000000
+mATDDR8_BIT14:      equ    %100000000000000
+mATDDR8_BIT15:      equ    %1000000000000000
+
+
+;*** ATDDR8H - ATD Conversion Result Register 8 High; 0x000000A0 ***
+ATDDR8H:            equ    $000000A0                                ;*** ATDDR8H - ATD Conversion Result Register 8 High; 0x000000A0 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+ATDDR8H_BIT8:       equ    0                                         ; Bit 8
+ATDDR8H_BIT9:       equ    1                                         ; Bit 9
+ATDDR8H_BIT10:      equ    2                                         ; Bit 10
+ATDDR8H_BIT11:      equ    3                                         ; Bit 11
+ATDDR8H_BIT12:      equ    4                                         ; Bit 12
+ATDDR8H_BIT13:      equ    5                                         ; Bit 13
+ATDDR8H_BIT14:      equ    6                                         ; Bit 14
+ATDDR8H_BIT15:      equ    7                                         ; Bit 15
+; bit position masks
+mATDDR8H_BIT8:      equ    %00000001
+mATDDR8H_BIT9:      equ    %00000010
+mATDDR8H_BIT10:     equ    %00000100
+mATDDR8H_BIT11:     equ    %00001000
+mATDDR8H_BIT12:     equ    %00010000
+mATDDR8H_BIT13:     equ    %00100000
+mATDDR8H_BIT14:     equ    %01000000
+mATDDR8H_BIT15:     equ    %10000000
+
+
+;*** ATDDR8L - ATD Conversion Result Register 8 Low; 0x000000A1 ***
+ATDDR8L:            equ    $000000A1                                ;*** ATDDR8L - ATD Conversion Result Register 8 Low; 0x000000A1 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+ATDDR8L_BIT6:       equ    6                                         ; Bit 6
+ATDDR8L_BIT7:       equ    7                                         ; Bit 7
+; bit position masks
+mATDDR8L_BIT6:      equ    %01000000
+mATDDR8L_BIT7:      equ    %10000000
+
+
+;*** ATDDR9 - ATD Conversion Result Register 9; 0x000000A2 ***
+ATDDR9:             equ    $000000A2                                ;*** ATDDR9 - ATD Conversion Result Register 9; 0x000000A2 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+ATDDR9_BIT6:        equ    6                                         ; Bit 6
+ATDDR9_BIT7:        equ    7                                         ; Bit 7
+ATDDR9_BIT8:        equ    8                                         ; Bit 8
+ATDDR9_BIT9:        equ    9                                         ; Bit 9
+ATDDR9_BIT10:       equ    10                                        ; Bit 10
+ATDDR9_BIT11:       equ    11                                        ; Bit 11
+ATDDR9_BIT12:       equ    12                                        ; Bit 12
+ATDDR9_BIT13:       equ    13                                        ; Bit 13
+ATDDR9_BIT14:       equ    14                                        ; Bit 14
+ATDDR9_BIT15:       equ    15                                        ; Bit 15
+; bit position masks
+mATDDR9_BIT6:       equ    %01000000
+mATDDR9_BIT7:       equ    %10000000
+mATDDR9_BIT8:       equ    %100000000
+mATDDR9_BIT9:       equ    %1000000000
+mATDDR9_BIT10:      equ    %10000000000
+mATDDR9_BIT11:      equ    %100000000000
+mATDDR9_BIT12:      equ    %1000000000000
+mATDDR9_BIT13:      equ    %10000000000000
+mATDDR9_BIT14:      equ    %100000000000000
+mATDDR9_BIT15:      equ    %1000000000000000
+
+
+;*** ATDDR9H - ATD Conversion Result Register 9 High; 0x000000A2 ***
+ATDDR9H:            equ    $000000A2                                ;*** ATDDR9H - ATD Conversion Result Register 9 High; 0x000000A2 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+ATDDR9H_BIT8:       equ    0                                         ; Bit 8
+ATDDR9H_BIT9:       equ    1                                         ; Bit 9
+ATDDR9H_BIT10:      equ    2                                         ; Bit 10
+ATDDR9H_BIT11:      equ    3                                         ; Bit 11
+ATDDR9H_BIT12:      equ    4                                         ; Bit 12
+ATDDR9H_BIT13:      equ    5                                         ; Bit 13
+ATDDR9H_BIT14:      equ    6                                         ; Bit 14
+ATDDR9H_BIT15:      equ    7                                         ; Bit 15
+; bit position masks
+mATDDR9H_BIT8:      equ    %00000001
+mATDDR9H_BIT9:      equ    %00000010
+mATDDR9H_BIT10:     equ    %00000100
+mATDDR9H_BIT11:     equ    %00001000
+mATDDR9H_BIT12:     equ    %00010000
+mATDDR9H_BIT13:     equ    %00100000
+mATDDR9H_BIT14:     equ    %01000000
+mATDDR9H_BIT15:     equ    %10000000
+
+
+;*** ATDDR9L - ATD Conversion Result Register 9 Low; 0x000000A3 ***
+ATDDR9L:            equ    $000000A3                                ;*** ATDDR9L - ATD Conversion Result Register 9 Low; 0x000000A3 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+ATDDR9L_BIT6:       equ    6                                         ; Bit 6
+ATDDR9L_BIT7:       equ    7                                         ; Bit 7
+; bit position masks
+mATDDR9L_BIT6:      equ    %01000000
+mATDDR9L_BIT7:      equ    %10000000
+
+
+;*** ATDDR10 - ATD Conversion Result Register 10; 0x000000A4 ***
+ATDDR10:            equ    $000000A4                                ;*** ATDDR10 - ATD Conversion Result Register 10; 0x000000A4 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+ATDDR10_BIT6:       equ    6                                         ; Bit 6
+ATDDR10_BIT7:       equ    7                                         ; Bit 7
+ATDDR10_BIT8:       equ    8                                         ; Bit 8
+ATDDR10_BIT9:       equ    9                                         ; Bit 9
+ATDDR10_BIT10:      equ    10                                        ; Bit 10
+ATDDR10_BIT11:      equ    11                                        ; Bit 11
+ATDDR10_BIT12:      equ    12                                        ; Bit 12
+ATDDR10_BIT13:      equ    13                                        ; Bit 13
+ATDDR10_BIT14:      equ    14                                        ; Bit 14
+ATDDR10_BIT15:      equ    15                                        ; Bit 15
+; bit position masks
+mATDDR10_BIT6:      equ    %01000000
+mATDDR10_BIT7:      equ    %10000000
+mATDDR10_BIT8:      equ    %100000000
+mATDDR10_BIT9:      equ    %1000000000
+mATDDR10_BIT10:     equ    %10000000000
+mATDDR10_BIT11:     equ    %100000000000
+mATDDR10_BIT12:     equ    %1000000000000
+mATDDR10_BIT13:     equ    %10000000000000
+mATDDR10_BIT14:     equ    %100000000000000
+mATDDR10_BIT15:     equ    %1000000000000000
+
+
+;*** ATDDR10H - ATD Conversion Result Register 10 High; 0x000000A4 ***
+ATDDR10H:           equ    $000000A4                                ;*** ATDDR10H - ATD Conversion Result Register 10 High; 0x000000A4 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+ATDDR10H_BIT8:      equ    0                                         ; Bit 8
+ATDDR10H_BIT9:      equ    1                                         ; Bit 9
+ATDDR10H_BIT10:     equ    2                                         ; Bit 10
+ATDDR10H_BIT11:     equ    3                                         ; Bit 11
+ATDDR10H_BIT12:     equ    4                                         ; Bit 12
+ATDDR10H_BIT13:     equ    5                                         ; Bit 13
+ATDDR10H_BIT14:     equ    6                                         ; Bit 14
+ATDDR10H_BIT15:     equ    7                                         ; Bit 15
+; bit position masks
+mATDDR10H_BIT8:     equ    %00000001
+mATDDR10H_BIT9:     equ    %00000010
+mATDDR10H_BIT10:    equ    %00000100
+mATDDR10H_BIT11:    equ    %00001000
+mATDDR10H_BIT12:    equ    %00010000
+mATDDR10H_BIT13:    equ    %00100000
+mATDDR10H_BIT14:    equ    %01000000
+mATDDR10H_BIT15:    equ    %10000000
+
+
+;*** ATDDR10L - ATD Conversion Result Register 10 Low; 0x000000A5 ***
+ATDDR10L:           equ    $000000A5                                ;*** ATDDR10L - ATD Conversion Result Register 10 Low; 0x000000A5 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+ATDDR10L_BIT6:      equ    6                                         ; Bit 6
+ATDDR10L_BIT7:      equ    7                                         ; Bit 7
+; bit position masks
+mATDDR10L_BIT6:     equ    %01000000
+mATDDR10L_BIT7:     equ    %10000000
+
+
+;*** ATDDR11 - ATD Conversion Result Register 11; 0x000000A6 ***
+ATDDR11:            equ    $000000A6                                ;*** ATDDR11 - ATD Conversion Result Register 11; 0x000000A6 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+ATDDR11_BIT6:       equ    6                                         ; Bit 6
+ATDDR11_BIT7:       equ    7                                         ; Bit 7
+ATDDR11_BIT8:       equ    8                                         ; Bit 8
+ATDDR11_BIT9:       equ    9                                         ; Bit 9
+ATDDR11_BIT10:      equ    10                                        ; Bit 10
+ATDDR11_BIT11:      equ    11                                        ; Bit 11
+ATDDR11_BIT12:      equ    12                                        ; Bit 12
+ATDDR11_BIT13:      equ    13                                        ; Bit 13
+ATDDR11_BIT14:      equ    14                                        ; Bit 14
+ATDDR11_BIT15:      equ    15                                        ; Bit 15
+; bit position masks
+mATDDR11_BIT6:      equ    %01000000
+mATDDR11_BIT7:      equ    %10000000
+mATDDR11_BIT8:      equ    %100000000
+mATDDR11_BIT9:      equ    %1000000000
+mATDDR11_BIT10:     equ    %10000000000
+mATDDR11_BIT11:     equ    %100000000000
+mATDDR11_BIT12:     equ    %1000000000000
+mATDDR11_BIT13:     equ    %10000000000000
+mATDDR11_BIT14:     equ    %100000000000000
+mATDDR11_BIT15:     equ    %1000000000000000
+
+
+;*** ATDDR11H - ATD Conversion Result Register 11 High; 0x000000A6 ***
+ATDDR11H:           equ    $000000A6                                ;*** ATDDR11H - ATD Conversion Result Register 11 High; 0x000000A6 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+ATDDR11H_BIT8:      equ    0                                         ; Bit 8
+ATDDR11H_BIT9:      equ    1                                         ; Bit 9
+ATDDR11H_BIT10:     equ    2                                         ; Bit 10
+ATDDR11H_BIT11:     equ    3                                         ; Bit 11
+ATDDR11H_BIT12:     equ    4                                         ; Bit 12
+ATDDR11H_BIT13:     equ    5                                         ; Bit 13
+ATDDR11H_BIT14:     equ    6                                         ; Bit 14
+ATDDR11H_BIT15:     equ    7                                         ; Bit 15
+; bit position masks
+mATDDR11H_BIT8:     equ    %00000001
+mATDDR11H_BIT9:     equ    %00000010
+mATDDR11H_BIT10:    equ    %00000100
+mATDDR11H_BIT11:    equ    %00001000
+mATDDR11H_BIT12:    equ    %00010000
+mATDDR11H_BIT13:    equ    %00100000
+mATDDR11H_BIT14:    equ    %01000000
+mATDDR11H_BIT15:    equ    %10000000
+
+
+;*** ATDDR11L - ATD Conversion Result Register 11 Low; 0x000000A7 ***
+ATDDR11L:           equ    $000000A7                                ;*** ATDDR11L - ATD Conversion Result Register 11 Low; 0x000000A7 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+ATDDR11L_BIT6:      equ    6                                         ; Bit 6
+ATDDR11L_BIT7:      equ    7                                         ; Bit 7
+; bit position masks
+mATDDR11L_BIT6:     equ    %01000000
+mATDDR11L_BIT7:     equ    %10000000
+
+
+;*** ATDDR12 - ATD Conversion Result Register 12; 0x000000A8 ***
+ATDDR12:            equ    $000000A8                                ;*** ATDDR12 - ATD Conversion Result Register 12; 0x000000A8 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+ATDDR12_BIT6:       equ    6                                         ; Bit 6
+ATDDR12_BIT7:       equ    7                                         ; Bit 7
+ATDDR12_BIT8:       equ    8                                         ; Bit 8
+ATDDR12_BIT9:       equ    9                                         ; Bit 9
+ATDDR12_BIT10:      equ    10                                        ; Bit 10
+ATDDR12_BIT11:      equ    11                                        ; Bit 11
+ATDDR12_BIT12:      equ    12                                        ; Bit 12
+ATDDR12_BIT13:      equ    13                                        ; Bit 13
+ATDDR12_BIT14:      equ    14                                        ; Bit 14
+ATDDR12_BIT15:      equ    15                                        ; Bit 15
+; bit position masks
+mATDDR12_BIT6:      equ    %01000000
+mATDDR12_BIT7:      equ    %10000000
+mATDDR12_BIT8:      equ    %100000000
+mATDDR12_BIT9:      equ    %1000000000
+mATDDR12_BIT10:     equ    %10000000000
+mATDDR12_BIT11:     equ    %100000000000
+mATDDR12_BIT12:     equ    %1000000000000
+mATDDR12_BIT13:     equ    %10000000000000
+mATDDR12_BIT14:     equ    %100000000000000
+mATDDR12_BIT15:     equ    %1000000000000000
+
+
+;*** ATDDR12H - ATD Conversion Result Register 12 High; 0x000000A8 ***
+ATDDR12H:           equ    $000000A8                                ;*** ATDDR12H - ATD Conversion Result Register 12 High; 0x000000A8 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+ATDDR12H_BIT8:      equ    0                                         ; Bit 8
+ATDDR12H_BIT9:      equ    1                                         ; Bit 9
+ATDDR12H_BIT10:     equ    2                                         ; Bit 10
+ATDDR12H_BIT11:     equ    3                                         ; Bit 11
+ATDDR12H_BIT12:     equ    4                                         ; Bit 12
+ATDDR12H_BIT13:     equ    5                                         ; Bit 13
+ATDDR12H_BIT14:     equ    6                                         ; Bit 14
+ATDDR12H_BIT15:     equ    7                                         ; Bit 15
+; bit position masks
+mATDDR12H_BIT8:     equ    %00000001
+mATDDR12H_BIT9:     equ    %00000010
+mATDDR12H_BIT10:    equ    %00000100
+mATDDR12H_BIT11:    equ    %00001000
+mATDDR12H_BIT12:    equ    %00010000
+mATDDR12H_BIT13:    equ    %00100000
+mATDDR12H_BIT14:    equ    %01000000
+mATDDR12H_BIT15:    equ    %10000000
+
+
+;*** ATDDR12L - ATD Conversion Result Register 12 Low; 0x000000A9 ***
+ATDDR12L:           equ    $000000A9                                ;*** ATDDR12L - ATD Conversion Result Register 12 Low; 0x000000A9 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+ATDDR12L_BIT6:      equ    6                                         ; Bit 6
+ATDDR12L_BIT7:      equ    7                                         ; Bit 7
+; bit position masks
+mATDDR12L_BIT6:     equ    %01000000
+mATDDR12L_BIT7:     equ    %10000000
+
+
+;*** ATDDR13 - ATD Conversion Result Register 13; 0x000000AA ***
+ATDDR13:            equ    $000000AA                                ;*** ATDDR13 - ATD Conversion Result Register 13; 0x000000AA ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+ATDDR13_BIT6:       equ    6                                         ; Bit 6
+ATDDR13_BIT7:       equ    7                                         ; Bit 7
+ATDDR13_BIT8:       equ    8                                         ; Bit 8
+ATDDR13_BIT9:       equ    9                                         ; Bit 9
+ATDDR13_BIT10:      equ    10                                        ; Bit 10
+ATDDR13_BIT11:      equ    11                                        ; Bit 11
+ATDDR13_BIT12:      equ    12                                        ; Bit 12
+ATDDR13_BIT13:      equ    13                                        ; Bit 13
+ATDDR13_BIT14:      equ    14                                        ; Bit 14
+ATDDR13_BIT15:      equ    15                                        ; Bit 15
+; bit position masks
+mATDDR13_BIT6:      equ    %01000000
+mATDDR13_BIT7:      equ    %10000000
+mATDDR13_BIT8:      equ    %100000000
+mATDDR13_BIT9:      equ    %1000000000
+mATDDR13_BIT10:     equ    %10000000000
+mATDDR13_BIT11:     equ    %100000000000
+mATDDR13_BIT12:     equ    %1000000000000
+mATDDR13_BIT13:     equ    %10000000000000
+mATDDR13_BIT14:     equ    %100000000000000
+mATDDR13_BIT15:     equ    %1000000000000000
+
+
+;*** ATDDR13H - ATD Conversion Result Register 13 High; 0x000000AA ***
+ATDDR13H:           equ    $000000AA                                ;*** ATDDR13H - ATD Conversion Result Register 13 High; 0x000000AA ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+ATDDR13H_BIT8:      equ    0                                         ; Bit 8
+ATDDR13H_BIT9:      equ    1                                         ; Bit 9
+ATDDR13H_BIT10:     equ    2                                         ; Bit 10
+ATDDR13H_BIT11:     equ    3                                         ; Bit 11
+ATDDR13H_BIT12:     equ    4                                         ; Bit 12
+ATDDR13H_BIT13:     equ    5                                         ; Bit 13
+ATDDR13H_BIT14:     equ    6                                         ; Bit 14
+ATDDR13H_BIT15:     equ    7                                         ; Bit 15
+; bit position masks
+mATDDR13H_BIT8:     equ    %00000001
+mATDDR13H_BIT9:     equ    %00000010
+mATDDR13H_BIT10:    equ    %00000100
+mATDDR13H_BIT11:    equ    %00001000
+mATDDR13H_BIT12:    equ    %00010000
+mATDDR13H_BIT13:    equ    %00100000
+mATDDR13H_BIT14:    equ    %01000000
+mATDDR13H_BIT15:    equ    %10000000
+
+
+;*** ATDDR13L - ATD Conversion Result Register 13 Low; 0x000000AB ***
+ATDDR13L:           equ    $000000AB                                ;*** ATDDR13L - ATD Conversion Result Register 13 Low; 0x000000AB ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+ATDDR13L_BIT6:      equ    6                                         ; Bit 6
+ATDDR13L_BIT7:      equ    7                                         ; Bit 7
+; bit position masks
+mATDDR13L_BIT6:     equ    %01000000
+mATDDR13L_BIT7:     equ    %10000000
+
+
+;*** ATDDR14 - ATD Conversion Result Register 14; 0x000000AC ***
+ATDDR14:            equ    $000000AC                                ;*** ATDDR14 - ATD Conversion Result Register 14; 0x000000AC ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+ATDDR14_BIT6:       equ    6                                         ; Bit 6
+ATDDR14_BIT7:       equ    7                                         ; Bit 7
+ATDDR14_BIT8:       equ    8                                         ; Bit 8
+ATDDR14_BIT9:       equ    9                                         ; Bit 9
+ATDDR14_BIT10:      equ    10                                        ; Bit 10
+ATDDR14_BIT11:      equ    11                                        ; Bit 11
+ATDDR14_BIT12:      equ    12                                        ; Bit 12
+ATDDR14_BIT13:      equ    13                                        ; Bit 13
+ATDDR14_BIT14:      equ    14                                        ; Bit 14
+ATDDR14_BIT15:      equ    15                                        ; Bit 15
+; bit position masks
+mATDDR14_BIT6:      equ    %01000000
+mATDDR14_BIT7:      equ    %10000000
+mATDDR14_BIT8:      equ    %100000000
+mATDDR14_BIT9:      equ    %1000000000
+mATDDR14_BIT10:     equ    %10000000000
+mATDDR14_BIT11:     equ    %100000000000
+mATDDR14_BIT12:     equ    %1000000000000
+mATDDR14_BIT13:     equ    %10000000000000
+mATDDR14_BIT14:     equ    %100000000000000
+mATDDR14_BIT15:     equ    %1000000000000000
+
+
+;*** ATDDR14H - ATD Conversion Result Register 14 High; 0x000000AC ***
+ATDDR14H:           equ    $000000AC                                ;*** ATDDR14H - ATD Conversion Result Register 14 High; 0x000000AC ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+ATDDR14H_BIT8:      equ    0                                         ; Bit 8
+ATDDR14H_BIT9:      equ    1                                         ; Bit 9
+ATDDR14H_BIT10:     equ    2                                         ; Bit 10
+ATDDR14H_BIT11:     equ    3                                         ; Bit 11
+ATDDR14H_BIT12:     equ    4                                         ; Bit 12
+ATDDR14H_BIT13:     equ    5                                         ; Bit 13
+ATDDR14H_BIT14:     equ    6                                         ; Bit 14
+ATDDR14H_BIT15:     equ    7                                         ; Bit 15
+; bit position masks
+mATDDR14H_BIT8:     equ    %00000001
+mATDDR14H_BIT9:     equ    %00000010
+mATDDR14H_BIT10:    equ    %00000100
+mATDDR14H_BIT11:    equ    %00001000
+mATDDR14H_BIT12:    equ    %00010000
+mATDDR14H_BIT13:    equ    %00100000
+mATDDR14H_BIT14:    equ    %01000000
+mATDDR14H_BIT15:    equ    %10000000
+
+
+;*** ATDDR14L - ATD Conversion Result Register 14 Low; 0x000000AD ***
+ATDDR14L:           equ    $000000AD                                ;*** ATDDR14L - ATD Conversion Result Register 14 Low; 0x000000AD ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+ATDDR14L_BIT6:      equ    6                                         ; Bit 6
+ATDDR14L_BIT7:      equ    7                                         ; Bit 7
+; bit position masks
+mATDDR14L_BIT6:     equ    %01000000
+mATDDR14L_BIT7:     equ    %10000000
+
+
+;*** ATDDR15 - ATD Conversion Result Register 15; 0x000000AE ***
+ATDDR15:            equ    $000000AE                                ;*** ATDDR15 - ATD Conversion Result Register 15; 0x000000AE ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+ATDDR15_BIT6:       equ    6                                         ; Bit 6
+ATDDR15_BIT7:       equ    7                                         ; Bit 7
+ATDDR15_BIT8:       equ    8                                         ; Bit 8
+ATDDR15_BIT9:       equ    9                                         ; Bit 9
+ATDDR15_BIT10:      equ    10                                        ; Bit 10
+ATDDR15_BIT11:      equ    11                                        ; Bit 11
+ATDDR15_BIT12:      equ    12                                        ; Bit 12
+ATDDR15_BIT13:      equ    13                                        ; Bit 13
+ATDDR15_BIT14:      equ    14                                        ; Bit 14
+ATDDR15_BIT15:      equ    15                                        ; Bit 15
+; bit position masks
+mATDDR15_BIT6:      equ    %01000000
+mATDDR15_BIT7:      equ    %10000000
+mATDDR15_BIT8:      equ    %100000000
+mATDDR15_BIT9:      equ    %1000000000
+mATDDR15_BIT10:     equ    %10000000000
+mATDDR15_BIT11:     equ    %100000000000
+mATDDR15_BIT12:     equ    %1000000000000
+mATDDR15_BIT13:     equ    %10000000000000
+mATDDR15_BIT14:     equ    %100000000000000
+mATDDR15_BIT15:     equ    %1000000000000000
+
+
+;*** ATDDR15H - ATD Conversion Result Register 15 High; 0x000000AE ***
+ATDDR15H:           equ    $000000AE                                ;*** ATDDR15H - ATD Conversion Result Register 15 High; 0x000000AE ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+ATDDR15H_BIT8:      equ    0                                         ; Bit 8
+ATDDR15H_BIT9:      equ    1                                         ; Bit 9
+ATDDR15H_BIT10:     equ    2                                         ; Bit 10
+ATDDR15H_BIT11:     equ    3                                         ; Bit 11
+ATDDR15H_BIT12:     equ    4                                         ; Bit 12
+ATDDR15H_BIT13:     equ    5                                         ; Bit 13
+ATDDR15H_BIT14:     equ    6                                         ; Bit 14
+ATDDR15H_BIT15:     equ    7                                         ; Bit 15
+; bit position masks
+mATDDR15H_BIT8:     equ    %00000001
+mATDDR15H_BIT9:     equ    %00000010
+mATDDR15H_BIT10:    equ    %00000100
+mATDDR15H_BIT11:    equ    %00001000
+mATDDR15H_BIT12:    equ    %00010000
+mATDDR15H_BIT13:    equ    %00100000
+mATDDR15H_BIT14:    equ    %01000000
+mATDDR15H_BIT15:    equ    %10000000
+
+
+;*** ATDDR15L - ATD Conversion Result Register 15 Low; 0x000000AF ***
+ATDDR15L:           equ    $000000AF                                ;*** ATDDR15L - ATD Conversion Result Register 15 Low; 0x000000AF ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+ATDDR15L_BIT6:      equ    6                                         ; Bit 6
+ATDDR15L_BIT7:      equ    7                                         ; Bit 7
+; bit position masks
+mATDDR15L_BIT6:     equ    %01000000
+mATDDR15L_BIT7:     equ    %10000000
+
+
+;*** SCI0BD - SCI 0 Baud Rate Register; 0x000000C8 ***
+SCI0BD:             equ    $000000C8                                ;*** SCI0BD - SCI 0 Baud Rate Register; 0x000000C8 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+SCI0BD_SBR0:        equ    0                                         ; SCI Baud Rate Bit 0
+SCI0BD_SBR1:        equ    1                                         ; SCI Baud Rate Bit 1
+SCI0BD_SBR2:        equ    2                                         ; SCI Baud Rate Bit 2
+SCI0BD_SBR3:        equ    3                                         ; SCI Baud Rate Bit 3
+SCI0BD_SBR4:        equ    4                                         ; SCI Baud Rate Bit 4
+SCI0BD_SBR5:        equ    5                                         ; SCI Baud Rate Bit 5
+SCI0BD_SBR6:        equ    6                                         ; SCI Baud Rate Bit 6
+SCI0BD_SBR7:        equ    7                                         ; SCI Baud Rate Bit 7
+SCI0BD_SBR8:        equ    8                                         ; SCI Baud Rate Bit 8
+SCI0BD_SBR9:        equ    9                                         ; SCI Baud Rate Bit 9
+SCI0BD_SBR10:       equ    10                                        ; SCI Baud Rate Bit 10
+SCI0BD_SBR11:       equ    11                                        ; SCI Baud Rate Bit 11
+SCI0BD_SBR12:       equ    12                                        ; SCI Baud Rate Bit 12
+SCI0BD_TNP0:        equ    13                                        ; Transmitter Narrow Pulse Bit 0
+SCI0BD_TNP1:        equ    14                                        ; Transmitter Narrow Pulse Bit 1
+SCI0BD_IREN:        equ    15                                        ; Infrared Enable Bit
+; bit position masks
+mSCI0BD_SBR0:       equ    %00000001
+mSCI0BD_SBR1:       equ    %00000010
+mSCI0BD_SBR2:       equ    %00000100
+mSCI0BD_SBR3:       equ    %00001000
+mSCI0BD_SBR4:       equ    %00010000
+mSCI0BD_SBR5:       equ    %00100000
+mSCI0BD_SBR6:       equ    %01000000
+mSCI0BD_SBR7:       equ    %10000000
+mSCI0BD_SBR8:       equ    %100000000
+mSCI0BD_SBR9:       equ    %1000000000
+mSCI0BD_SBR10:      equ    %10000000000
+mSCI0BD_SBR11:      equ    %100000000000
+mSCI0BD_SBR12:      equ    %1000000000000
+mSCI0BD_TNP0:       equ    %10000000000000
+mSCI0BD_TNP1:       equ    %100000000000000
+mSCI0BD_IREN:       equ    %1000000000000000
+
+
+;*** SCI0BDH - SCI 0 Baud Rate Register High; 0x000000C8 ***
+SCI0BDH:            equ    $000000C8                                ;*** SCI0BDH - SCI 0 Baud Rate Register High; 0x000000C8 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+SCI0BDH_SBR8:       equ    0                                         ; SCI Baud Rate Bit 8
+SCI0BDH_SBR9:       equ    1                                         ; SCI Baud Rate Bit 9
+SCI0BDH_SBR10:      equ    2                                         ; SCI Baud Rate Bit 10
+SCI0BDH_SBR11:      equ    3                                         ; SCI Baud Rate Bit 11
+SCI0BDH_SBR12:      equ    4                                         ; SCI Baud Rate Bit 12
+SCI0BDH_TNP0:       equ    5                                         ; Transmitter Narrow Pulse Bit 0
+SCI0BDH_TNP1:       equ    6                                         ; Transmitter Narrow Pulse Bit 1
+SCI0BDH_IREN:       equ    7                                         ; Infrared Enable Bit
+; bit position masks
+mSCI0BDH_SBR8:      equ    %00000001
+mSCI0BDH_SBR9:      equ    %00000010
+mSCI0BDH_SBR10:     equ    %00000100
+mSCI0BDH_SBR11:     equ    %00001000
+mSCI0BDH_SBR12:     equ    %00010000
+mSCI0BDH_TNP0:      equ    %00100000
+mSCI0BDH_TNP1:      equ    %01000000
+mSCI0BDH_IREN:      equ    %10000000
+
+
+;*** SCI0BDL - SCI 0 Baud Rate Register Low; 0x000000C9 ***
+SCI0BDL:            equ    $000000C9                                ;*** SCI0BDL - SCI 0 Baud Rate Register Low; 0x000000C9 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+SCI0BDL_SBR0:       equ    0                                         ; SCI Baud Rate Bit 0
+SCI0BDL_SBR1:       equ    1                                         ; SCI Baud Rate Bit 1
+SCI0BDL_SBR2:       equ    2                                         ; SCI Baud Rate Bit 2
+SCI0BDL_SBR3:       equ    3                                         ; SCI Baud Rate Bit 3
+SCI0BDL_SBR4:       equ    4                                         ; SCI Baud Rate Bit 4
+SCI0BDL_SBR5:       equ    5                                         ; SCI Baud Rate Bit 5
+SCI0BDL_SBR6:       equ    6                                         ; SCI Baud Rate Bit 6
+SCI0BDL_SBR7:       equ    7                                         ; SCI Baud Rate Bit 7
+; bit position masks
+mSCI0BDL_SBR0:      equ    %00000001
+mSCI0BDL_SBR1:      equ    %00000010
+mSCI0BDL_SBR2:      equ    %00000100
+mSCI0BDL_SBR3:      equ    %00001000
+mSCI0BDL_SBR4:      equ    %00010000
+mSCI0BDL_SBR5:      equ    %00100000
+mSCI0BDL_SBR6:      equ    %01000000
+mSCI0BDL_SBR7:      equ    %10000000
+
+
+;*** SCI0CR1 - SCI 0 Control Register 1; 0x000000CA ***
+SCI0CR1:            equ    $000000CA                                ;*** SCI0CR1 - SCI 0 Control Register 1; 0x000000CA ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+SCI0CR1_PT:         equ    0                                         ; Parity Type Bit
+SCI0CR1_PE:         equ    1                                         ; Parity Enable Bit
+SCI0CR1_ILT:        equ    2                                         ; Idle Line Type Bit
+SCI0CR1_WAKE:       equ    3                                         ; Wakeup Condition Bit
+SCI0CR1_M:          equ    4                                         ; Data Format Mode Bit
+SCI0CR1_RSRC:       equ    5                                         ; Receiver Source Bit
+SCI0CR1_SCISWAI:    equ    6                                         ; SCI Stop in Wait Mode Bit
+SCI0CR1_LOOPS:      equ    7                                         ; Loop Select Bit
+; bit position masks
+mSCI0CR1_PT:        equ    %00000001
+mSCI0CR1_PE:        equ    %00000010
+mSCI0CR1_ILT:       equ    %00000100
+mSCI0CR1_WAKE:      equ    %00001000
+mSCI0CR1_M:         equ    %00010000
+mSCI0CR1_RSRC:      equ    %00100000
+mSCI0CR1_SCISWAI:   equ    %01000000
+mSCI0CR1_LOOPS:     equ    %10000000
+
+
+;*** SCI0CR2 - SCI 0 Control Register 2; 0x000000CB ***
+SCI0CR2:            equ    $000000CB                                ;*** SCI0CR2 - SCI 0 Control Register 2; 0x000000CB ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+SCI0CR2_SBK:        equ    0                                         ; Send Break Bit
+SCI0CR2_RWU:        equ    1                                         ; Receiver Wakeup Bit
+SCI0CR2_RE:         equ    2                                         ; Receiver Enable Bit
+SCI0CR2_TE:         equ    3                                         ; Transmitter Enable Bit
+SCI0CR2_ILIE:       equ    4                                         ; Idle Line Interrupt Enable Bit
+SCI0CR2_RIE:        equ    5                                         ; Receiver Full Interrupt Enable Bit
+SCI0CR2_TCIE:       equ    6                                         ; Transmission Complete Interrupt Enable Bit
+SCI0CR2_SCTIE:      equ    7                                         ; Transmitter Interrupt Enable Bit
+; bit position masks
+mSCI0CR2_SBK:       equ    %00000001
+mSCI0CR2_RWU:       equ    %00000010
+mSCI0CR2_RE:        equ    %00000100
+mSCI0CR2_TE:        equ    %00001000
+mSCI0CR2_ILIE:      equ    %00010000
+mSCI0CR2_RIE:       equ    %00100000
+mSCI0CR2_TCIE:      equ    %01000000
+mSCI0CR2_SCTIE:     equ    %10000000
+
+
+;*** SCI0SR1 - SCI 0 Status Register 1; 0x000000CC ***
+SCI0SR1:            equ    $000000CC                                ;*** SCI0SR1 - SCI 0 Status Register 1; 0x000000CC ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+SCI0SR1_PF:         equ    0                                         ; Parity Error Flag
+SCI0SR1_FE:         equ    1                                         ; Framing Error Flag
+SCI0SR1_NF:         equ    2                                         ; Noise Flag
+SCI0SR1_OR:         equ    3                                         ; Overrun Flag
+SCI0SR1_IDLE:       equ    4                                         ; Idle Line Flag
+SCI0SR1_RDRF:       equ    5                                         ; Receive Data Register Full Flag
+SCI0SR1_TC:         equ    6                                         ; Transmit Complete Flag
+SCI0SR1_TDRE:       equ    7                                         ; Transmit Data Register Empty Flag
+; bit position masks
+mSCI0SR1_PF:        equ    %00000001
+mSCI0SR1_FE:        equ    %00000010
+mSCI0SR1_NF:        equ    %00000100
+mSCI0SR1_OR:        equ    %00001000
+mSCI0SR1_IDLE:      equ    %00010000
+mSCI0SR1_RDRF:      equ    %00100000
+mSCI0SR1_TC:        equ    %01000000
+mSCI0SR1_TDRE:      equ    %10000000
+
+
+;*** SCI0SR2 - SCI 0 Status Register 2; 0x000000CD ***
+SCI0SR2:            equ    $000000CD                                ;*** SCI0SR2 - SCI 0 Status Register 2; 0x000000CD ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+SCI0SR2_RAF:        equ    0                                         ; Receiver Active Flag
+SCI0SR2_TXDIR:      equ    1                                         ; Transmitter pin data direction in Single-Wire mode
+SCI0SR2_BRK13:      equ    2                                         ; Break Transmit character length
+; bit position masks
+mSCI0SR2_RAF:       equ    %00000001
+mSCI0SR2_TXDIR:     equ    %00000010
+mSCI0SR2_BRK13:     equ    %00000100
+
+
+;*** SCI0DRH - SCI 0 Data Register High; 0x000000CE ***
+SCI0DRH:            equ    $000000CE                                ;*** SCI0DRH - SCI 0 Data Register High; 0x000000CE ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+SCI0DRH_T8:         equ    6                                         ; Transmit Bit 8
+SCI0DRH_R8:         equ    7                                         ; Received Bit 8
+; bit position masks
+mSCI0DRH_T8:        equ    %01000000
+mSCI0DRH_R8:        equ    %10000000
+
+
+;*** SCI0DRL - SCI 0 Data Register Low; 0x000000CF ***
+SCI0DRL:            equ    $000000CF                                ;*** SCI0DRL - SCI 0 Data Register Low; 0x000000CF ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+SCI0DRL_R0_T0:      equ    0                                         ; Received bit 0 or Transmit bit 0
+SCI0DRL_R1_T1:      equ    1                                         ; Received bit 1 or Transmit bit 1
+SCI0DRL_R2_T2:      equ    2                                         ; Received bit 2 or Transmit bit 2
+SCI0DRL_R3_T3:      equ    3                                         ; Received bit 3 or Transmit bit 3
+SCI0DRL_R4_T4:      equ    4                                         ; Received bit 4 or Transmit bit 4
+SCI0DRL_R5_T5:      equ    5                                         ; Received bit 5 or Transmit bit 5
+SCI0DRL_R6_T6:      equ    6                                         ; Received bit 6 or Transmit bit 6
+SCI0DRL_R7_T7:      equ    7                                         ; Received bit 7 or Transmit bit 7
+; bit position masks
+mSCI0DRL_R0_T0:     equ    %00000001
+mSCI0DRL_R1_T1:     equ    %00000010
+mSCI0DRL_R2_T2:     equ    %00000100
+mSCI0DRL_R3_T3:     equ    %00001000
+mSCI0DRL_R4_T4:     equ    %00010000
+mSCI0DRL_R5_T5:     equ    %00100000
+mSCI0DRL_R6_T6:     equ    %01000000
+mSCI0DRL_R7_T7:     equ    %10000000
+
+
+;*** SCI1BD - SCI 1 Baud Rate Register; 0x000000D0 ***
+SCI1BD:             equ    $000000D0                                ;*** SCI1BD - SCI 1 Baud Rate Register; 0x000000D0 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+SCI1BD_SBR0:        equ    0                                         ; SCI Baud Rate Bit 0
+SCI1BD_SBR1:        equ    1                                         ; SCI Baud Rate Bit 1
+SCI1BD_SBR2:        equ    2                                         ; SCI Baud Rate Bit 2
+SCI1BD_SBR3:        equ    3                                         ; SCI Baud Rate Bit 3
+SCI1BD_SBR4:        equ    4                                         ; SCI Baud Rate Bit 4
+SCI1BD_SBR5:        equ    5                                         ; SCI Baud Rate Bit 5
+SCI1BD_SBR6:        equ    6                                         ; SCI Baud Rate Bit 6
+SCI1BD_SBR7:        equ    7                                         ; SCI Baud Rate Bit 7
+SCI1BD_SBR8:        equ    8                                         ; SCI Baud Rate Bit 8
+SCI1BD_SBR9:        equ    9                                         ; SCI Baud Rate Bit 9
+SCI1BD_SBR10:       equ    10                                        ; SCI Baud Rate Bit 10
+SCI1BD_SBR11:       equ    11                                        ; SCI Baud Rate Bit 11
+SCI1BD_SBR12:       equ    12                                        ; SCI Baud Rate Bit 12
+SCI1BD_TNP0:        equ    13                                        ; Transmitter Narrow Pulse Bit 0
+SCI1BD_TNP1:        equ    14                                        ; Transmitter Narrow Pulse Bit 1
+SCI1BD_IREN:        equ    15                                        ; Infrared Enable Bit
+; bit position masks
+mSCI1BD_SBR0:       equ    %00000001
+mSCI1BD_SBR1:       equ    %00000010
+mSCI1BD_SBR2:       equ    %00000100
+mSCI1BD_SBR3:       equ    %00001000
+mSCI1BD_SBR4:       equ    %00010000
+mSCI1BD_SBR5:       equ    %00100000
+mSCI1BD_SBR6:       equ    %01000000
+mSCI1BD_SBR7:       equ    %10000000
+mSCI1BD_SBR8:       equ    %100000000
+mSCI1BD_SBR9:       equ    %1000000000
+mSCI1BD_SBR10:      equ    %10000000000
+mSCI1BD_SBR11:      equ    %100000000000
+mSCI1BD_SBR12:      equ    %1000000000000
+mSCI1BD_TNP0:       equ    %10000000000000
+mSCI1BD_TNP1:       equ    %100000000000000
+mSCI1BD_IREN:       equ    %1000000000000000
+
+
+;*** SCI1BDH - SCI 1 Baud Rate Register High; 0x000000D0 ***
+SCI1BDH:            equ    $000000D0                                ;*** SCI1BDH - SCI 1 Baud Rate Register High; 0x000000D0 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+SCI1BDH_SBR8:       equ    0                                         ; SCI Baud Rate Bit 8
+SCI1BDH_SBR9:       equ    1                                         ; SCI Baud Rate Bit 9
+SCI1BDH_SBR10:      equ    2                                         ; SCI Baud Rate Bit 10
+SCI1BDH_SBR11:      equ    3                                         ; SCI Baud Rate Bit 11
+SCI1BDH_SBR12:      equ    4                                         ; SCI Baud Rate Bit 12
+SCI1BDH_TNP0:       equ    5                                         ; Transmitter Narrow Pulse Bit 0
+SCI1BDH_TNP1:       equ    6                                         ; Transmitter Narrow Pulse Bit 1
+SCI1BDH_IREN:       equ    7                                         ; Infrared Enable Bit
+; bit position masks
+mSCI1BDH_SBR8:      equ    %00000001
+mSCI1BDH_SBR9:      equ    %00000010
+mSCI1BDH_SBR10:     equ    %00000100
+mSCI1BDH_SBR11:     equ    %00001000
+mSCI1BDH_SBR12:     equ    %00010000
+mSCI1BDH_TNP0:      equ    %00100000
+mSCI1BDH_TNP1:      equ    %01000000
+mSCI1BDH_IREN:      equ    %10000000
+
+
+;*** SCI1BDL - SCI 1 Baud Rate Register Low; 0x000000D1 ***
+SCI1BDL:            equ    $000000D1                                ;*** SCI1BDL - SCI 1 Baud Rate Register Low; 0x000000D1 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+SCI1BDL_SBR0:       equ    0                                         ; SCI Baud Rate Bit 0
+SCI1BDL_SBR1:       equ    1                                         ; SCI Baud Rate Bit 1
+SCI1BDL_SBR2:       equ    2                                         ; SCI Baud Rate Bit 2
+SCI1BDL_SBR3:       equ    3                                         ; SCI Baud Rate Bit 3
+SCI1BDL_SBR4:       equ    4                                         ; SCI Baud Rate Bit 4
+SCI1BDL_SBR5:       equ    5                                         ; SCI Baud Rate Bit 5
+SCI1BDL_SBR6:       equ    6                                         ; SCI Baud Rate Bit 6
+SCI1BDL_SBR7:       equ    7                                         ; SCI Baud Rate Bit 7
+; bit position masks
+mSCI1BDL_SBR0:      equ    %00000001
+mSCI1BDL_SBR1:      equ    %00000010
+mSCI1BDL_SBR2:      equ    %00000100
+mSCI1BDL_SBR3:      equ    %00001000
+mSCI1BDL_SBR4:      equ    %00010000
+mSCI1BDL_SBR5:      equ    %00100000
+mSCI1BDL_SBR6:      equ    %01000000
+mSCI1BDL_SBR7:      equ    %10000000
+
+
+;*** SCI1CR1 - SCI 1 Control Register 1; 0x000000D2 ***
+SCI1CR1:            equ    $000000D2                                ;*** SCI1CR1 - SCI 1 Control Register 1; 0x000000D2 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+SCI1CR1_PT:         equ    0                                         ; Parity Type Bit
+SCI1CR1_PE:         equ    1                                         ; Parity Enable Bit
+SCI1CR1_ILT:        equ    2                                         ; Idle Line Type Bit
+SCI1CR1_WAKE:       equ    3                                         ; Wakeup Condition Bit
+SCI1CR1_M:          equ    4                                         ; Data Format Mode Bit
+SCI1CR1_RSRC:       equ    5                                         ; Receiver Source Bit
+SCI1CR1_SCISWAI:    equ    6                                         ; SCI Stop in Wait Mode Bit
+SCI1CR1_LOOPS:      equ    7                                         ; Loop Select Bit
+; bit position masks
+mSCI1CR1_PT:        equ    %00000001
+mSCI1CR1_PE:        equ    %00000010
+mSCI1CR1_ILT:       equ    %00000100
+mSCI1CR1_WAKE:      equ    %00001000
+mSCI1CR1_M:         equ    %00010000
+mSCI1CR1_RSRC:      equ    %00100000
+mSCI1CR1_SCISWAI:   equ    %01000000
+mSCI1CR1_LOOPS:     equ    %10000000
+
+
+;*** SCI1CR2 - SCI 1 Control Register 2; 0x000000D3 ***
+SCI1CR2:            equ    $000000D3                                ;*** SCI1CR2 - SCI 1 Control Register 2; 0x000000D3 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+SCI1CR2_SBK:        equ    0                                         ; Send Break Bit
+SCI1CR2_RWU:        equ    1                                         ; Receiver Wakeup Bit
+SCI1CR2_RE:         equ    2                                         ; Receiver Enable Bit
+SCI1CR2_TE:         equ    3                                         ; Transmitter Enable Bit
+SCI1CR2_ILIE:       equ    4                                         ; Idle Line Interrupt Enable Bit
+SCI1CR2_RIE:        equ    5                                         ; Receiver Full Interrupt Enable Bit
+SCI1CR2_TCIE:       equ    6                                         ; Transmission Complete Interrupt Enable Bit
+SCI1CR2_SCTIE:      equ    7                                         ; Transmitter Interrupt Enable Bit
+; bit position masks
+mSCI1CR2_SBK:       equ    %00000001
+mSCI1CR2_RWU:       equ    %00000010
+mSCI1CR2_RE:        equ    %00000100
+mSCI1CR2_TE:        equ    %00001000
+mSCI1CR2_ILIE:      equ    %00010000
+mSCI1CR2_RIE:       equ    %00100000
+mSCI1CR2_TCIE:      equ    %01000000
+mSCI1CR2_SCTIE:     equ    %10000000
+
+
+;*** SCI1SR1 - SCI 1 Status Register 1; 0x000000D4 ***
+SCI1SR1:            equ    $000000D4                                ;*** SCI1SR1 - SCI 1 Status Register 1; 0x000000D4 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+SCI1SR1_PF:         equ    0                                         ; Parity Error Flag
+SCI1SR1_FE:         equ    1                                         ; Framing Error Flag
+SCI1SR1_NF:         equ    2                                         ; Noise Flag
+SCI1SR1_OR:         equ    3                                         ; Overrun Flag
+SCI1SR1_IDLE:       equ    4                                         ; Idle Line Flag
+SCI1SR1_RDRF:       equ    5                                         ; Receive Data Register Full Flag
+SCI1SR1_TC:         equ    6                                         ; Transmit Complete Flag
+SCI1SR1_TDRE:       equ    7                                         ; Transmit Data Register Empty Flag
+; bit position masks
+mSCI1SR1_PF:        equ    %00000001
+mSCI1SR1_FE:        equ    %00000010
+mSCI1SR1_NF:        equ    %00000100
+mSCI1SR1_OR:        equ    %00001000
+mSCI1SR1_IDLE:      equ    %00010000
+mSCI1SR1_RDRF:      equ    %00100000
+mSCI1SR1_TC:        equ    %01000000
+mSCI1SR1_TDRE:      equ    %10000000
+
+
+;*** SCI1SR2 - SCI 1 Status Register 2; 0x000000D5 ***
+SCI1SR2:            equ    $000000D5                                ;*** SCI1SR2 - SCI 1 Status Register 2; 0x000000D5 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+SCI1SR2_RAF:        equ    0                                         ; Receiver Active Flag
+SCI1SR2_TXDIR:      equ    1                                         ; Transmitter pin data direction in Single-Wire mode
+SCI1SR2_BRK13:      equ    2                                         ; Break Transmit character length
+; bit position masks
+mSCI1SR2_RAF:       equ    %00000001
+mSCI1SR2_TXDIR:     equ    %00000010
+mSCI1SR2_BRK13:     equ    %00000100
+
+
+;*** SCI1DRH - SCI 1 Data Register High; 0x000000D6 ***
+SCI1DRH:            equ    $000000D6                                ;*** SCI1DRH - SCI 1 Data Register High; 0x000000D6 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+SCI1DRH_T8:         equ    6                                         ; Transmit Bit 8
+SCI1DRH_R8:         equ    7                                         ; Received Bit 8
+; bit position masks
+mSCI1DRH_T8:        equ    %01000000
+mSCI1DRH_R8:        equ    %10000000
+
+
+;*** SCI1DRL - SCI 1 Data Register Low; 0x000000D7 ***
+SCI1DRL:            equ    $000000D7                                ;*** SCI1DRL - SCI 1 Data Register Low; 0x000000D7 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+SCI1DRL_R0_T0:      equ    0                                         ; Received bit 0 or Transmit bit 0
+SCI1DRL_R1_T1:      equ    1                                         ; Received bit 1 or Transmit bit 1
+SCI1DRL_R2_T2:      equ    2                                         ; Received bit 2 or Transmit bit 2
+SCI1DRL_R3_T3:      equ    3                                         ; Received bit 3 or Transmit bit 3
+SCI1DRL_R4_T4:      equ    4                                         ; Received bit 4 or Transmit bit 4
+SCI1DRL_R5_T5:      equ    5                                         ; Received bit 5 or Transmit bit 5
+SCI1DRL_R6_T6:      equ    6                                         ; Received bit 6 or Transmit bit 6
+SCI1DRL_R7_T7:      equ    7                                         ; Received bit 7 or Transmit bit 7
+; bit position masks
+mSCI1DRL_R0_T0:     equ    %00000001
+mSCI1DRL_R1_T1:     equ    %00000010
+mSCI1DRL_R2_T2:     equ    %00000100
+mSCI1DRL_R3_T3:     equ    %00001000
+mSCI1DRL_R4_T4:     equ    %00010000
+mSCI1DRL_R5_T5:     equ    %00100000
+mSCI1DRL_R6_T6:     equ    %01000000
+mSCI1DRL_R7_T7:     equ    %10000000
+
+
+;*** SPICR1 - SPI Control Register; 0x000000D8 ***
+SPICR1:             equ    $000000D8                                ;*** SPICR1 - SPI Control Register; 0x000000D8 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+SPICR1_LSBFE:       equ    0                                         ; SPI LSB-First Enable
+SPICR1_SSOE:        equ    1                                         ; Slave Select Output Enable
+SPICR1_CPHA:        equ    2                                         ; SPI Clock Phase Bit
+SPICR1_CPOL:        equ    3                                         ; SPI Clock Polarity Bit
+SPICR1_MSTR:        equ    4                                         ; SPI Master/Slave Mode Select Bit
+SPICR1_SPTIE:       equ    5                                         ; SPI Transmit Interrupt Enable
+SPICR1_SPE:         equ    6                                         ; SPI System Enable Bit
+SPICR1_SPIE:        equ    7                                         ; SPI Interrupt Enable Bit
+; bit position masks
+mSPICR1_LSBFE:      equ    %00000001
+mSPICR1_SSOE:       equ    %00000010
+mSPICR1_CPHA:       equ    %00000100
+mSPICR1_CPOL:       equ    %00001000
+mSPICR1_MSTR:       equ    %00010000
+mSPICR1_SPTIE:      equ    %00100000
+mSPICR1_SPE:        equ    %01000000
+mSPICR1_SPIE:       equ    %10000000
+
+
+;*** SPICR2 - SPI Control Register 2; 0x000000D9 ***
+SPICR2:             equ    $000000D9                                ;*** SPICR2 - SPI Control Register 2; 0x000000D9 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+SPICR2_SPC0:        equ    0                                         ; Serial Pin Control Bit 0
+SPICR2_SPISWAI:     equ    1                                         ; SPI Stop in Wait Mode Bit
+SPICR2_BIDIROE:     equ    3                                         ; Output enable in the Bidirectional mode of operation
+SPICR2_MODFEN:      equ    4                                         ; Mode Fault Enable Bit
+; bit position masks
+mSPICR2_SPC0:       equ    %00000001
+mSPICR2_SPISWAI:    equ    %00000010
+mSPICR2_BIDIROE:    equ    %00001000
+mSPICR2_MODFEN:     equ    %00010000
+
+
+;*** SPIBR - SPI Baud Rate Register; 0x000000DA ***
+SPIBR:              equ    $000000DA                                ;*** SPIBR - SPI Baud Rate Register; 0x000000DA ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+SPIBR_SPR0:         equ    0                                         ; SPI Baud Rate Selection Bit 0
+SPIBR_SPR1:         equ    1                                         ; SPI Baud Rate Selection Bit 1
+SPIBR_SPR2:         equ    2                                         ; SPI Baud Rate Selection Bit 2
+SPIBR_SPPR0:        equ    4                                         ; SPI Baud Rate Preselection Bits 0
+SPIBR_SPPR1:        equ    5                                         ; SPI Baud Rate Preselection Bits 1
+SPIBR_SPPR2:        equ    6                                         ; SPI Baud Rate Preselection Bits 2
+; bit position masks
+mSPIBR_SPR0:        equ    %00000001
+mSPIBR_SPR1:        equ    %00000010
+mSPIBR_SPR2:        equ    %00000100
+mSPIBR_SPPR0:       equ    %00010000
+mSPIBR_SPPR1:       equ    %00100000
+mSPIBR_SPPR2:       equ    %01000000
+
+
+;*** SPISR - SPI Status Register; 0x000000DB ***
+SPISR:              equ    $000000DB                                ;*** SPISR - SPI Status Register; 0x000000DB ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+SPISR_MODF:         equ    4                                         ; Mode Fault Flag
+SPISR_SPTEF:        equ    5                                         ; SPI Transmit Empty Interrupt Flag
+SPISR_SPIF:         equ    7                                         ; SPIF Receive Interrupt Flag
+; bit position masks
+mSPISR_MODF:        equ    %00010000
+mSPISR_SPTEF:       equ    %00100000
+mSPISR_SPIF:        equ    %10000000
+
+
+;*** SPIDR - SPI Data Register; 0x000000DD ***
+SPIDR:              equ    $000000DD                                ;*** SPIDR - SPI Data Register; 0x000000DD ***
+
+
+;*** IBAD - IIC Address Register; 0x000000E0 ***
+IBAD:               equ    $000000E0                                ;*** IBAD - IIC Address Register; 0x000000E0 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+IBAD_ADR1:          equ    1                                         ; Slave Address Bit 1
+IBAD_ADR2:          equ    2                                         ; Slave Address Bit 2
+IBAD_ADR3:          equ    3                                         ; Slave Address Bit 3
+IBAD_ADR4:          equ    4                                         ; Slave Address Bit 4
+IBAD_ADR5:          equ    5                                         ; Slave Address Bit 5
+IBAD_ADR6:          equ    6                                         ; Slave Address Bit 6
+IBAD_ADR7:          equ    7                                         ; Slave Address Bit 7
+; bit position masks
+mIBAD_ADR1:         equ    %00000010
+mIBAD_ADR2:         equ    %00000100
+mIBAD_ADR3:         equ    %00001000
+mIBAD_ADR4:         equ    %00010000
+mIBAD_ADR5:         equ    %00100000
+mIBAD_ADR6:         equ    %01000000
+mIBAD_ADR7:         equ    %10000000
+
+
+;*** IBFD - IIC Frequency Divider Register; 0x000000E1 ***
+IBFD:               equ    $000000E1                                ;*** IBFD - IIC Frequency Divider Register; 0x000000E1 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+IBFD_IBC0:          equ    0                                         ; I-Bus Clock Rate 0
+IBFD_IBC1:          equ    1                                         ; I-Bus Clock Rate 1
+IBFD_IBC2:          equ    2                                         ; I-Bus Clock Rate 2
+IBFD_IBC3:          equ    3                                         ; I-Bus Clock Rate 3
+IBFD_IBC4:          equ    4                                         ; I-Bus Clock Rate 4
+IBFD_IBC5:          equ    5                                         ; I-Bus Clock Rate 5
+IBFD_IBC6:          equ    6                                         ; I-Bus Clock Rate 6
+IBFD_IBC7:          equ    7                                         ; I-Bus Clock Rate 7
+; bit position masks
+mIBFD_IBC0:         equ    %00000001
+mIBFD_IBC1:         equ    %00000010
+mIBFD_IBC2:         equ    %00000100
+mIBFD_IBC3:         equ    %00001000
+mIBFD_IBC4:         equ    %00010000
+mIBFD_IBC5:         equ    %00100000
+mIBFD_IBC6:         equ    %01000000
+mIBFD_IBC7:         equ    %10000000
+
+
+;*** IBCR - IIC Control Register; 0x000000E2 ***
+IBCR:               equ    $000000E2                                ;*** IBCR - IIC Control Register; 0x000000E2 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+IBCR_IBSWAI:        equ    0                                         ; I-Bus Interface Stop in WAIT mode
+IBCR_RSTA:          equ    2                                         ; Repeat Start
+IBCR_TXAK:          equ    3                                         ; Transmit Acknowledge enable
+IBCR_TX_RX:         equ    4                                         ; Transmit/Receive mode select bit
+IBCR_MS_SL:         equ    5                                         ; Master/Slave mode select bit
+IBCR_IBIE:          equ    6                                         ; I-Bus Interrupt Enable
+IBCR_IBEN:          equ    7                                         ; I-Bus Enable
+; bit position masks
+mIBCR_IBSWAI:       equ    %00000001
+mIBCR_RSTA:         equ    %00000100
+mIBCR_TXAK:         equ    %00001000
+mIBCR_TX_RX:        equ    %00010000
+mIBCR_MS_SL:        equ    %00100000
+mIBCR_IBIE:         equ    %01000000
+mIBCR_IBEN:         equ    %10000000
+
+
+;*** IBSR - IIC Status Register; 0x000000E3 ***
+IBSR:               equ    $000000E3                                ;*** IBSR - IIC Status Register; 0x000000E3 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+IBSR_RXAK:          equ    0                                         ; Received Acknowledge
+IBSR_IBIF:          equ    1                                         ; I-Bus Interrupt
+IBSR_SRW:           equ    2                                         ; Slave Read/Write
+IBSR_IBAL:          equ    4                                         ; Arbitration Lost
+IBSR_IBB:           equ    5                                         ; Bus busy bit
+IBSR_IAAS:          equ    6                                         ; Addressed as a slave bit
+IBSR_TCF:           equ    7                                         ; Data transferring bit
+; bit position masks
+mIBSR_RXAK:         equ    %00000001
+mIBSR_IBIF:         equ    %00000010
+mIBSR_SRW:          equ    %00000100
+mIBSR_IBAL:         equ    %00010000
+mIBSR_IBB:          equ    %00100000
+mIBSR_IAAS:         equ    %01000000
+mIBSR_TCF:          equ    %10000000
+
+
+;*** IBDR - IIC Data I/O Register; 0x000000E4 ***
+IBDR:               equ    $000000E4                                ;*** IBDR - IIC Data I/O Register; 0x000000E4 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+IBDR_D0:            equ    0                                         ; IIC Data Bit 0
+IBDR_D1:            equ    1                                         ; IIC Data Bit 1
+IBDR_D2:            equ    2                                         ; IIC Data Bit 2
+IBDR_D3:            equ    3                                         ; IIC Data Bit 3
+IBDR_D4:            equ    4                                         ; IIC Data Bit 4
+IBDR_D5:            equ    5                                         ; IIC Data Bit 5
+IBDR_D6:            equ    6                                         ; IIC Data Bit 6
+IBDR_D7:            equ    7                                         ; IIC Data Bit 7
+; bit position masks
+mIBDR_D0:           equ    %00000001
+mIBDR_D1:           equ    %00000010
+mIBDR_D2:           equ    %00000100
+mIBDR_D3:           equ    %00001000
+mIBDR_D4:           equ    %00010000
+mIBDR_D5:           equ    %00100000
+mIBDR_D6:           equ    %01000000
+mIBDR_D7:           equ    %10000000
+
+
+;*** SCI2BD - SCI 2 Baud Rate Register; 0x000000E8 ***
+SCI2BD:             equ    $000000E8                                ;*** SCI2BD - SCI 2 Baud Rate Register; 0x000000E8 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+SCI2BD_SBR0:        equ    0                                         ; SCI Baud Rate Bit 0
+SCI2BD_SBR1:        equ    1                                         ; SCI Baud Rate Bit 1
+SCI2BD_SBR2:        equ    2                                         ; SCI Baud Rate Bit 2
+SCI2BD_SBR3:        equ    3                                         ; SCI Baud Rate Bit 3
+SCI2BD_SBR4:        equ    4                                         ; SCI Baud Rate Bit 4
+SCI2BD_SBR5:        equ    5                                         ; SCI Baud Rate Bit 5
+SCI2BD_SBR6:        equ    6                                         ; SCI Baud Rate Bit 6
+SCI2BD_SBR7:        equ    7                                         ; SCI Baud Rate Bit 7
+SCI2BD_SBR8:        equ    8                                         ; SCI Baud Rate Bit 8
+SCI2BD_SBR9:        equ    9                                         ; SCI Baud Rate Bit 9
+SCI2BD_SBR10:       equ    10                                        ; SCI Baud Rate Bit 10
+SCI2BD_SBR11:       equ    11                                        ; SCI Baud Rate Bit 11
+SCI2BD_SBR12:       equ    12                                        ; SCI Baud Rate Bit 12
+SCI2BD_TNP0:        equ    13                                        ; Transmitter Narrow Pulse Bit 0
+SCI2BD_TNP1:        equ    14                                        ; Transmitter Narrow Pulse Bit 1
+SCI2BD_IREN:        equ    15                                        ; Infrared Enable Bit
+; bit position masks
+mSCI2BD_SBR0:       equ    %00000001
+mSCI2BD_SBR1:       equ    %00000010
+mSCI2BD_SBR2:       equ    %00000100
+mSCI2BD_SBR3:       equ    %00001000
+mSCI2BD_SBR4:       equ    %00010000
+mSCI2BD_SBR5:       equ    %00100000
+mSCI2BD_SBR6:       equ    %01000000
+mSCI2BD_SBR7:       equ    %10000000
+mSCI2BD_SBR8:       equ    %100000000
+mSCI2BD_SBR9:       equ    %1000000000
+mSCI2BD_SBR10:      equ    %10000000000
+mSCI2BD_SBR11:      equ    %100000000000
+mSCI2BD_SBR12:      equ    %1000000000000
+mSCI2BD_TNP0:       equ    %10000000000000
+mSCI2BD_TNP1:       equ    %100000000000000
+mSCI2BD_IREN:       equ    %1000000000000000
+
+
+;*** SCI2BDH - SCI 2 Baud Rate Register High; 0x000000E8 ***
+SCI2BDH:            equ    $000000E8                                ;*** SCI2BDH - SCI 2 Baud Rate Register High; 0x000000E8 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+SCI2BDH_SBR8:       equ    0                                         ; SCI Baud Rate Bit 8
+SCI2BDH_SBR9:       equ    1                                         ; SCI Baud Rate Bit 9
+SCI2BDH_SBR10:      equ    2                                         ; SCI Baud Rate Bit 10
+SCI2BDH_SBR11:      equ    3                                         ; SCI Baud Rate Bit 11
+SCI2BDH_SBR12:      equ    4                                         ; SCI Baud Rate Bit 12
+SCI2BDH_TNP0:       equ    5                                         ; Transmitter Narrow Pulse Bit 0
+SCI2BDH_TNP1:       equ    6                                         ; Transmitter Narrow Pulse Bit 1
+SCI2BDH_IREN:       equ    7                                         ; Infrared Enable Bit
+; bit position masks
+mSCI2BDH_SBR8:      equ    %00000001
+mSCI2BDH_SBR9:      equ    %00000010
+mSCI2BDH_SBR10:     equ    %00000100
+mSCI2BDH_SBR11:     equ    %00001000
+mSCI2BDH_SBR12:     equ    %00010000
+mSCI2BDH_TNP0:      equ    %00100000
+mSCI2BDH_TNP1:      equ    %01000000
+mSCI2BDH_IREN:      equ    %10000000
+
+
+;*** SCI2BDL - SCI 2 Baud Rate Register Low; 0x000000E9 ***
+SCI2BDL:            equ    $000000E9                                ;*** SCI2BDL - SCI 2 Baud Rate Register Low; 0x000000E9 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+SCI2BDL_SBR0:       equ    0                                         ; SCI Baud Rate Bit 0
+SCI2BDL_SBR1:       equ    1                                         ; SCI Baud Rate Bit 1
+SCI2BDL_SBR2:       equ    2                                         ; SCI Baud Rate Bit 2
+SCI2BDL_SBR3:       equ    3                                         ; SCI Baud Rate Bit 3
+SCI2BDL_SBR4:       equ    4                                         ; SCI Baud Rate Bit 4
+SCI2BDL_SBR5:       equ    5                                         ; SCI Baud Rate Bit 5
+SCI2BDL_SBR6:       equ    6                                         ; SCI Baud Rate Bit 6
+SCI2BDL_SBR7:       equ    7                                         ; SCI Baud Rate Bit 7
+; bit position masks
+mSCI2BDL_SBR0:      equ    %00000001
+mSCI2BDL_SBR1:      equ    %00000010
+mSCI2BDL_SBR2:      equ    %00000100
+mSCI2BDL_SBR3:      equ    %00001000
+mSCI2BDL_SBR4:      equ    %00010000
+mSCI2BDL_SBR5:      equ    %00100000
+mSCI2BDL_SBR6:      equ    %01000000
+mSCI2BDL_SBR7:      equ    %10000000
+
+
+;*** SCI2CR1 - SCI 2 Control Register 1; 0x000000EA ***
+SCI2CR1:            equ    $000000EA                                ;*** SCI2CR1 - SCI 2 Control Register 1; 0x000000EA ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+SCI2CR1_PT:         equ    0                                         ; Parity Type Bit
+SCI2CR1_PE:         equ    1                                         ; Parity Enable Bit
+SCI2CR1_ILT:        equ    2                                         ; Idle Line Type Bit
+SCI2CR1_WAKE:       equ    3                                         ; Wakeup Condition Bit
+SCI2CR1_M:          equ    4                                         ; Data Format Mode Bit
+SCI2CR1_RSRC:       equ    5                                         ; Receiver Source Bit
+SCI2CR1_SCISWAI:    equ    6                                         ; SCI Stop in Wait Mode Bit
+SCI2CR1_LOOPS:      equ    7                                         ; Loop Select Bit
+; bit position masks
+mSCI2CR1_PT:        equ    %00000001
+mSCI2CR1_PE:        equ    %00000010
+mSCI2CR1_ILT:       equ    %00000100
+mSCI2CR1_WAKE:      equ    %00001000
+mSCI2CR1_M:         equ    %00010000
+mSCI2CR1_RSRC:      equ    %00100000
+mSCI2CR1_SCISWAI:   equ    %01000000
+mSCI2CR1_LOOPS:     equ    %10000000
+
+
+;*** SCI2CR2 - SCI 2 Control Register 2; 0x000000EB ***
+SCI2CR2:            equ    $000000EB                                ;*** SCI2CR2 - SCI 2 Control Register 2; 0x000000EB ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+SCI2CR2_SBK:        equ    0                                         ; Send Break Bit
+SCI2CR2_RWU:        equ    1                                         ; Receiver Wakeup Bit
+SCI2CR2_RE:         equ    2                                         ; Receiver Enable Bit
+SCI2CR2_TE:         equ    3                                         ; Transmitter Enable Bit
+SCI2CR2_ILIE:       equ    4                                         ; Idle Line Interrupt Enable Bit
+SCI2CR2_RIE:        equ    5                                         ; Receiver Full Interrupt Enable Bit
+SCI2CR2_TCIE:       equ    6                                         ; Transmission Complete Interrupt Enable Bit
+SCI2CR2_SCTIE:      equ    7                                         ; Transmitter Interrupt Enable Bit
+; bit position masks
+mSCI2CR2_SBK:       equ    %00000001
+mSCI2CR2_RWU:       equ    %00000010
+mSCI2CR2_RE:        equ    %00000100
+mSCI2CR2_TE:        equ    %00001000
+mSCI2CR2_ILIE:      equ    %00010000
+mSCI2CR2_RIE:       equ    %00100000
+mSCI2CR2_TCIE:      equ    %01000000
+mSCI2CR2_SCTIE:     equ    %10000000
+
+
+;*** SCI2SR1 - SCI 2 Status Register 1; 0x000000EC ***
+SCI2SR1:            equ    $000000EC                                ;*** SCI2SR1 - SCI 2 Status Register 1; 0x000000EC ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+SCI2SR1_PF:         equ    0                                         ; Parity Error Flag
+SCI2SR1_FE:         equ    1                                         ; Framing Error Flag
+SCI2SR1_NF:         equ    2                                         ; Noise Flag
+SCI2SR1_OR:         equ    3                                         ; Overrun Flag
+SCI2SR1_IDLE:       equ    4                                         ; Idle Line Flag
+SCI2SR1_RDRF:       equ    5                                         ; Receive Data Register Full Flag
+SCI2SR1_TC:         equ    6                                         ; Transmit Complete Flag
+SCI2SR1_TDRE:       equ    7                                         ; Transmit Data Register Empty Flag
+; bit position masks
+mSCI2SR1_PF:        equ    %00000001
+mSCI2SR1_FE:        equ    %00000010
+mSCI2SR1_NF:        equ    %00000100
+mSCI2SR1_OR:        equ    %00001000
+mSCI2SR1_IDLE:      equ    %00010000
+mSCI2SR1_RDRF:      equ    %00100000
+mSCI2SR1_TC:        equ    %01000000
+mSCI2SR1_TDRE:      equ    %10000000
+
+
+;*** SCI2SR2 - SCI 2 Status Register 2; 0x000000ED ***
+SCI2SR2:            equ    $000000ED                                ;*** SCI2SR2 - SCI 2 Status Register 2; 0x000000ED ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+SCI2SR2_RAF:        equ    0                                         ; Receiver Active Flag
+SCI2SR2_TXDIR:      equ    1                                         ; Transmitter pin data direction in Single-Wire mode
+SCI2SR2_BRK13:      equ    2                                         ; Break Transmit character length
+; bit position masks
+mSCI2SR2_RAF:       equ    %00000001
+mSCI2SR2_TXDIR:     equ    %00000010
+mSCI2SR2_BRK13:     equ    %00000100
+
+
+;*** SCI2DRH - SCI 2 Data Register High; 0x000000EE ***
+SCI2DRH:            equ    $000000EE                                ;*** SCI2DRH - SCI 2 Data Register High; 0x000000EE ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+SCI2DRH_T8:         equ    6                                         ; Transmit Bit 8
+SCI2DRH_R8:         equ    7                                         ; Received Bit 8
+; bit position masks
+mSCI2DRH_T8:        equ    %01000000
+mSCI2DRH_R8:        equ    %10000000
+
+
+;*** SCI2DRL - SCI 2 Data Register Low; 0x000000EF ***
+SCI2DRL:            equ    $000000EF                                ;*** SCI2DRL - SCI 2 Data Register Low; 0x000000EF ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+SCI2DRL_R0_T0:      equ    0                                         ; Received bit 0 or Transmit bit 0
+SCI2DRL_R1_T1:      equ    1                                         ; Received bit 1 or Transmit bit 1
+SCI2DRL_R2_T2:      equ    2                                         ; Received bit 2 or Transmit bit 2
+SCI2DRL_R3_T3:      equ    3                                         ; Received bit 3 or Transmit bit 3
+SCI2DRL_R4_T4:      equ    4                                         ; Received bit 4 or Transmit bit 4
+SCI2DRL_R5_T5:      equ    5                                         ; Received bit 5 or Transmit bit 5
+SCI2DRL_R6_T6:      equ    6                                         ; Received bit 6 or Transmit bit 6
+SCI2DRL_R7_T7:      equ    7                                         ; Received bit 7 or Transmit bit 7
+; bit position masks
+mSCI2DRL_R0_T0:     equ    %00000001
+mSCI2DRL_R1_T1:     equ    %00000010
+mSCI2DRL_R2_T2:     equ    %00000100
+mSCI2DRL_R3_T3:     equ    %00001000
+mSCI2DRL_R4_T4:     equ    %00010000
+mSCI2DRL_R5_T5:     equ    %00100000
+mSCI2DRL_R6_T6:     equ    %01000000
+mSCI2DRL_R7_T7:     equ    %10000000
+
+
+;*** DAC0_DACC0 - DAC0 Control Register 0; 0x000000F0 ***
+DAC0_DACC0:         equ    $000000F0                                ;*** DAC0_DACC0 - DAC0 Control Register 0; 0x000000F0 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+DAC0_DACC0_DACOE:   equ    0                                         ; DAC Output Enable
+DAC0_DACC0_DACWAI:  equ    1                                         ; DAC Stop in WAIT mode
+DAC0_DACC0_DSGN:    equ    2                                         ; Result Register Data Signed or Unsigned Representation
+DAC0_DACC0_DJM:     equ    3                                         ; Data Register Data Justification
+DAC0_DACC0_DACTE:   equ    6                                         ; DAC Test Enable
+DAC0_DACC0_DACE:    equ    7                                         ; DAC Enable
+; bit position masks
+mDAC0_DACC0_DACOE:  equ    %00000001
+mDAC0_DACC0_DACWAI: equ    %00000010
+mDAC0_DACC0_DSGN:   equ    %00000100
+mDAC0_DACC0_DJM:    equ    %00001000
+mDAC0_DACC0_DACTE:  equ    %01000000
+mDAC0_DACC0_DACE:   equ    %10000000
+
+
+;*** DAC0_DACDLeft - DAC0 Data Register - Left Justified; 0x000000F2 ***
+DAC0_DACDLeft:      equ    $000000F2                                ;*** DAC0_DACDLeft - DAC0 Data Register - Left Justified; 0x000000F2 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+DAC0_DACDLeft_BIT0: equ    0                                         ; Data Bit 0
+DAC0_DACDLeft_BIT1: equ    1                                         ; Data Bit 1
+DAC0_DACDLeft_BIT2: equ    2                                         ; Data Bit 2
+DAC0_DACDLeft_BIT3: equ    3                                         ; Data Bit 3
+DAC0_DACDLeft_BIT4: equ    4                                         ; Data Bit 4
+DAC0_DACDLeft_BIT5: equ    5                                         ; Data Bit 5
+DAC0_DACDLeft_BIT6: equ    6                                         ; Data Bit 6
+DAC0_DACDLeft_BIT7: equ    7                                         ; Data Bit 7
+; bit position masks
+mDAC0_DACDLeft_BIT0: equ    %00000001
+mDAC0_DACDLeft_BIT1: equ    %00000010
+mDAC0_DACDLeft_BIT2: equ    %00000100
+mDAC0_DACDLeft_BIT3: equ    %00001000
+mDAC0_DACDLeft_BIT4: equ    %00010000
+mDAC0_DACDLeft_BIT5: equ    %00100000
+mDAC0_DACDLeft_BIT6: equ    %01000000
+mDAC0_DACDLeft_BIT7: equ    %10000000
+
+
+;*** DAC0_DACDRight - DAC0 Data Register - Right Justified; 0x000000F3 ***
+DAC0_DACDRight:     equ    $000000F3                                ;*** DAC0_DACDRight - DAC0 Data Register - Right Justified; 0x000000F3 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+DAC0_DACDRight_BIT0: equ    0                                        ; Data Bit 0
+DAC0_DACDRight_BIT1: equ    1                                        ; Data Bit 1
+DAC0_DACDRight_BIT2: equ    2                                        ; Data Bit 2
+DAC0_DACDRight_BIT3: equ    3                                        ; Data Bit 3
+DAC0_DACDRight_BIT4: equ    4                                        ; Data Bit 4
+DAC0_DACDRight_BIT5: equ    5                                        ; Data Bit 5
+DAC0_DACDRight_BIT6: equ    6                                        ; Data Bit 6
+DAC0_DACDRight_BIT7: equ    7                                        ; Data Bit 7
+; bit position masks
+mDAC0_DACDRight_BIT0: equ    %00000001
+mDAC0_DACDRight_BIT1: equ    %00000010
+mDAC0_DACDRight_BIT2: equ    %00000100
+mDAC0_DACDRight_BIT3: equ    %00001000
+mDAC0_DACDRight_BIT4: equ    %00010000
+mDAC0_DACDRight_BIT5: equ    %00100000
+mDAC0_DACDRight_BIT6: equ    %01000000
+mDAC0_DACDRight_BIT7: equ    %10000000
+
+
+;*** DAC1_DACC0 - DAC1Control Register 0; 0x000000F4 ***
+DAC1_DACC0:         equ    $000000F4                                ;*** DAC1_DACC0 - DAC1Control Register 0; 0x000000F4 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+DAC1_DACC0_DACOE:   equ    0                                         ; DAC Output Enable
+DAC1_DACC0_DACWAI:  equ    1                                         ; DAC Stop in WAIT mode
+DAC1_DACC0_DSGN:    equ    2                                         ; Result Register Data Signed or Unsigned Representation
+DAC1_DACC0_DJM:     equ    3                                         ; Data Register Data Justification
+DAC1_DACC0_DACTE:   equ    6                                         ; DAC Test Enable
+DAC1_DACC0_DACE:    equ    7                                         ; DAC Enable
+; bit position masks
+mDAC1_DACC0_DACOE:  equ    %00000001
+mDAC1_DACC0_DACWAI: equ    %00000010
+mDAC1_DACC0_DSGN:   equ    %00000100
+mDAC1_DACC0_DJM:    equ    %00001000
+mDAC1_DACC0_DACTE:  equ    %01000000
+mDAC1_DACC0_DACE:   equ    %10000000
+
+
+;*** DAC1_DACDLeft - DAC1 Data Register - Left Justified; 0x000000F6 ***
+DAC1_DACDLeft:      equ    $000000F6                                ;*** DAC1_DACDLeft - DAC1 Data Register - Left Justified; 0x000000F6 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+DAC1_DACDLeft_BIT0: equ    0                                         ; Data Bit 0
+DAC1_DACDLeft_BIT1: equ    1                                         ; Data Bit 1
+DAC1_DACDLeft_BIT2: equ    2                                         ; Data Bit 2
+DAC1_DACDLeft_BIT3: equ    3                                         ; Data Bit 3
+DAC1_DACDLeft_BIT4: equ    4                                         ; Data Bit 4
+DAC1_DACDLeft_BIT5: equ    5                                         ; Data Bit 5
+DAC1_DACDLeft_BIT6: equ    6                                         ; Data Bit 6
+DAC1_DACDLeft_BIT7: equ    7                                         ; Data Bit 7
+; bit position masks
+mDAC1_DACDLeft_BIT0: equ    %00000001
+mDAC1_DACDLeft_BIT1: equ    %00000010
+mDAC1_DACDLeft_BIT2: equ    %00000100
+mDAC1_DACDLeft_BIT3: equ    %00001000
+mDAC1_DACDLeft_BIT4: equ    %00010000
+mDAC1_DACDLeft_BIT5: equ    %00100000
+mDAC1_DACDLeft_BIT6: equ    %01000000
+mDAC1_DACDLeft_BIT7: equ    %10000000
+
+
+;*** DAC1_DACDRight - DAC1 Data Register - Right Justified; 0x000000F7 ***
+DAC1_DACDRight:     equ    $000000F7                                ;*** DAC1_DACDRight - DAC1 Data Register - Right Justified; 0x000000F7 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+DAC1_DACDRight_BIT0: equ    0                                        ; Data Bit 0
+DAC1_DACDRight_BIT1: equ    1                                        ; Data Bit 1
+DAC1_DACDRight_BIT2: equ    2                                        ; Data Bit 2
+DAC1_DACDRight_BIT3: equ    3                                        ; Data Bit 3
+DAC1_DACDRight_BIT4: equ    4                                        ; Data Bit 4
+DAC1_DACDRight_BIT5: equ    5                                        ; Data Bit 5
+DAC1_DACDRight_BIT6: equ    6                                        ; Data Bit 6
+DAC1_DACDRight_BIT7: equ    7                                        ; Data Bit 7
+; bit position masks
+mDAC1_DACDRight_BIT0: equ    %00000001
+mDAC1_DACDRight_BIT1: equ    %00000010
+mDAC1_DACDRight_BIT2: equ    %00000100
+mDAC1_DACDRight_BIT3: equ    %00001000
+mDAC1_DACDRight_BIT4: equ    %00010000
+mDAC1_DACDRight_BIT5: equ    %00100000
+mDAC1_DACDRight_BIT6: equ    %01000000
+mDAC1_DACDRight_BIT7: equ    %10000000
+
+
+;*** FCLKDIV - Flash Clock Divider Register; 0x00000100 ***
+FCLKDIV:            equ    $00000100                                ;*** FCLKDIV - Flash Clock Divider Register; 0x00000100 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+FCLKDIV_FDIV0:      equ    0                                         ; Flash Clock Divider Bit 0
+FCLKDIV_FDIV1:      equ    1                                         ; Flash Clock Divider Bit 1
+FCLKDIV_FDIV2:      equ    2                                         ; Flash Clock Divider Bit 2
+FCLKDIV_FDIV3:      equ    3                                         ; Flash Clock Divider Bit 3
+FCLKDIV_FDIV4:      equ    4                                         ; Flash Clock Divider Bit 4
+FCLKDIV_FDIV5:      equ    5                                         ; Flash Clock Divider Bit 5
+FCLKDIV_PRDIV8:     equ    6                                         ; Enable Prescaler by 8
+FCLKDIV_FDIVLD:     equ    7                                         ; Flash Clock Divider Loaded
+; bit position masks
+mFCLKDIV_FDIV0:     equ    %00000001
+mFCLKDIV_FDIV1:     equ    %00000010
+mFCLKDIV_FDIV2:     equ    %00000100
+mFCLKDIV_FDIV3:     equ    %00001000
+mFCLKDIV_FDIV4:     equ    %00010000
+mFCLKDIV_FDIV5:     equ    %00100000
+mFCLKDIV_PRDIV8:    equ    %01000000
+mFCLKDIV_FDIVLD:    equ    %10000000
+
+
+;*** FSEC - Flash Security Register; 0x00000101 ***
+FSEC:               equ    $00000101                                ;*** FSEC - Flash Security Register; 0x00000101 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+FSEC_SEC0:          equ    0                                         ; Memory security bit 0
+FSEC_SEC1:          equ    1                                         ; Memory security bit 1
+FSEC_NV2:           equ    2                                         ; Non Volatile flag bit 2
+FSEC_NV3:           equ    3                                         ; Non Volatile flag bit 3
+FSEC_NV4:           equ    4                                         ; Non Volatile flag bit 4
+FSEC_NV5:           equ    5                                         ; Non Volatile flag bit 5
+FSEC_NV6:           equ    6                                         ; Non Volatile flag bit 6
+FSEC_KEYEN:         equ    7                                         ; Backdoor Key Security Enable
+; bit position masks
+mFSEC_SEC0:         equ    %00000001
+mFSEC_SEC1:         equ    %00000010
+mFSEC_NV2:          equ    %00000100
+mFSEC_NV3:          equ    %00001000
+mFSEC_NV4:          equ    %00010000
+mFSEC_NV5:          equ    %00100000
+mFSEC_NV6:          equ    %01000000
+mFSEC_KEYEN:        equ    %10000000
+
+
+;*** FCNFG - Flash Configuration Register; 0x00000103 ***
+FCNFG:              equ    $00000103                                ;*** FCNFG - Flash Configuration Register; 0x00000103 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+FCNFG_KEYACC:       equ    5                                         ; Enable Security Key Writing
+FCNFG_CCIE:         equ    6                                         ; Command Complete Interrupt Enable
+FCNFG_CBEIE:        equ    7                                         ; Command Buffers Empty Interrupt Enable
+; bit position masks
+mFCNFG_KEYACC:      equ    %00100000
+mFCNFG_CCIE:        equ    %01000000
+mFCNFG_CBEIE:       equ    %10000000
+
+
+;*** FPROT - Flash Protection Register; 0x00000104 ***
+FPROT:              equ    $00000104                                ;*** FPROT - Flash Protection Register; 0x00000104 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+FPROT_FPLS0:        equ    0                                         ; Flash Protection Lower Address size 0
+FPROT_FPLS1:        equ    1                                         ; Flash Protection Lower Address size 1
+FPROT_FPLDIS:       equ    2                                         ; Flash Protection Lower address range disable
+FPROT_FPHS0:        equ    3                                         ; Flash Protection Higher address size 0
+FPROT_FPHS1:        equ    4                                         ; Flash Protection Higher address size 1
+FPROT_FPHDIS:       equ    5                                         ; Flash Protection Higher address range disable
+FPROT_NV6:          equ    6                                         ; Non Volatile Flag Bit
+FPROT_FPOPEN:       equ    7                                         ; Opens the flash block or subsections of it for program or erase
+; bit position masks
+mFPROT_FPLS0:       equ    %00000001
+mFPROT_FPLS1:       equ    %00000010
+mFPROT_FPLDIS:      equ    %00000100
+mFPROT_FPHS0:       equ    %00001000
+mFPROT_FPHS1:       equ    %00010000
+mFPROT_FPHDIS:      equ    %00100000
+mFPROT_NV6:         equ    %01000000
+mFPROT_FPOPEN:      equ    %10000000
+
+
+;*** FSTAT - Flash Status Register; 0x00000105 ***
+FSTAT:              equ    $00000105                                ;*** FSTAT - Flash Status Register; 0x00000105 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+FSTAT_BLANK:        equ    2                                         ; Blank Verify Flag
+FSTAT_ACCERR:       equ    4                                         ; Access error
+FSTAT_PVIOL:        equ    5                                         ; Protection violation
+FSTAT_CCIF:         equ    6                                         ; Command Complete Interrupt Flag
+FSTAT_CBEIF:        equ    7                                         ; Command Buffers Empty Interrupt Flag
+; bit position masks
+mFSTAT_BLANK:       equ    %00000100
+mFSTAT_ACCERR:      equ    %00010000
+mFSTAT_PVIOL:       equ    %00100000
+mFSTAT_CCIF:        equ    %01000000
+mFSTAT_CBEIF:       equ    %10000000
+
+
+;*** FCMD - Flash Command Buffer and Register; 0x00000106 ***
+FCMD:               equ    $00000106                                ;*** FCMD - Flash Command Buffer and Register; 0x00000106 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+FCMD_CMDB0:         equ    0                                         ; NVM User Mode Command Bit 0
+FCMD_CMDB2:         equ    2                                         ; NVM User Mode Command Bit 2
+FCMD_CMDB5:         equ    5                                         ; NVM User Mode Command Bit 5
+FCMD_CMDB6:         equ    6                                         ; NVM User Mode Command Bit 6
+; bit position masks
+mFCMD_CMDB0:        equ    %00000001
+mFCMD_CMDB2:        equ    %00000100
+mFCMD_CMDB5:        equ    %00100000
+mFCMD_CMDB6:        equ    %01000000
+
+
+;*** TIM1_TIOS - TIM1 Timer Input Capture/Output Compare Select; 0x00000140 ***
+TIM1_TIOS:          equ    $00000140                                ;*** TIM1_TIOS - TIM1 Timer Input Capture/Output Compare Select; 0x00000140 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+TIM1_TIOS_IOS4:     equ    4                                         ; Input Capture or Output Compare Channel Configuration Bit 4
+TIM1_TIOS_IOS5:     equ    5                                         ; Input Capture or Output Compare Channel Configuration Bit 5
+TIM1_TIOS_IOS6:     equ    6                                         ; Input Capture or Output Compare Channel Configuration Bit 6
+TIM1_TIOS_IOS7:     equ    7                                         ; Input Capture or Output Compare Channel Configuration Bit 7
+; bit position masks
+mTIM1_TIOS_IOS4:    equ    %00010000
+mTIM1_TIOS_IOS5:    equ    %00100000
+mTIM1_TIOS_IOS6:    equ    %01000000
+mTIM1_TIOS_IOS7:    equ    %10000000
+
+
+;*** TIM1_CFORC - TIM1 Timer Compare Force Register; 0x00000141 ***
+TIM1_CFORC:         equ    $00000141                                ;*** TIM1_CFORC - TIM1 Timer Compare Force Register; 0x00000141 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+TIM1_CFORC_FOC4:    equ    4                                         ; Force Output Compare Action for Channel 4
+TIM1_CFORC_FOC5:    equ    5                                         ; Force Output Compare Action for Channel 5
+TIM1_CFORC_FOC6:    equ    6                                         ; Force Output Compare Action for Channel 6
+TIM1_CFORC_FOC7:    equ    7                                         ; Force Output Compare Action for Channel 7
+; bit position masks
+mTIM1_CFORC_FOC4:   equ    %00010000
+mTIM1_CFORC_FOC5:   equ    %00100000
+mTIM1_CFORC_FOC6:   equ    %01000000
+mTIM1_CFORC_FOC7:   equ    %10000000
+
+
+;*** TIM1_OC7M - TIM1 Output Compare 7 Mask Register; 0x00000142 ***
+TIM1_OC7M:          equ    $00000142                                ;*** TIM1_OC7M - TIM1 Output Compare 7 Mask Register; 0x00000142 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+TIM1_OC7M_OC7M4:    equ    4                                         ; Output Compare 7 Mask Bit 4
+TIM1_OC7M_OC7M5:    equ    5                                         ; Output Compare 7 Mask Bit 5
+TIM1_OC7M_OC7M6:    equ    6                                         ; Output Compare 7 Mask Bit 6
+TIM1_OC7M_OC7M7:    equ    7                                         ; Output Compare 7 Mask Bit 7
+; bit position masks
+mTIM1_OC7M_OC7M4:   equ    %00010000
+mTIM1_OC7M_OC7M5:   equ    %00100000
+mTIM1_OC7M_OC7M6:   equ    %01000000
+mTIM1_OC7M_OC7M7:   equ    %10000000
+
+
+;*** TIM1_OC7D - TIM1 Output Compare 7 Data Register; 0x00000143 ***
+TIM1_OC7D:          equ    $00000143                                ;*** TIM1_OC7D - TIM1 Output Compare 7 Data Register; 0x00000143 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+TIM1_OC7D_OC7D4:    equ    4                                         ; Output Compare 7 Bit 4
+TIM1_OC7D_OC7D5:    equ    5                                         ; Output Compare 7 Bit 5
+TIM1_OC7D_OC7D6:    equ    6                                         ; Output Compare 7 Bit 6
+TIM1_OC7D_OC7D7:    equ    7                                         ; Output Compare 7 Bit 7
+; bit position masks
+mTIM1_OC7D_OC7D4:   equ    %00010000
+mTIM1_OC7D_OC7D5:   equ    %00100000
+mTIM1_OC7D_OC7D6:   equ    %01000000
+mTIM1_OC7D_OC7D7:   equ    %10000000
+
+
+;*** TIM1_TCNT - TIM1 Timer Count Register; 0x00000144 ***
+TIM1_TCNT:          equ    $00000144                                ;*** TIM1_TCNT - TIM1 Timer Count Register; 0x00000144 ***
+
+
+;*** TIM1_TCNTHi - TIM1 Timer Count Register High; 0x00000144 ***
+TIM1_TCNTHi:        equ    $00000144                                ;*** TIM1_TCNTHi - TIM1 Timer Count Register High; 0x00000144 ***
+
+
+;*** TIM1_TCNTLo - TIM1 Timer Count Register Low; 0x00000145 ***
+TIM1_TCNTLo:        equ    $00000145                                ;*** TIM1_TCNTLo - TIM1 Timer Count Register Low; 0x00000145 ***
+
+
+;*** TIM1_TSCR1 - TIM1 Timer System Control Register1; 0x00000146 ***
+TIM1_TSCR1:         equ    $00000146                                ;*** TIM1_TSCR1 - TIM1 Timer System Control Register1; 0x00000146 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+TIM1_TSCR1_TFFCA:   equ    4                                         ; Timer Fast Flag Clear All
+TIM1_TSCR1_TSFRZ:   equ    5                                         ; Timer and Modulus Counter Stop While in Freeze Mode
+TIM1_TSCR1_TSWAI:   equ    6                                         ; Timer Module Stops While in Wait
+TIM1_TSCR1_TEN:     equ    7                                         ; Timer Enable
+; bit position masks
+mTIM1_TSCR1_TFFCA:  equ    %00010000
+mTIM1_TSCR1_TSFRZ:  equ    %00100000
+mTIM1_TSCR1_TSWAI:  equ    %01000000
+mTIM1_TSCR1_TEN:    equ    %10000000
+
+
+;*** TIM1_TTOV - TIM1 Timer Toggle On Overflow Register; 0x00000147 ***
+TIM1_TTOV:          equ    $00000147                                ;*** TIM1_TTOV - TIM1 Timer Toggle On Overflow Register; 0x00000147 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+TIM1_TTOV_TOV4:     equ    4                                         ; Toggle On Overflow Bit 4
+TIM1_TTOV_TOV5:     equ    5                                         ; Toggle On Overflow Bit 5
+TIM1_TTOV_TOV6:     equ    6                                         ; Toggle On Overflow Bit 6
+TIM1_TTOV_TOV7:     equ    7                                         ; Toggle On Overflow Bit 7
+; bit position masks
+mTIM1_TTOV_TOV4:    equ    %00010000
+mTIM1_TTOV_TOV5:    equ    %00100000
+mTIM1_TTOV_TOV6:    equ    %01000000
+mTIM1_TTOV_TOV7:    equ    %10000000
+
+
+;*** TIM1_TCTL1 - TIM1 Timer Control Register 1; 0x00000148 ***
+TIM1_TCTL1:         equ    $00000148                                ;*** TIM1_TCTL1 - TIM1 Timer Control Register 1; 0x00000148 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+TIM1_TCTL1_OL4:     equ    0                                         ; Output Level Bit 4
+TIM1_TCTL1_OM4:     equ    1                                         ; Output Mode Bit 4
+TIM1_TCTL1_OL5:     equ    2                                         ; Output Level Bit 5
+TIM1_TCTL1_OM5:     equ    3                                         ; Output Mode Bit 5
+TIM1_TCTL1_OL6:     equ    4                                         ; Output Level Bit 6
+TIM1_TCTL1_OM6:     equ    5                                         ; Output Mode Bit 6
+TIM1_TCTL1_OL7:     equ    6                                         ; Output Level Bit 7
+TIM1_TCTL1_OM7:     equ    7                                         ; Output Mode Bit 7
+; bit position masks
+mTIM1_TCTL1_OL4:    equ    %00000001
+mTIM1_TCTL1_OM4:    equ    %00000010
+mTIM1_TCTL1_OL5:    equ    %00000100
+mTIM1_TCTL1_OM5:    equ    %00001000
+mTIM1_TCTL1_OL6:    equ    %00010000
+mTIM1_TCTL1_OM6:    equ    %00100000
+mTIM1_TCTL1_OL7:    equ    %01000000
+mTIM1_TCTL1_OM7:    equ    %10000000
+
+
+;*** TIM1_TCTL3 - TIM1 Timer Control Register 3; 0x0000014A ***
+TIM1_TCTL3:         equ    $0000014A                                ;*** TIM1_TCTL3 - TIM1 Timer Control Register 3; 0x0000014A ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+TIM1_TCTL3_EDG4A:   equ    0                                         ; Input Capture Edge Control 4A
+TIM1_TCTL3_EDG4B:   equ    1                                         ; Input Capture Edge Control 4B
+TIM1_TCTL3_EDG5A:   equ    2                                         ; Input Capture Edge Control 5A
+TIM1_TCTL3_EDG5B:   equ    3                                         ; Input Capture Edge Control 5B
+TIM1_TCTL3_EDG6A:   equ    4                                         ; Input Capture Edge Control 6A
+TIM1_TCTL3_EDG6B:   equ    5                                         ; Input Capture Edge Control 6B
+TIM1_TCTL3_EDG7A:   equ    6                                         ; Input Capture Edge Control 7A
+TIM1_TCTL3_EDG7B:   equ    7                                         ; Input Capture Edge Control 7B
+; bit position masks
+mTIM1_TCTL3_EDG4A:  equ    %00000001
+mTIM1_TCTL3_EDG4B:  equ    %00000010
+mTIM1_TCTL3_EDG5A:  equ    %00000100
+mTIM1_TCTL3_EDG5B:  equ    %00001000
+mTIM1_TCTL3_EDG6A:  equ    %00010000
+mTIM1_TCTL3_EDG6B:  equ    %00100000
+mTIM1_TCTL3_EDG7A:  equ    %01000000
+mTIM1_TCTL3_EDG7B:  equ    %10000000
+
+
+;*** TIM1_TIE - TIM1 Timer Interrupt Enable Register; 0x0000014C ***
+TIM1_TIE:           equ    $0000014C                                ;*** TIM1_TIE - TIM1 Timer Interrupt Enable Register; 0x0000014C ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+TIM1_TIE_C4I:       equ    4                                         ; Input Capture/Output Compare Interrupt Enable Bit 4
+TIM1_TIE_C5I:       equ    5                                         ; Input Capture/Output Compare Interrupt Enable Bit 5
+TIM1_TIE_C6I:       equ    6                                         ; Input Capture/Output Compare Interrupt Enable Bit 6
+TIM1_TIE_C7I:       equ    7                                         ; Input Capture/Output Compare Interrupt Enable Bit 7
+; bit position masks
+mTIM1_TIE_C4I:      equ    %00010000
+mTIM1_TIE_C5I:      equ    %00100000
+mTIM1_TIE_C6I:      equ    %01000000
+mTIM1_TIE_C7I:      equ    %10000000
+
+
+;*** TIM1_TSCR2 - TIM1 Timer System Control Register 2; 0x0000014D ***
+TIM1_TSCR2:         equ    $0000014D                                ;*** TIM1_TSCR2 - TIM1 Timer System Control Register 2; 0x0000014D ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+TIM1_TSCR2_PR0:     equ    0                                         ; Timer Prescaler Select Bit 0
+TIM1_TSCR2_PR1:     equ    1                                         ; Timer Prescaler Select Bit 1
+TIM1_TSCR2_PR2:     equ    2                                         ; Timer Prescaler Select Bit 2
+TIM1_TSCR2_TCRE:    equ    3                                         ; Timer Counter Reset Enable
+TIM1_TSCR2_TOI:     equ    7                                         ; Timer Overflow Interrupt Enable
+; bit position masks
+mTIM1_TSCR2_PR0:    equ    %00000001
+mTIM1_TSCR2_PR1:    equ    %00000010
+mTIM1_TSCR2_PR2:    equ    %00000100
+mTIM1_TSCR2_TCRE:   equ    %00001000
+mTIM1_TSCR2_TOI:    equ    %10000000
+
+
+;*** TIM1_TFLG1 - TIM1 Main Timer Interrupt Flag 1; 0x0000014E ***
+TIM1_TFLG1:         equ    $0000014E                                ;*** TIM1_TFLG1 - TIM1 Main Timer Interrupt Flag 1; 0x0000014E ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+TIM1_TFLG1_C4F:     equ    4                                         ; Input Capture/Output Compare Channel Flag 4
+TIM1_TFLG1_C5F:     equ    5                                         ; Input Capture/Output Compare Channel Flag 5
+TIM1_TFLG1_C6F:     equ    6                                         ; Input Capture/Output Compare Channel Flag 6
+TIM1_TFLG1_C7F:     equ    7                                         ; Input Capture/Output Compare Channel Flag 7
+; bit position masks
+mTIM1_TFLG1_C4F:    equ    %00010000
+mTIM1_TFLG1_C5F:    equ    %00100000
+mTIM1_TFLG1_C6F:    equ    %01000000
+mTIM1_TFLG1_C7F:    equ    %10000000
+
+
+;*** TIM1_TFLG2 - TIM1 Main Timer Interrupt Flag 2; 0x0000014F ***
+TIM1_TFLG2:         equ    $0000014F                                ;*** TIM1_TFLG2 - TIM1 Main Timer Interrupt Flag 2; 0x0000014F ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+TIM1_TFLG2_TOF:     equ    7                                         ; Timer Overflow Flag
+; bit position masks
+mTIM1_TFLG2_TOF:    equ    %10000000
+
+
+;*** TIM1_TC4 - TIM1 Timer Input Capture/Output Compare Register 4; 0x00000158 ***
+TIM1_TC4:           equ    $00000158                                ;*** TIM1_TC4 - TIM1 Timer Input Capture/Output Compare Register 4; 0x00000158 ***
+
+
+;*** TIM1_TC4Hi - TIM1 Timer Input Capture/Output Compare Register 4 High; 0x00000158 ***
+TIM1_TC4Hi:         equ    $00000158                                ;*** TIM1_TC4Hi - TIM1 Timer Input Capture/Output Compare Register 4 High; 0x00000158 ***
+
+
+;*** TIM1_TC4Lo - TIM1 Timer Input Capture/Output Compare Register 4 Low; 0x00000159 ***
+TIM1_TC4Lo:         equ    $00000159                                ;*** TIM1_TC4Lo - TIM1 Timer Input Capture/Output Compare Register 4 Low; 0x00000159 ***
+
+
+;*** TIM1_TC5 - TIM1 Timer Input Capture/Output Compare Register 5; 0x0000015A ***
+TIM1_TC5:           equ    $0000015A                                ;*** TIM1_TC5 - TIM1 Timer Input Capture/Output Compare Register 5; 0x0000015A ***
+
+
+;*** TIM1_TC5Hi - TIM1 Timer Input Capture/Output Compare Register 5 High; 0x0000015A ***
+TIM1_TC5Hi:         equ    $0000015A                                ;*** TIM1_TC5Hi - TIM1 Timer Input Capture/Output Compare Register 5 High; 0x0000015A ***
+
+
+;*** TIM1_TC5Lo - TIM1 Timer Input Capture/Output Compare Register 5 Low; 0x0000015B ***
+TIM1_TC5Lo:         equ    $0000015B                                ;*** TIM1_TC5Lo - TIM1 Timer Input Capture/Output Compare Register 5 Low; 0x0000015B ***
+
+
+;*** TIM1_TC6 - TIM1 Timer Input Capture/Output Compare Register 6; 0x0000015C ***
+TIM1_TC6:           equ    $0000015C                                ;*** TIM1_TC6 - TIM1 Timer Input Capture/Output Compare Register 6; 0x0000015C ***
+
+
+;*** TIM1_TC6Hi - TIM1 Timer Input Capture/Output Compare Register 6 High; 0x0000015C ***
+TIM1_TC6Hi:         equ    $0000015C                                ;*** TIM1_TC6Hi - TIM1 Timer Input Capture/Output Compare Register 6 High; 0x0000015C ***
+
+
+;*** TIM1_TC6Lo - TIM1 Timer Input Capture/Output Compare Register 6 Low; 0x0000015D ***
+TIM1_TC6Lo:         equ    $0000015D                                ;*** TIM1_TC6Lo - TIM1 Timer Input Capture/Output Compare Register 6 Low; 0x0000015D ***
+
+
+;*** TIM1_TC7 - TIM1 Timer Input Capture/Output Compare Register 7; 0x0000015E ***
+TIM1_TC7:           equ    $0000015E                                ;*** TIM1_TC7 - TIM1 Timer Input Capture/Output Compare Register 7; 0x0000015E ***
+
+
+;*** TIM1_TC7Hi - TIM1 Timer Input Capture/Output Compare Register 7 High; 0x0000015E ***
+TIM1_TC7Hi:         equ    $0000015E                                ;*** TIM1_TC7Hi - TIM1 Timer Input Capture/Output Compare Register 7 High; 0x0000015E ***
+
+
+;*** TIM1_TC7Lo - TIM1 Timer Input Capture/Output Compare Register 7 Low; 0x0000015F ***
+TIM1_TC7Lo:         equ    $0000015F                                ;*** TIM1_TC7Lo - TIM1 Timer Input Capture/Output Compare Register 7 Low; 0x0000015F ***
+
+
+;*** TIM1_PACTL - TIM1 16-Bit Pulse Accumulator A Control Register; 0x00000160 ***
+TIM1_PACTL:         equ    $00000160                                ;*** TIM1_PACTL - TIM1 16-Bit Pulse Accumulator A Control Register; 0x00000160 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+TIM1_PACTL_PAI:     equ    0                                         ; Pulse Accumulator Input Interrupt enable
+TIM1_PACTL_PAOVI:   equ    1                                         ; Pulse Accumulator A Overflow Interrupt enable
+TIM1_PACTL_CLK0:    equ    2                                         ; Clock Select Bit 0
+TIM1_PACTL_CLK1:    equ    3                                         ; Clock Select Bit 1
+TIM1_PACTL_PEDGE:   equ    4                                         ; Pulse Accumulator Edge Control
+TIM1_PACTL_PAMOD:   equ    5                                         ; Pulse Accumulator Mode
+TIM1_PACTL_PAEN:    equ    6                                         ; Pulse Accumulator A System Enable
+; bit position masks
+mTIM1_PACTL_PAI:    equ    %00000001
+mTIM1_PACTL_PAOVI:  equ    %00000010
+mTIM1_PACTL_CLK0:   equ    %00000100
+mTIM1_PACTL_CLK1:   equ    %00001000
+mTIM1_PACTL_PEDGE:  equ    %00010000
+mTIM1_PACTL_PAMOD:  equ    %00100000
+mTIM1_PACTL_PAEN:   equ    %01000000
+
+
+;*** TIM1_PAFLG - TIM1 Pulse Accumulator A Flag Register; 0x00000161 ***
+TIM1_PAFLG:         equ    $00000161                                ;*** TIM1_PAFLG - TIM1 Pulse Accumulator A Flag Register; 0x00000161 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+TIM1_PAFLG_PAIF:    equ    0                                         ; Pulse Accumulator Input edge Flag
+TIM1_PAFLG_PAOVF:   equ    1                                         ; Pulse Accumulator A Overflow Flag
+; bit position masks
+mTIM1_PAFLG_PAIF:   equ    %00000001
+mTIM1_PAFLG_PAOVF:  equ    %00000010
+
+
+;*** TIM1_PACNT - TIM1 Pulse Accumulators Count Register; 0x00000162 ***
+TIM1_PACNT:         equ    $00000162                                ;*** TIM1_PACNT - TIM1 Pulse Accumulators Count Register; 0x00000162 ***
+
+
+;*** TIM2_TIOS - TIM2 Timer Input Capture/Output Compare Select; 0x00000180 ***
+TIM2_TIOS:          equ    $00000180                                ;*** TIM2_TIOS - TIM2 Timer Input Capture/Output Compare Select; 0x00000180 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+TIM2_TIOS_IOS4:     equ    4                                         ; Input Capture or Output Compare Channel Configuration Bit 4
+TIM2_TIOS_IOS5:     equ    5                                         ; Input Capture or Output Compare Channel Configuration Bit 5
+TIM2_TIOS_IOS6:     equ    6                                         ; Input Capture or Output Compare Channel Configuration Bit 6
+TIM2_TIOS_IOS7:     equ    7                                         ; Input Capture or Output Compare Channel Configuration Bit 7
+; bit position masks
+mTIM2_TIOS_IOS4:    equ    %00010000
+mTIM2_TIOS_IOS5:    equ    %00100000
+mTIM2_TIOS_IOS6:    equ    %01000000
+mTIM2_TIOS_IOS7:    equ    %10000000
+
+
+;*** TIM2_CFORC - TIM2 Timer Compare Force Register; 0x00000181 ***
+TIM2_CFORC:         equ    $00000181                                ;*** TIM2_CFORC - TIM2 Timer Compare Force Register; 0x00000181 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+TIM2_CFORC_FOC4:    equ    4                                         ; Force Output Compare Action for Channel 4
+TIM2_CFORC_FOC5:    equ    5                                         ; Force Output Compare Action for Channel 5
+TIM2_CFORC_FOC6:    equ    6                                         ; Force Output Compare Action for Channel 6
+TIM2_CFORC_FOC7:    equ    7                                         ; Force Output Compare Action for Channel 7
+; bit position masks
+mTIM2_CFORC_FOC4:   equ    %00010000
+mTIM2_CFORC_FOC5:   equ    %00100000
+mTIM2_CFORC_FOC6:   equ    %01000000
+mTIM2_CFORC_FOC7:   equ    %10000000
+
+
+;*** TIM2_OC7M - TIM2 Output Compare 7 Mask Register; 0x00000182 ***
+TIM2_OC7M:          equ    $00000182                                ;*** TIM2_OC7M - TIM2 Output Compare 7 Mask Register; 0x00000182 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+TIM2_OC7M_OC7M4:    equ    4                                         ; Output Compare 7 Mask Bit 4
+TIM2_OC7M_OC7M5:    equ    5                                         ; Output Compare 7 Mask Bit 5
+TIM2_OC7M_OC7M6:    equ    6                                         ; Output Compare 7 Mask Bit 6
+TIM2_OC7M_OC7M7:    equ    7                                         ; Output Compare 7 Mask Bit 7
+; bit position masks
+mTIM2_OC7M_OC7M4:   equ    %00010000
+mTIM2_OC7M_OC7M5:   equ    %00100000
+mTIM2_OC7M_OC7M6:   equ    %01000000
+mTIM2_OC7M_OC7M7:   equ    %10000000
+
+
+;*** TIM2_OC7D - TIM2 Output Compare 7 Data Register; 0x00000183 ***
+TIM2_OC7D:          equ    $00000183                                ;*** TIM2_OC7D - TIM2 Output Compare 7 Data Register; 0x00000183 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+TIM2_OC7D_OC7D4:    equ    4                                         ; Output Compare 7 Bit 4
+TIM2_OC7D_OC7D5:    equ    5                                         ; Output Compare 7 Bit 5
+TIM2_OC7D_OC7D6:    equ    6                                         ; Output Compare 7 Bit 6
+TIM2_OC7D_OC7D7:    equ    7                                         ; Output Compare 7 Bit 7
+; bit position masks
+mTIM2_OC7D_OC7D4:   equ    %00010000
+mTIM2_OC7D_OC7D5:   equ    %00100000
+mTIM2_OC7D_OC7D6:   equ    %01000000
+mTIM2_OC7D_OC7D7:   equ    %10000000
+
+
+;*** TIM2_TCNT - TIM2 Timer Count Register; 0x00000184 ***
+TIM2_TCNT:          equ    $00000184                                ;*** TIM2_TCNT - TIM2 Timer Count Register; 0x00000184 ***
+
+
+;*** TIM2_TCNTHi - TIM2 Timer Count Register High; 0x00000184 ***
+TIM2_TCNTHi:        equ    $00000184                                ;*** TIM2_TCNTHi - TIM2 Timer Count Register High; 0x00000184 ***
+
+
+;*** TIM2_TCNTLo - TIM2 Timer Count Register Low; 0x00000185 ***
+TIM2_TCNTLo:        equ    $00000185                                ;*** TIM2_TCNTLo - TIM2 Timer Count Register Low; 0x00000185 ***
+
+
+;*** TIM2_TSCR1 - TIM2 Timer System Control Register1; 0x00000186 ***
+TIM2_TSCR1:         equ    $00000186                                ;*** TIM2_TSCR1 - TIM2 Timer System Control Register1; 0x00000186 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+TIM2_TSCR1_TFFCA:   equ    4                                         ; Timer Fast Flag Clear All
+TIM2_TSCR1_TSFRZ:   equ    5                                         ; Timer and Modulus Counter Stop While in Freeze Mode
+TIM2_TSCR1_TSWAI:   equ    6                                         ; Timer Module Stops While in Wait
+TIM2_TSCR1_TEN:     equ    7                                         ; Timer Enable
+; bit position masks
+mTIM2_TSCR1_TFFCA:  equ    %00010000
+mTIM2_TSCR1_TSFRZ:  equ    %00100000
+mTIM2_TSCR1_TSWAI:  equ    %01000000
+mTIM2_TSCR1_TEN:    equ    %10000000
+
+
+;*** TIM2_TTOV - TIM2 Timer Toggle On Overflow Register; 0x00000187 ***
+TIM2_TTOV:          equ    $00000187                                ;*** TIM2_TTOV - TIM2 Timer Toggle On Overflow Register; 0x00000187 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+TIM2_TTOV_TOV4:     equ    4                                         ; Toggle On Overflow Bit 4
+TIM2_TTOV_TOV5:     equ    5                                         ; Toggle On Overflow Bit 5
+TIM2_TTOV_TOV6:     equ    6                                         ; Toggle On Overflow Bit 6
+TIM2_TTOV_TOV7:     equ    7                                         ; Toggle On Overflow Bit 7
+; bit position masks
+mTIM2_TTOV_TOV4:    equ    %00010000
+mTIM2_TTOV_TOV5:    equ    %00100000
+mTIM2_TTOV_TOV6:    equ    %01000000
+mTIM2_TTOV_TOV7:    equ    %10000000
+
+
+;*** TIM2_TCTL1 - TIM2 Timer Control Register 1; 0x00000188 ***
+TIM2_TCTL1:         equ    $00000188                                ;*** TIM2_TCTL1 - TIM2 Timer Control Register 1; 0x00000188 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+TIM2_TCTL1_OL4:     equ    0                                         ; Output Level Bit 4
+TIM2_TCTL1_OM4:     equ    1                                         ; Output Mode Bit 4
+TIM2_TCTL1_OL5:     equ    2                                         ; Output Level Bit 5
+TIM2_TCTL1_OM5:     equ    3                                         ; Output Mode Bit 5
+TIM2_TCTL1_OL6:     equ    4                                         ; Output Level Bit 6
+TIM2_TCTL1_OM6:     equ    5                                         ; Output Mode Bit 6
+TIM2_TCTL1_OL7:     equ    6                                         ; Output Level Bit 7
+TIM2_TCTL1_OM7:     equ    7                                         ; Output Mode Bit 7
+; bit position masks
+mTIM2_TCTL1_OL4:    equ    %00000001
+mTIM2_TCTL1_OM4:    equ    %00000010
+mTIM2_TCTL1_OL5:    equ    %00000100
+mTIM2_TCTL1_OM5:    equ    %00001000
+mTIM2_TCTL1_OL6:    equ    %00010000
+mTIM2_TCTL1_OM6:    equ    %00100000
+mTIM2_TCTL1_OL7:    equ    %01000000
+mTIM2_TCTL1_OM7:    equ    %10000000
+
+
+;*** TIM2_TCTL3 - TIM2 Timer Control Register 3; 0x0000018A ***
+TIM2_TCTL3:         equ    $0000018A                                ;*** TIM2_TCTL3 - TIM2 Timer Control Register 3; 0x0000018A ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+TIM2_TCTL3_EDG4A:   equ    0                                         ; Input Capture Edge Control 4A
+TIM2_TCTL3_EDG4B:   equ    1                                         ; Input Capture Edge Control 4B
+TIM2_TCTL3_EDG5A:   equ    2                                         ; Input Capture Edge Control 5A
+TIM2_TCTL3_EDG5B:   equ    3                                         ; Input Capture Edge Control 5B
+TIM2_TCTL3_EDG6A:   equ    4                                         ; Input Capture Edge Control 6A
+TIM2_TCTL3_EDG6B:   equ    5                                         ; Input Capture Edge Control 6B
+TIM2_TCTL3_EDG7A:   equ    6                                         ; Input Capture Edge Control 7A
+TIM2_TCTL3_EDG7B:   equ    7                                         ; Input Capture Edge Control 7B
+; bit position masks
+mTIM2_TCTL3_EDG4A:  equ    %00000001
+mTIM2_TCTL3_EDG4B:  equ    %00000010
+mTIM2_TCTL3_EDG5A:  equ    %00000100
+mTIM2_TCTL3_EDG5B:  equ    %00001000
+mTIM2_TCTL3_EDG6A:  equ    %00010000
+mTIM2_TCTL3_EDG6B:  equ    %00100000
+mTIM2_TCTL3_EDG7A:  equ    %01000000
+mTIM2_TCTL3_EDG7B:  equ    %10000000
+
+
+;*** TIM2_TIE - TIM2 Timer Interrupt Enable Register; 0x0000018C ***
+TIM2_TIE:           equ    $0000018C                                ;*** TIM2_TIE - TIM2 Timer Interrupt Enable Register; 0x0000018C ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+TIM2_TIE_C4I:       equ    4                                         ; Input Capture/Output Compare Interrupt Enable Bit 4
+TIM2_TIE_C5I:       equ    5                                         ; Input Capture/Output Compare Interrupt Enable Bit 5
+TIM2_TIE_C6I:       equ    6                                         ; Input Capture/Output Compare Interrupt Enable Bit 6
+TIM2_TIE_C7I:       equ    7                                         ; Input Capture/Output Compare Interrupt Enable Bit 7
+; bit position masks
+mTIM2_TIE_C4I:      equ    %00010000
+mTIM2_TIE_C5I:      equ    %00100000
+mTIM2_TIE_C6I:      equ    %01000000
+mTIM2_TIE_C7I:      equ    %10000000
+
+
+;*** TIM2_TSCR2 - TIM2 Timer System Control Register 2; 0x0000018D ***
+TIM2_TSCR2:         equ    $0000018D                                ;*** TIM2_TSCR2 - TIM2 Timer System Control Register 2; 0x0000018D ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+TIM2_TSCR2_PR0:     equ    0                                         ; Timer Prescaler Select Bit 0
+TIM2_TSCR2_PR1:     equ    1                                         ; Timer Prescaler Select Bit 1
+TIM2_TSCR2_PR2:     equ    2                                         ; Timer Prescaler Select Bit 2
+TIM2_TSCR2_TCRE:    equ    3                                         ; Timer Counter Reset Enable
+TIM2_TSCR2_TOI:     equ    7                                         ; Timer Overflow Interrupt Enable
+; bit position masks
+mTIM2_TSCR2_PR0:    equ    %00000001
+mTIM2_TSCR2_PR1:    equ    %00000010
+mTIM2_TSCR2_PR2:    equ    %00000100
+mTIM2_TSCR2_TCRE:   equ    %00001000
+mTIM2_TSCR2_TOI:    equ    %10000000
+
+
+;*** TIM2_TFLG1 - TIM2 Main Timer Interrupt Flag 1; 0x0000018E ***
+TIM2_TFLG1:         equ    $0000018E                                ;*** TIM2_TFLG1 - TIM2 Main Timer Interrupt Flag 1; 0x0000018E ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+TIM2_TFLG1_C4F:     equ    4                                         ; Input Capture/Output Compare Channel Flag 4
+TIM2_TFLG1_C5F:     equ    5                                         ; Input Capture/Output Compare Channel Flag 5
+TIM2_TFLG1_C6F:     equ    6                                         ; Input Capture/Output Compare Channel Flag 6
+TIM2_TFLG1_C7F:     equ    7                                         ; Input Capture/Output Compare Channel Flag 7
+; bit position masks
+mTIM2_TFLG1_C4F:    equ    %00010000
+mTIM2_TFLG1_C5F:    equ    %00100000
+mTIM2_TFLG1_C6F:    equ    %01000000
+mTIM2_TFLG1_C7F:    equ    %10000000
+
+
+;*** TIM2_TFLG2 - TIM2 Main Timer Interrupt Flag 2; 0x0000018F ***
+TIM2_TFLG2:         equ    $0000018F                                ;*** TIM2_TFLG2 - TIM2 Main Timer Interrupt Flag 2; 0x0000018F ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+TIM2_TFLG2_TOF:     equ    7                                         ; Timer Overflow Flag
+; bit position masks
+mTIM2_TFLG2_TOF:    equ    %10000000
+
+
+;*** TIM2_TC4 - TIM2 Timer Input Capture/Output Compare Register 4; 0x00000198 ***
+TIM2_TC4:           equ    $00000198                                ;*** TIM2_TC4 - TIM2 Timer Input Capture/Output Compare Register 4; 0x00000198 ***
+
+
+;*** TIM2_TC4Hi - TIM2 Timer Input Capture/Output Compare Register 4 High; 0x00000198 ***
+TIM2_TC4Hi:         equ    $00000198                                ;*** TIM2_TC4Hi - TIM2 Timer Input Capture/Output Compare Register 4 High; 0x00000198 ***
+
+
+;*** TIM2_TC4Lo - TIM2 Timer Input Capture/Output Compare Register 4 Low; 0x00000199 ***
+TIM2_TC4Lo:         equ    $00000199                                ;*** TIM2_TC4Lo - TIM2 Timer Input Capture/Output Compare Register 4 Low; 0x00000199 ***
+
+
+;*** TIM2_TC5 - TIM2 Timer Input Capture/Output Compare Register 5; 0x0000019A ***
+TIM2_TC5:           equ    $0000019A                                ;*** TIM2_TC5 - TIM2 Timer Input Capture/Output Compare Register 5; 0x0000019A ***
+
+
+;*** TIM2_TC5Hi - TIM2 Timer Input Capture/Output Compare Register 5 High; 0x0000019A ***
+TIM2_TC5Hi:         equ    $0000019A                                ;*** TIM2_TC5Hi - TIM2 Timer Input Capture/Output Compare Register 5 High; 0x0000019A ***
+
+
+;*** TIM2_TC5Lo - TIM2 Timer Input Capture/Output Compare Register 5 Low; 0x0000019B ***
+TIM2_TC5Lo:         equ    $0000019B                                ;*** TIM2_TC5Lo - TIM2 Timer Input Capture/Output Compare Register 5 Low; 0x0000019B ***
+
+
+;*** TIM2_TC6 - TIM2 Timer Input Capture/Output Compare Register 6; 0x0000019C ***
+TIM2_TC6:           equ    $0000019C                                ;*** TIM2_TC6 - TIM2 Timer Input Capture/Output Compare Register 6; 0x0000019C ***
+
+
+;*** TIM2_TC6Hi - TIM2 Timer Input Capture/Output Compare Register 6 High; 0x0000019C ***
+TIM2_TC6Hi:         equ    $0000019C                                ;*** TIM2_TC6Hi - TIM2 Timer Input Capture/Output Compare Register 6 High; 0x0000019C ***
+
+
+;*** TIM2_TC6Lo - TIM2 Timer Input Capture/Output Compare Register 6 Low; 0x0000019D ***
+TIM2_TC6Lo:         equ    $0000019D                                ;*** TIM2_TC6Lo - TIM2 Timer Input Capture/Output Compare Register 6 Low; 0x0000019D ***
+
+
+;*** TIM2_TC7 - TIM2 Timer Input Capture/Output Compare Register 7; 0x0000019E ***
+TIM2_TC7:           equ    $0000019E                                ;*** TIM2_TC7 - TIM2 Timer Input Capture/Output Compare Register 7; 0x0000019E ***
+
+
+;*** TIM2_TC7Hi - TIM2 Timer Input Capture/Output Compare Register 7 High; 0x0000019E ***
+TIM2_TC7Hi:         equ    $0000019E                                ;*** TIM2_TC7Hi - TIM2 Timer Input Capture/Output Compare Register 7 High; 0x0000019E ***
+
+
+;*** TIM2_TC7Lo - TIM2 Timer Input Capture/Output Compare Register 7 Low; 0x0000019F ***
+TIM2_TC7Lo:         equ    $0000019F                                ;*** TIM2_TC7Lo - TIM2 Timer Input Capture/Output Compare Register 7 Low; 0x0000019F ***
+
+
+;*** TIM2_PACTL - TIM2 16-Bit Pulse Accumulator A Control Register; 0x000001A0 ***
+TIM2_PACTL:         equ    $000001A0                                ;*** TIM2_PACTL - TIM2 16-Bit Pulse Accumulator A Control Register; 0x000001A0 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+TIM2_PACTL_PAI:     equ    0                                         ; Pulse Accumulator Input Interrupt enable
+TIM2_PACTL_PAOVI:   equ    1                                         ; Pulse Accumulator A Overflow Interrupt enable
+TIM2_PACTL_CLK0:    equ    2                                         ; Clock Select Bit 0
+TIM2_PACTL_CLK1:    equ    3                                         ; Clock Select Bit 1
+TIM2_PACTL_PEDGE:   equ    4                                         ; Pulse Accumulator Edge Control
+TIM2_PACTL_PAMOD:   equ    5                                         ; Pulse Accumulator Mode
+TIM2_PACTL_PAEN:    equ    6                                         ; Pulse Accumulator A System Enable
+; bit position masks
+mTIM2_PACTL_PAI:    equ    %00000001
+mTIM2_PACTL_PAOVI:  equ    %00000010
+mTIM2_PACTL_CLK0:   equ    %00000100
+mTIM2_PACTL_CLK1:   equ    %00001000
+mTIM2_PACTL_PEDGE:  equ    %00010000
+mTIM2_PACTL_PAMOD:  equ    %00100000
+mTIM2_PACTL_PAEN:   equ    %01000000
+
+
+;*** TIM2_PAFLG - TIM2 Pulse Accumulator A Flag Register; 0x000001A1 ***
+TIM2_PAFLG:         equ    $000001A1                                ;*** TIM2_PAFLG - TIM2 Pulse Accumulator A Flag Register; 0x000001A1 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+TIM2_PAFLG_PAIF:    equ    0                                         ; Pulse Accumulator Input edge Flag
+TIM2_PAFLG_PAOVF:   equ    1                                         ; Pulse Accumulator A Overflow Flag
+; bit position masks
+mTIM2_PAFLG_PAIF:   equ    %00000001
+mTIM2_PAFLG_PAOVF:  equ    %00000010
+
+
+;*** TIM2_PACNT - TIM2 Pulse Accumulators Count Register; 0x000001A2 ***
+TIM2_PACNT:         equ    $000001A2                                ;*** TIM2_PACNT - TIM2 Pulse Accumulators Count Register; 0x000001A2 ***
+
+
+;*** PWME - PWM Enable Register; 0x000001E0 ***
+PWME:               equ    $000001E0                                ;*** PWME - PWM Enable Register; 0x000001E0 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PWME_PWME0:         equ    0                                         ; Pulse Width Channel 0 Enable
+PWME_PWME1:         equ    1                                         ; Pulse Width Channel 1 Enable
+PWME_PWME2:         equ    2                                         ; Pulse Width Channel 2 Enable
+PWME_PWME3:         equ    3                                         ; Pulse Width Channel 3 Enable
+PWME_PWME4:         equ    4                                         ; Pulse Width Channel 4 Enable
+PWME_PWME5:         equ    5                                         ; Pulse Width Channel 5 Enable
+; bit position masks
+mPWME_PWME0:        equ    %00000001
+mPWME_PWME1:        equ    %00000010
+mPWME_PWME2:        equ    %00000100
+mPWME_PWME3:        equ    %00001000
+mPWME_PWME4:        equ    %00010000
+mPWME_PWME5:        equ    %00100000
+
+
+;*** PWMPOL - PWM Polarity Register; 0x000001E1 ***
+PWMPOL:             equ    $000001E1                                ;*** PWMPOL - PWM Polarity Register; 0x000001E1 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PWMPOL_PPOL0:       equ    0                                         ; Pulse Width Channel 0 Polarity
+PWMPOL_PPOL1:       equ    1                                         ; Pulse Width Channel 1 Polarity
+PWMPOL_PPOL2:       equ    2                                         ; Pulse Width Channel 2 Polarity
+PWMPOL_PPOL3:       equ    3                                         ; Pulse Width Channel 3 Polarity
+PWMPOL_PPOL4:       equ    4                                         ; Pulse Width Channel 4 Polarity
+PWMPOL_PPOL5:       equ    5                                         ; Pulse Width Channel 5 Polarity
+; bit position masks
+mPWMPOL_PPOL0:      equ    %00000001
+mPWMPOL_PPOL1:      equ    %00000010
+mPWMPOL_PPOL2:      equ    %00000100
+mPWMPOL_PPOL3:      equ    %00001000
+mPWMPOL_PPOL4:      equ    %00010000
+mPWMPOL_PPOL5:      equ    %00100000
+
+
+;*** PWMCLK - PWM Clock Select Register; 0x000001E2 ***
+PWMCLK:             equ    $000001E2                                ;*** PWMCLK - PWM Clock Select Register; 0x000001E2 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PWMCLK_PCLK0:       equ    0                                         ; Pulse Width Channel 0 Clock Select
+PWMCLK_PCLK1:       equ    1                                         ; Pulse Width Channel 1 Clock Select
+PWMCLK_PCLK2:       equ    2                                         ; Pulse Width Channel 2 Clock Select
+PWMCLK_PCLK3:       equ    3                                         ; Pulse Width Channel 3 Clock Select
+PWMCLK_PCLK4:       equ    4                                         ; Pulse Width Channel 4 Clock Select
+PWMCLK_PCLK5:       equ    5                                         ; Pulse Width Channel 5 Clock Select
+; bit position masks
+mPWMCLK_PCLK0:      equ    %00000001
+mPWMCLK_PCLK1:      equ    %00000010
+mPWMCLK_PCLK2:      equ    %00000100
+mPWMCLK_PCLK3:      equ    %00001000
+mPWMCLK_PCLK4:      equ    %00010000
+mPWMCLK_PCLK5:      equ    %00100000
+
+
+;*** PWMPRCLK - PWM Prescale Clock Select Register; 0x000001E3 ***
+PWMPRCLK:           equ    $000001E3                                ;*** PWMPRCLK - PWM Prescale Clock Select Register; 0x000001E3 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PWMPRCLK_PCKA0:     equ    0                                         ; Prescaler Select for Clock A 0
+PWMPRCLK_PCKA1:     equ    1                                         ; Prescaler Select for Clock A 1
+PWMPRCLK_PCKA2:     equ    2                                         ; Prescaler Select for Clock A 2
+PWMPRCLK_PCKB0:     equ    4                                         ; Prescaler Select for Clock B 0
+PWMPRCLK_PCKB1:     equ    5                                         ; Prescaler Select for Clock B 1
+PWMPRCLK_PCKB2:     equ    6                                         ; Prescaler Select for Clock B 2
+; bit position masks
+mPWMPRCLK_PCKA0:    equ    %00000001
+mPWMPRCLK_PCKA1:    equ    %00000010
+mPWMPRCLK_PCKA2:    equ    %00000100
+mPWMPRCLK_PCKB0:    equ    %00010000
+mPWMPRCLK_PCKB1:    equ    %00100000
+mPWMPRCLK_PCKB2:    equ    %01000000
+
+
+;*** PWMCAE - PWM Center Align Enable Register; 0x000001E4 ***
+PWMCAE:             equ    $000001E4                                ;*** PWMCAE - PWM Center Align Enable Register; 0x000001E4 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PWMCAE_CAE0:        equ    0                                         ; Center Aligned Output Mode on channel 0
+PWMCAE_CAE1:        equ    1                                         ; Center Aligned Output Mode on channel 1
+PWMCAE_CAE2:        equ    2                                         ; Center Aligned Output Mode on channel 2
+PWMCAE_CAE3:        equ    3                                         ; Center Aligned Output Mode on channel 3
+PWMCAE_CAE4:        equ    4                                         ; Center Aligned Output Mode on channel 4
+PWMCAE_CAE5:        equ    5                                         ; Center Aligned Output Mode on channel 5
+; bit position masks
+mPWMCAE_CAE0:       equ    %00000001
+mPWMCAE_CAE1:       equ    %00000010
+mPWMCAE_CAE2:       equ    %00000100
+mPWMCAE_CAE3:       equ    %00001000
+mPWMCAE_CAE4:       equ    %00010000
+mPWMCAE_CAE5:       equ    %00100000
+
+
+;*** PWMCTL - PWM Control Register; 0x000001E5 ***
+PWMCTL:             equ    $000001E5                                ;*** PWMCTL - PWM Control Register; 0x000001E5 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PWMCTL_PFRZ:        equ    2                                         ; PWM Counters Stop in Freeze Mode
+PWMCTL_PSWAI:       equ    3                                         ; PWM Stops in Wait Mode
+PWMCTL_CON01:       equ    4                                         ; Concatenate channels 0 and 1
+PWMCTL_CON23:       equ    5                                         ; Concatenate channels 2 and 3
+PWMCTL_CON45:       equ    6                                         ; Concatenate channels 4 and 5
+; bit position masks
+mPWMCTL_PFRZ:       equ    %00000100
+mPWMCTL_PSWAI:      equ    %00001000
+mPWMCTL_CON01:      equ    %00010000
+mPWMCTL_CON23:      equ    %00100000
+mPWMCTL_CON45:      equ    %01000000
+
+
+;*** PWMSCLA - PWM Scale A Register; 0x000001E8 ***
+PWMSCLA:            equ    $000001E8                                ;*** PWMSCLA - PWM Scale A Register; 0x000001E8 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PWMSCLA_BIT0:       equ    0                                         ; PWM Scale A Bit 0
+PWMSCLA_BIT1:       equ    1                                         ; PWM Scale A Bit 1
+PWMSCLA_BIT2:       equ    2                                         ; PWM Scale A Bit 2
+PWMSCLA_BIT3:       equ    3                                         ; PWM Scale A Bit 3
+PWMSCLA_BIT4:       equ    4                                         ; PWM Scale A Bit 4
+PWMSCLA_BIT5:       equ    5                                         ; PWM Scale A Bit 5
+PWMSCLA_BIT6:       equ    6                                         ; PWM Scale A Bit 6
+PWMSCLA_BIT7:       equ    7                                         ; PWM Scale A Bit 7
+; bit position masks
+mPWMSCLA_BIT0:      equ    %00000001
+mPWMSCLA_BIT1:      equ    %00000010
+mPWMSCLA_BIT2:      equ    %00000100
+mPWMSCLA_BIT3:      equ    %00001000
+mPWMSCLA_BIT4:      equ    %00010000
+mPWMSCLA_BIT5:      equ    %00100000
+mPWMSCLA_BIT6:      equ    %01000000
+mPWMSCLA_BIT7:      equ    %10000000
+
+
+;*** PWMSCLB - PWM Scale B Register; 0x000001E9 ***
+PWMSCLB:            equ    $000001E9                                ;*** PWMSCLB - PWM Scale B Register; 0x000001E9 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PWMSCLB_BIT0:       equ    0                                         ; PWM Scale B Bit 0
+PWMSCLB_BIT1:       equ    1                                         ; PWM Scale B Bit 1
+PWMSCLB_BIT2:       equ    2                                         ; PWM Scale B Bit 2
+PWMSCLB_BIT3:       equ    3                                         ; PWM Scale B Bit 3
+PWMSCLB_BIT4:       equ    4                                         ; PWM Scale B Bit 4
+PWMSCLB_BIT5:       equ    5                                         ; PWM Scale B Bit 5
+PWMSCLB_BIT6:       equ    6                                         ; PWM Scale B Bit 6
+PWMSCLB_BIT7:       equ    7                                         ; PWM Scale B Bit 7
+; bit position masks
+mPWMSCLB_BIT0:      equ    %00000001
+mPWMSCLB_BIT1:      equ    %00000010
+mPWMSCLB_BIT2:      equ    %00000100
+mPWMSCLB_BIT3:      equ    %00001000
+mPWMSCLB_BIT4:      equ    %00010000
+mPWMSCLB_BIT5:      equ    %00100000
+mPWMSCLB_BIT6:      equ    %01000000
+mPWMSCLB_BIT7:      equ    %10000000
+
+
+;*** PWMCNT01 - PWM Channel Counter 01 Register; 0x000001EC ***
+PWMCNT01:           equ    $000001EC                                ;*** PWMCNT01 - PWM Channel Counter 01 Register; 0x000001EC ***
+
+
+;*** PWMCNT0 - PWM Channel Counter 0 Register; 0x000001EC ***
+PWMCNT0:            equ    $000001EC                                ;*** PWMCNT0 - PWM Channel Counter 0 Register; 0x000001EC ***
+
+
+;*** PWMCNT1 - PWM Channel Counter 1 Register; 0x000001ED ***
+PWMCNT1:            equ    $000001ED                                ;*** PWMCNT1 - PWM Channel Counter 1 Register; 0x000001ED ***
+
+
+;*** PWMCNT23 - PWM Channel Counter 23 Register; 0x000001EE ***
+PWMCNT23:           equ    $000001EE                                ;*** PWMCNT23 - PWM Channel Counter 23 Register; 0x000001EE ***
+
+
+;*** PWMCNT2 - PWM Channel Counter 2 Register; 0x000001EE ***
+PWMCNT2:            equ    $000001EE                                ;*** PWMCNT2 - PWM Channel Counter 2 Register; 0x000001EE ***
+
+
+;*** PWMCNT3 - PWM Channel Counter 3 Register; 0x000001EF ***
+PWMCNT3:            equ    $000001EF                                ;*** PWMCNT3 - PWM Channel Counter 3 Register; 0x000001EF ***
+
+
+;*** PWMCNT45 - PWM Channel Counter 45 Register; 0x000001F0 ***
+PWMCNT45:           equ    $000001F0                                ;*** PWMCNT45 - PWM Channel Counter 45 Register; 0x000001F0 ***
+
+
+;*** PWMCNT4 - PWM Channel Counter 4 Register; 0x000001F0 ***
+PWMCNT4:            equ    $000001F0                                ;*** PWMCNT4 - PWM Channel Counter 4 Register; 0x000001F0 ***
+
+
+;*** PWMCNT5 - PWM Channel Counter 5 Register; 0x000001F1 ***
+PWMCNT5:            equ    $000001F1                                ;*** PWMCNT5 - PWM Channel Counter 5 Register; 0x000001F1 ***
+
+
+;*** PWMPER01 - PWM Channel Period 01 Register; 0x000001F2 ***
+PWMPER01:           equ    $000001F2                                ;*** PWMPER01 - PWM Channel Period 01 Register; 0x000001F2 ***
+
+
+;*** PWMPER0 - PWM Channel Period 0 Register; 0x000001F2 ***
+PWMPER0:            equ    $000001F2                                ;*** PWMPER0 - PWM Channel Period 0 Register; 0x000001F2 ***
+
+
+;*** PWMPER1 - PWM Channel Period 1 Register; 0x000001F3 ***
+PWMPER1:            equ    $000001F3                                ;*** PWMPER1 - PWM Channel Period 1 Register; 0x000001F3 ***
+
+
+;*** PWMPER23 - PWM Channel Period 23 Register; 0x000001F4 ***
+PWMPER23:           equ    $000001F4                                ;*** PWMPER23 - PWM Channel Period 23 Register; 0x000001F4 ***
+
+
+;*** PWMPER2 - PWM Channel Period 2 Register; 0x000001F4 ***
+PWMPER2:            equ    $000001F4                                ;*** PWMPER2 - PWM Channel Period 2 Register; 0x000001F4 ***
+
+
+;*** PWMPER3 - PWM Channel Period 3 Register; 0x000001F5 ***
+PWMPER3:            equ    $000001F5                                ;*** PWMPER3 - PWM Channel Period 3 Register; 0x000001F5 ***
+
+
+;*** PWMPER45 - PWM Channel Period 45 Register; 0x000001F6 ***
+PWMPER45:           equ    $000001F6                                ;*** PWMPER45 - PWM Channel Period 45 Register; 0x000001F6 ***
+
+
+;*** PWMPER4 - PWM Channel Period 4 Register; 0x000001F6 ***
+PWMPER4:            equ    $000001F6                                ;*** PWMPER4 - PWM Channel Period 4 Register; 0x000001F6 ***
+
+
+;*** PWMPER5 - PWM Channel Period 5 Register; 0x000001F7 ***
+PWMPER5:            equ    $000001F7                                ;*** PWMPER5 - PWM Channel Period 5 Register; 0x000001F7 ***
+
+
+;*** PWMDTY01 - PWM Channel Duty 01 Register; 0x000001F8 ***
+PWMDTY01:           equ    $000001F8                                ;*** PWMDTY01 - PWM Channel Duty 01 Register; 0x000001F8 ***
+
+
+;*** PWMDTY0 - PWM Channel Duty 0 Register; 0x000001F8 ***
+PWMDTY0:            equ    $000001F8                                ;*** PWMDTY0 - PWM Channel Duty 0 Register; 0x000001F8 ***
+
+
+;*** PWMDTY1 - PWM Channel Duty 1 Register; 0x000001F9 ***
+PWMDTY1:            equ    $000001F9                                ;*** PWMDTY1 - PWM Channel Duty 1 Register; 0x000001F9 ***
+
+
+;*** PWMDTY23 - PWM Channel Duty 23 Register; 0x000001FA ***
+PWMDTY23:           equ    $000001FA                                ;*** PWMDTY23 - PWM Channel Duty 23 Register; 0x000001FA ***
+
+
+;*** PWMDTY2 - PWM Channel Duty 2 Register; 0x000001FA ***
+PWMDTY2:            equ    $000001FA                                ;*** PWMDTY2 - PWM Channel Duty 2 Register; 0x000001FA ***
+
+
+;*** PWMDTY3 - PWM Channel Duty 3 Register; 0x000001FB ***
+PWMDTY3:            equ    $000001FB                                ;*** PWMDTY3 - PWM Channel Duty 3 Register; 0x000001FB ***
+
+
+;*** PWMDTY45 - PWM Channel Duty 45 Register; 0x000001FC ***
+PWMDTY45:           equ    $000001FC                                ;*** PWMDTY45 - PWM Channel Duty 45 Register; 0x000001FC ***
+
+
+;*** PWMDTY4 - PWM Channel Duty 4 Register; 0x000001FC ***
+PWMDTY4:            equ    $000001FC                                ;*** PWMDTY4 - PWM Channel Duty 4 Register; 0x000001FC ***
+
+
+;*** PWMDTY5 - PWM Channel Duty 5 Register; 0x000001FD ***
+PWMDTY5:            equ    $000001FD                                ;*** PWMDTY5 - PWM Channel Duty 5 Register; 0x000001FD ***
+
+
+;*** PWMSDN - PWM Shutdown Register; 0x000001FE ***
+PWMSDN:             equ    $000001FE                                ;*** PWMSDN - PWM Shutdown Register; 0x000001FE ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PWMSDN_PWM5ENA:     equ    0                                         ; PWM emergency shutdown Enable
+PWMSDN_PWM5INL:     equ    1                                         ; PWM shutdown active input level for ch. 5
+PWMSDN_PWM5IN:      equ    2                                         ; PWM channel 5 input status
+PWMSDN_PWMLVL:      equ    4                                         ; PWM shutdown output Level
+PWMSDN_PWMRSTRT:    equ    5                                         ; PWM Restart
+PWMSDN_PWMIE:       equ    6                                         ; PWM Interrupt Enable
+PWMSDN_PWMIF:       equ    7                                         ; PWM Interrupt Flag
+; bit position masks
+mPWMSDN_PWM5ENA:    equ    %00000001
+mPWMSDN_PWM5INL:    equ    %00000010
+mPWMSDN_PWM5IN:     equ    %00000100
+mPWMSDN_PWMLVL:     equ    %00010000
+mPWMSDN_PWMRSTRT:   equ    %00100000
+mPWMSDN_PWMIE:      equ    %01000000
+mPWMSDN_PWMIF:      equ    %10000000
+
+
+;*** PMFCFG0 - PMF Configure 0 Register; 0x00000200 ***
+PMFCFG0:            equ    $00000200                                ;*** PMFCFG0 - PMF Configure 0 Register; 0x00000200 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PMFCFG0_INDEPA:     equ    0                                         ; Independent or Complimentary Operation for Pair A
+PMFCFG0_INDEPB:     equ    1                                         ; Independent or Complimentary Operation for Pair B
+PMFCFG0_INDEPC:     equ    2                                         ; Independent or Complimentary Operation for Pair C
+PMFCFG0_EDGEA:      equ    3                                         ; Edge-Aligned or Center-Aligned PWM for Pair A
+PMFCFG0_EDGEB:      equ    4                                         ; Edge-Aligned or Center-Aligned PWM for Pair B
+PMFCFG0_EDGEC:      equ    5                                         ; Edge-Aligned or Center-Aligned PWM for Pair C
+PMFCFG0_MTG:        equ    6                                         ; Multiple Timebase Generators
+PMFCFG0_WP:         equ    7                                         ; Write Protect
+; bit position masks
+mPMFCFG0_INDEPA:    equ    %00000001
+mPMFCFG0_INDEPB:    equ    %00000010
+mPMFCFG0_INDEPC:    equ    %00000100
+mPMFCFG0_EDGEA:     equ    %00001000
+mPMFCFG0_EDGEB:     equ    %00010000
+mPMFCFG0_EDGEC:     equ    %00100000
+mPMFCFG0_MTG:       equ    %01000000
+mPMFCFG0_WP:        equ    %10000000
+
+
+;*** PMFCFG1 - PMF Configure 1 Register; 0x00000201 ***
+PMFCFG1:            equ    $00000201                                ;*** PMFCFG1 - PMF Configure 1 Register; 0x00000201 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PMFCFG1_TOPNEGA:    equ    0                                         ; Pair A Top-side PWM Polarity
+PMFCFG1_BOTNEGA:    equ    1                                         ; Pair A Bottom-side PWM Polarity
+PMFCFG1_TOPNEGB:    equ    2                                         ; Pair B Top-side PWM Polarity
+PMFCFG1_BOTNEGB:    equ    3                                         ; Pair B Bottom-side PWM Polarity
+PMFCFG1_TOPNEGC:    equ    4                                         ; Pair C Top-side PWM Polarity
+PMFCFG1_BOTNEGC:    equ    5                                         ; Pair C Bottom-side PWM Polarity
+PMFCFG1_ENHA:       equ    7                                         ; Enable Hardware Acceleration
+; bit position masks
+mPMFCFG1_TOPNEGA:   equ    %00000001
+mPMFCFG1_BOTNEGA:   equ    %00000010
+mPMFCFG1_TOPNEGB:   equ    %00000100
+mPMFCFG1_BOTNEGB:   equ    %00001000
+mPMFCFG1_TOPNEGC:   equ    %00010000
+mPMFCFG1_BOTNEGC:   equ    %00100000
+mPMFCFG1_ENHA:      equ    %10000000
+
+
+;*** PMFCFG2 - PMF Configure 2 Register; 0x00000202 ***
+PMFCFG2:            equ    $00000202                                ;*** PMFCFG2 - PMF Configure 2 Register; 0x00000202 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PMFCFG2_MSK0:       equ    0                                         ; Mask PWM 0
+PMFCFG2_MSK1:       equ    1                                         ; Mask PWM 1
+PMFCFG2_MSK2:       equ    2                                         ; Mask PWM 2
+PMFCFG2_MSK3:       equ    3                                         ; Mask PWM 3
+PMFCFG2_MSK4:       equ    4                                         ; Mask PWM 4
+PMFCFG2_MSK5:       equ    5                                         ; Mask PWM 5
+; bit position masks
+mPMFCFG2_MSK0:      equ    %00000001
+mPMFCFG2_MSK1:      equ    %00000010
+mPMFCFG2_MSK2:      equ    %00000100
+mPMFCFG2_MSK3:      equ    %00001000
+mPMFCFG2_MSK4:      equ    %00010000
+mPMFCFG2_MSK5:      equ    %00100000
+
+
+;*** PMFCFG3 - PMF Configure 3 Register; 0x00000203 ***
+PMFCFG3:            equ    $00000203                                ;*** PMFCFG3 - PMF Configure 3 Register; 0x00000203 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PMFCFG3_SWAPA:      equ    0                                         ; Swap Pair A
+PMFCFG3_SWAPB:      equ    1                                         ; Swap Pair B
+PMFCFG3_SWAPC:      equ    2                                         ; Swap Pair C
+PMFCFG3_VLMODE0:    equ    3                                         ; Value Register Load Mode Bit 0
+PMFCFG3_VLMODE1:    equ    4                                         ; Value Register Load Mode Bit 1
+PMFCFG3_PMFFRZ:     equ    6                                         ; PMF stops in FREEZE mode
+PMFCFG3_PMFWAI:     equ    7                                         ; PMF stops in WAIT mode
+; bit position masks
+mPMFCFG3_SWAPA:     equ    %00000001
+mPMFCFG3_SWAPB:     equ    %00000010
+mPMFCFG3_SWAPC:     equ    %00000100
+mPMFCFG3_VLMODE0:   equ    %00001000
+mPMFCFG3_VLMODE1:   equ    %00010000
+mPMFCFG3_PMFFRZ:    equ    %01000000
+mPMFCFG3_PMFWAI:    equ    %10000000
+
+
+;*** PMFFCTL - PMF fault control register; 0x00000204 ***
+PMFFCTL:            equ    $00000204                                ;*** PMFFCTL - PMF fault control register; 0x00000204 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PMFFCTL_FIE0:       equ    0                                         ; Fault 0 Pin Interrupt Enable
+PMFFCTL_FMODE0:     equ    1                                         ; Fault 0 Pin Clearing Mode
+PMFFCTL_FIE1:       equ    2                                         ; Fault 1 Pin Interrupt Enable
+PMFFCTL_FMODE1:     equ    3                                         ; Fault 1 Pin Clearing Mode
+PMFFCTL_FIE2:       equ    4                                         ; Fault 2 Pin Interrupt Enable
+PMFFCTL_FMODE2:     equ    5                                         ; Fault 2 Pin Clearing Mode
+PMFFCTL_FIE3:       equ    6                                         ; Fault 3 Pin Interrupt Enable
+PMFFCTL_FMODE3:     equ    7                                         ; Fault 3 Pin Clearing Mode
+; bit position masks
+mPMFFCTL_FIE0:      equ    %00000001
+mPMFFCTL_FMODE0:    equ    %00000010
+mPMFFCTL_FIE1:      equ    %00000100
+mPMFFCTL_FMODE1:    equ    %00001000
+mPMFFCTL_FIE2:      equ    %00010000
+mPMFFCTL_FMODE2:    equ    %00100000
+mPMFFCTL_FIE3:      equ    %01000000
+mPMFFCTL_FMODE3:    equ    %10000000
+
+
+;*** PMFFPIN - PMF fault acknowledge register; 0x00000205 ***
+PMFFPIN:            equ    $00000205                                ;*** PMFFPIN - PMF fault acknowledge register; 0x00000205 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PMFFPIN_FPINE0:     equ    0                                         ; Fault 0 Pin Enable
+PMFFPIN_FPINE1:     equ    2                                         ; Fault 1 Pin Enable
+PMFFPIN_FPINE2:     equ    4                                         ; Fault 2 Pin Enable
+PMFFPIN_FPINE3:     equ    6                                         ; Fault 3 Pin Enable
+; bit position masks
+mPMFFPIN_FPINE0:    equ    %00000001
+mPMFFPIN_FPINE1:    equ    %00000100
+mPMFFPIN_FPINE2:    equ    %00010000
+mPMFFPIN_FPINE3:    equ    %01000000
+
+
+;*** PMFFSTA - PMF fault status register; 0x00000206 ***
+PMFFSTA:            equ    $00000206                                ;*** PMFFSTA - PMF fault status register; 0x00000206 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PMFFSTA_FFLAG0:     equ    0                                         ; Fault 0 pin Flag
+PMFFSTA_FFLAG1:     equ    2                                         ; Fault 1 pin Flag
+PMFFSTA_FFLAG2:     equ    4                                         ; Fault 2 pin Flag
+PMFFSTA_FFLAG3:     equ    6                                         ; Fault 3 pin Flag
+; bit position masks
+mPMFFSTA_FFLAG0:    equ    %00000001
+mPMFFSTA_FFLAG1:    equ    %00000100
+mPMFFSTA_FFLAG2:    equ    %00010000
+mPMFFSTA_FFLAG3:    equ    %01000000
+
+
+;*** PMFQSMP - PMF fault qualifying samples register; 0x00000207 ***
+PMFQSMP:            equ    $00000207                                ;*** PMFQSMP - PMF fault qualifying samples register; 0x00000207 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PMFQSMP_QSMP00:     equ    0                                         ; Fault 0 Qualifying samples, bit 0
+PMFQSMP_QSMP01:     equ    1                                         ; Fault 0 Qualifying samples, bit 1
+PMFQSMP_QSMP10:     equ    2                                         ; Fault 1 Qualifying samples, bit 0
+PMFQSMP_QSMP11:     equ    3                                         ; Fault 1 Qualifying samples, bit 1
+PMFQSMP_QSMP20:     equ    4                                         ; Fault 2 Qualifying samples, bit 0
+PMFQSMP_QSMP21:     equ    5                                         ; Fault 2 Qualifying samples, bit 1
+PMFQSMP_QSMP30:     equ    6                                         ; Fault 3 Qualifying samples, bit 0
+PMFQSMP_QSMP31:     equ    7                                         ; Fault 3 Qualifying samples, bit 1
+; bit position masks
+mPMFQSMP_QSMP00:    equ    %00000001
+mPMFQSMP_QSMP01:    equ    %00000010
+mPMFQSMP_QSMP10:    equ    %00000100
+mPMFQSMP_QSMP11:    equ    %00001000
+mPMFQSMP_QSMP20:    equ    %00010000
+mPMFQSMP_QSMP21:    equ    %00100000
+mPMFQSMP_QSMP30:    equ    %01000000
+mPMFQSMP_QSMP31:    equ    %10000000
+
+
+;*** PMFDMPA - PMF disable mapping A register; 0x00000208 ***
+PMFDMPA:            equ    $00000208                                ;*** PMFDMPA - PMF disable mapping A register; 0x00000208 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PMFDMPA_DMP00:      equ    0                                         ; PMF Disable Mapping A Bit 00
+PMFDMPA_DMP01:      equ    1                                         ; PMF Disable Mapping A Bit 01
+PMFDMPA_DMP02:      equ    2                                         ; PMF Disable Mapping A Bit 02
+PMFDMPA_DMP03:      equ    3                                         ; PMF Disable Mapping A Bit 03
+PMFDMPA_DMP10:      equ    4                                         ; PMF Disable Mapping A Bit 10
+PMFDMPA_DMP11:      equ    5                                         ; PMF Disable Mapping A Bit 11
+PMFDMPA_DMP12:      equ    6                                         ; PMF Disable Mapping A Bit 12
+PMFDMPA_DMP13:      equ    7                                         ; PMF Disable Mapping A Bit 13
+; bit position masks
+mPMFDMPA_DMP00:     equ    %00000001
+mPMFDMPA_DMP01:     equ    %00000010
+mPMFDMPA_DMP02:     equ    %00000100
+mPMFDMPA_DMP03:     equ    %00001000
+mPMFDMPA_DMP10:     equ    %00010000
+mPMFDMPA_DMP11:     equ    %00100000
+mPMFDMPA_DMP12:     equ    %01000000
+mPMFDMPA_DMP13:     equ    %10000000
+
+
+;*** PMFDMPB - PMF disable mapping B register; 0x00000209 ***
+PMFDMPB:            equ    $00000209                                ;*** PMFDMPB - PMF disable mapping B register; 0x00000209 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PMFDMPB_DMP20:      equ    0                                         ; PMF Disable Mapping A Bit 20
+PMFDMPB_DMP21:      equ    1                                         ; PMF Disable Mapping A Bit 21
+PMFDMPB_DMP22:      equ    2                                         ; PMF Disable Mapping A Bit 22
+PMFDMPB_DMP23:      equ    3                                         ; PMF Disable Mapping A Bit 23
+PMFDMPB_DMP30:      equ    4                                         ; PMF Disable Mapping A Bit 30
+PMFDMPB_DMP31:      equ    5                                         ; PMF Disable Mapping A Bit 31
+PMFDMPB_DMP32:      equ    6                                         ; PMF Disable Mapping A Bit 32
+PMFDMPB_DMP33:      equ    7                                         ; PMF Disable Mapping A Bit 33
+; bit position masks
+mPMFDMPB_DMP20:     equ    %00000001
+mPMFDMPB_DMP21:     equ    %00000010
+mPMFDMPB_DMP22:     equ    %00000100
+mPMFDMPB_DMP23:     equ    %00001000
+mPMFDMPB_DMP30:     equ    %00010000
+mPMFDMPB_DMP31:     equ    %00100000
+mPMFDMPB_DMP32:     equ    %01000000
+mPMFDMPB_DMP33:     equ    %10000000
+
+
+;*** PMFDMPC - PMF disable mapping C register; 0x0000020A ***
+PMFDMPC:            equ    $0000020A                                ;*** PMFDMPC - PMF disable mapping C register; 0x0000020A ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PMFDMPC_DMP40:      equ    0                                         ; PMF Disable Mapping A Bit 40
+PMFDMPC_DMP41:      equ    1                                         ; PMF Disable Mapping A Bit 41
+PMFDMPC_DMP42:      equ    2                                         ; PMF Disable Mapping A Bit 42
+PMFDMPC_DMP43:      equ    3                                         ; PMF Disable Mapping A Bit 43
+PMFDMPC_DMP50:      equ    4                                         ; PMF Disable Mapping A Bit 50
+PMFDMPC_DMP51:      equ    5                                         ; PMF Disable Mapping A Bit 51
+PMFDMPC_DMP52:      equ    6                                         ; PMF Disable Mapping A Bit 52
+PMFDMPC_DMP53:      equ    7                                         ; PMF Disable Mapping A Bit 53
+; bit position masks
+mPMFDMPC_DMP40:     equ    %00000001
+mPMFDMPC_DMP41:     equ    %00000010
+mPMFDMPC_DMP42:     equ    %00000100
+mPMFDMPC_DMP43:     equ    %00001000
+mPMFDMPC_DMP50:     equ    %00010000
+mPMFDMPC_DMP51:     equ    %00100000
+mPMFDMPC_DMP52:     equ    %01000000
+mPMFDMPC_DMP53:     equ    %10000000
+
+
+;*** PMFOUTC - PMF output control register; 0x0000020C ***
+PMFOUTC:            equ    $0000020C                                ;*** PMFOUTC - PMF output control register; 0x0000020C ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PMFOUTC_OUTCTL0:    equ    0                                         ; PMF Output Control Bit 0
+PMFOUTC_OUTCTL1:    equ    1                                         ; PMF Output Control Bit 1
+PMFOUTC_OUTCTL2:    equ    2                                         ; PMF Output Control Bit 2
+PMFOUTC_OUTCTL3:    equ    3                                         ; PMF Output Control Bit 3
+PMFOUTC_OUTCTL4:    equ    4                                         ; PMF Output Control Bit 4
+PMFOUTC_OUTCTL5:    equ    5                                         ; PMF Output Control Bit 5
+; bit position masks
+mPMFOUTC_OUTCTL0:   equ    %00000001
+mPMFOUTC_OUTCTL1:   equ    %00000010
+mPMFOUTC_OUTCTL2:   equ    %00000100
+mPMFOUTC_OUTCTL3:   equ    %00001000
+mPMFOUTC_OUTCTL4:   equ    %00010000
+mPMFOUTC_OUTCTL5:   equ    %00100000
+
+
+;*** PMFOUTB - PMF output control bit register; 0x0000020D ***
+PMFOUTB:            equ    $0000020D                                ;*** PMFOUTB - PMF output control bit register; 0x0000020D ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PMFOUTB_OUT0:       equ    0                                         ; PMF Output Control Bit Bit 0
+PMFOUTB_OUT1:       equ    1                                         ; PMF Output Control Bit Bit 1
+PMFOUTB_OUT2:       equ    2                                         ; PMF Output Control Bit Bit 2
+PMFOUTB_OUT3:       equ    3                                         ; PMF Output Control Bit Bit 3
+PMFOUTB_OUT4:       equ    4                                         ; PMF Output Control Bit Bit 4
+PMFOUTB_OUT5:       equ    5                                         ; PMF Output Control Bit Bit 5
+; bit position masks
+mPMFOUTB_OUT0:      equ    %00000001
+mPMFOUTB_OUT1:      equ    %00000010
+mPMFOUTB_OUT2:      equ    %00000100
+mPMFOUTB_OUT3:      equ    %00001000
+mPMFOUTB_OUT4:      equ    %00010000
+mPMFOUTB_OUT5:      equ    %00100000
+
+
+;*** PMFDTMS - PMF deadtime sample register; 0x0000020E ***
+PMFDTMS:            equ    $0000020E                                ;*** PMFDTMS - PMF deadtime sample register; 0x0000020E ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PMFDTMS_DT0:        equ    0                                         ; PMF Deadtime Sample Bit 0
+PMFDTMS_DT1:        equ    1                                         ; PMF Deadtime Sample Bit 1
+PMFDTMS_DT2:        equ    2                                         ; PMF Deadtime Sample Bit 2
+PMFDTMS_DT3:        equ    3                                         ; PMF Deadtime Sample Bit 3
+PMFDTMS_DT4:        equ    4                                         ; PMF Deadtime Sample Bit 4
+PMFDTMS_DT5:        equ    5                                         ; PMF Deadtime Sample Bit 5
+; bit position masks
+mPMFDTMS_DT0:       equ    %00000001
+mPMFDTMS_DT1:       equ    %00000010
+mPMFDTMS_DT2:       equ    %00000100
+mPMFDTMS_DT3:       equ    %00001000
+mPMFDTMS_DT4:       equ    %00010000
+mPMFDTMS_DT5:       equ    %00100000
+
+
+;*** PMFCCTL - PMF correction control register; 0x0000020F ***
+PMFCCTL:            equ    $0000020F                                ;*** PMFCCTL - PMF correction control register; 0x0000020F ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PMFCCTL_IPOLA:      equ    0                                         ; Current Polarity A
+PMFCCTL_IPOLB:      equ    1                                         ; Current Polarity B
+PMFCCTL_IPOLC:      equ    2                                         ; Current Polarity C
+PMFCCTL_ISENS0:     equ    4                                         ; Current status sensing method Bit 0
+PMFCCTL_ISENS1:     equ    5                                         ; Current status sensing method Bit 1
+; bit position masks
+mPMFCCTL_IPOLA:     equ    %00000001
+mPMFCCTL_IPOLB:     equ    %00000010
+mPMFCCTL_IPOLC:     equ    %00000100
+mPMFCCTL_ISENS0:    equ    %00010000
+mPMFCCTL_ISENS1:    equ    %00100000
+
+
+;*** PMFVAL0 - PMF Value 0 Register; 0x00000210 ***
+PMFVAL0:            equ    $00000210                                ;*** PMFVAL0 - PMF Value 0 Register; 0x00000210 ***
+
+
+;*** PMFVAL1 - PMF Value 1 Register; 0x00000212 ***
+PMFVAL1:            equ    $00000212                                ;*** PMFVAL1 - PMF Value 1 Register; 0x00000212 ***
+
+
+;*** PMFVAL2 - PMF Value 2 Register; 0x00000214 ***
+PMFVAL2:            equ    $00000214                                ;*** PMFVAL2 - PMF Value 2 Register; 0x00000214 ***
+
+
+;*** PMFVAL3 - PMF Value 3 Register; 0x00000216 ***
+PMFVAL3:            equ    $00000216                                ;*** PMFVAL3 - PMF Value 3 Register; 0x00000216 ***
+
+
+;*** PMFVAL4 - PMF Value 4 Register; 0x00000218 ***
+PMFVAL4:            equ    $00000218                                ;*** PMFVAL4 - PMF Value 4 Register; 0x00000218 ***
+
+
+;*** PMFVAL5 - PMF Value 5 Register; 0x0000021A ***
+PMFVAL5:            equ    $0000021A                                ;*** PMFVAL5 - PMF Value 5 Register; 0x0000021A ***
+
+
+;*** PMFENCA - PMF Enable Control A Register; 0x00000220 ***
+PMFENCA:            equ    $00000220                                ;*** PMFENCA - PMF Enable Control A Register; 0x00000220 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PMFENCA_PWMRIEA:    equ    0                                         ; PWM Reload Interrupt Enable A
+PMFENCA_LDOKA:      equ    1                                         ; Load Okay A
+PMFENCA_PWMENA:     equ    7                                         ; PWM Generator A Enable
+; bit position masks
+mPMFENCA_PWMRIEA:   equ    %00000001
+mPMFENCA_LDOKA:     equ    %00000010
+mPMFENCA_PWMENA:    equ    %10000000
+
+
+;*** PMFFQCA - PMF Frequency Control A Register; 0x00000221 ***
+PMFFQCA:            equ    $00000221                                ;*** PMFFQCA - PMF Frequency Control A Register; 0x00000221 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PMFFQCA_PWMRFA:     equ    0                                         ; PWM Reload Flag A
+PMFFQCA_PRSCA0:     equ    1                                         ; Prescaler A, bit 0
+PMFFQCA_PRSCA1:     equ    2                                         ; Prescaler A, bit 1
+PMFFQCA_HALFA:      equ    3                                         ; Half Cycle Reload A
+PMFFQCA_LDFQA0:     equ    4                                         ; Load Frequency A, bit 0
+PMFFQCA_LDFQA1:     equ    5                                         ; Load Frequency A, bit 1
+PMFFQCA_LDFQA2:     equ    6                                         ; Load Frequency A, bit 2
+PMFFQCA_LDFQA3:     equ    7                                         ; Load Frequency A, bit 3
+; bit position masks
+mPMFFQCA_PWMRFA:    equ    %00000001
+mPMFFQCA_PRSCA0:    equ    %00000010
+mPMFFQCA_PRSCA1:    equ    %00000100
+mPMFFQCA_HALFA:     equ    %00001000
+mPMFFQCA_LDFQA0:    equ    %00010000
+mPMFFQCA_LDFQA1:    equ    %00100000
+mPMFFQCA_LDFQA2:    equ    %01000000
+mPMFFQCA_LDFQA3:    equ    %10000000
+
+
+;*** PMFCNTA - PMF Counter A Register; 0x00000222 ***
+PMFCNTA:            equ    $00000222                                ;*** PMFCNTA - PMF Counter A Register; 0x00000222 ***
+
+
+;*** PMFMODA - PMF Counter Modulo A Register; 0x00000224 ***
+PMFMODA:            equ    $00000224                                ;*** PMFMODA - PMF Counter Modulo A Register; 0x00000224 ***
+
+
+;*** PMFDTMA - PMF Deadtime A Register; 0x00000226 ***
+PMFDTMA:            equ    $00000226                                ;*** PMFDTMA - PMF Deadtime A Register; 0x00000226 ***
+
+
+;*** PMFENCB - PMF enable control B register; 0x00000228 ***
+PMFENCB:            equ    $00000228                                ;*** PMFENCB - PMF enable control B register; 0x00000228 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PMFENCB_PWMRIEB:    equ    0                                         ; PWM Reload Interrupt Enable B
+PMFENCB_LDOKB:      equ    1                                         ; Load Okay B
+PMFENCB_PWMENB:     equ    7                                         ; PWM Generator B Enable
+; bit position masks
+mPMFENCB_PWMRIEB:   equ    %00000001
+mPMFENCB_LDOKB:     equ    %00000010
+mPMFENCB_PWMENB:    equ    %10000000
+
+
+;*** PMFFQCB - PMF Frequency Control B Register; 0x00000229 ***
+PMFFQCB:            equ    $00000229                                ;*** PMFFQCB - PMF Frequency Control B Register; 0x00000229 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PMFFQCB_PWMRFB:     equ    0                                         ; PWM Reload Flag B
+PMFFQCB_PRSCB0:     equ    1                                         ; Prescaler B, bit 0
+PMFFQCB_PRSCB1:     equ    2                                         ; Prescaler B, bit 1
+PMFFQCB_HALFB:      equ    3                                         ; Half Cycle Reload B
+PMFFQCB_LDFQB0:     equ    4                                         ; Load Frequency B, bit 0
+PMFFQCB_LDFQB1:     equ    5                                         ; Load Frequency B, bit 1
+PMFFQCB_LDFQB2:     equ    6                                         ; Load Frequency B, bit 2
+PMFFQCB_LDFQB3:     equ    7                                         ; Load Frequency B, bit 3
+; bit position masks
+mPMFFQCB_PWMRFB:    equ    %00000001
+mPMFFQCB_PRSCB0:    equ    %00000010
+mPMFFQCB_PRSCB1:    equ    %00000100
+mPMFFQCB_HALFB:     equ    %00001000
+mPMFFQCB_LDFQB0:    equ    %00010000
+mPMFFQCB_LDFQB1:    equ    %00100000
+mPMFFQCB_LDFQB2:    equ    %01000000
+mPMFFQCB_LDFQB3:    equ    %10000000
+
+
+;*** PMFCNTB - PMF Counter B Register; 0x0000022A ***
+PMFCNTB:            equ    $0000022A                                ;*** PMFCNTB - PMF Counter B Register; 0x0000022A ***
+
+
+;*** PMFMODB - PMF Counter Modulo B Register; 0x0000022C ***
+PMFMODB:            equ    $0000022C                                ;*** PMFMODB - PMF Counter Modulo B Register; 0x0000022C ***
+
+
+;*** PMFDTMB - PMF Deadtime B Register; 0x0000022E ***
+PMFDTMB:            equ    $0000022E                                ;*** PMFDTMB - PMF Deadtime B Register; 0x0000022E ***
+
+
+;*** PMFENCC - PMF Enable Control C Register; 0x00000230 ***
+PMFENCC:            equ    $00000230                                ;*** PMFENCC - PMF Enable Control C Register; 0x00000230 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PMFENCC_PWMRIEC:    equ    0                                         ; PWM Reload Interrupt Enable C
+PMFENCC_LDOKC:      equ    1                                         ; Load Okay C
+PMFENCC_PWMENC:     equ    7                                         ; PWM Generator C Enable
+; bit position masks
+mPMFENCC_PWMRIEC:   equ    %00000001
+mPMFENCC_LDOKC:     equ    %00000010
+mPMFENCC_PWMENC:    equ    %10000000
+
+
+;*** PMFFQCC - PMF Frequency Control C Register; 0x00000231 ***
+PMFFQCC:            equ    $00000231                                ;*** PMFFQCC - PMF Frequency Control C Register; 0x00000231 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PMFFQCC_PWMRFC:     equ    0                                         ; PWM Reload Flag C
+PMFFQCC_PRSCC0:     equ    1                                         ; Prescaler C, bit 0
+PMFFQCC_PRSCC1:     equ    2                                         ; Prescaler C, bit 1
+PMFFQCC_HALFC:      equ    3                                         ; Half Cycle Reload C
+PMFFQCC_LDFQC0:     equ    4                                         ; Load Frequency C, bit 0
+PMFFQCC_LDFQC1:     equ    5                                         ; Load Frequency C, bit 1
+PMFFQCC_LDFQC2:     equ    6                                         ; Load Frequency C, bit 2
+PMFFQCC_LDFQC3:     equ    7                                         ; Load Frequency C, bit 3
+; bit position masks
+mPMFFQCC_PWMRFC:    equ    %00000001
+mPMFFQCC_PRSCC0:    equ    %00000010
+mPMFFQCC_PRSCC1:    equ    %00000100
+mPMFFQCC_HALFC:     equ    %00001000
+mPMFFQCC_LDFQC0:    equ    %00010000
+mPMFFQCC_LDFQC1:    equ    %00100000
+mPMFFQCC_LDFQC2:    equ    %01000000
+mPMFFQCC_LDFQC3:    equ    %10000000
+
+
+;*** PMFCNTC - PMF Counter C Register; 0x00000232 ***
+PMFCNTC:            equ    $00000232                                ;*** PMFCNTC - PMF Counter C Register; 0x00000232 ***
+
+
+;*** PMFMODC - PMF Counter Modulo C Register; 0x00000234 ***
+PMFMODC:            equ    $00000234                                ;*** PMFMODC - PMF Counter Modulo C Register; 0x00000234 ***
+
+
+;*** PMFDTMC - PMF Deadtime C Register; 0x00000236 ***
+PMFDTMC:            equ    $00000236                                ;*** PMFDTMC - PMF Deadtime C Register; 0x00000236 ***
+
+
+;*** PTT - Port T I/O Register; 0x00000240 ***
+PTT:                equ    $00000240                                ;*** PTT - Port T I/O Register; 0x00000240 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PTT_PTT0:           equ    0                                         ; Port T Bit 0
+PTT_PTT1:           equ    1                                         ; Port T Bit 1
+PTT_PTT2:           equ    2                                         ; Port T Bit 2
+PTT_PTT3:           equ    3                                         ; Port T Bit 3
+PTT_PTT4:           equ    4                                         ; Port T Bit 4
+PTT_PTT5:           equ    5                                         ; Port T Bit 5
+PTT_PTT6:           equ    6                                         ; Port T Bit 6
+PTT_PTT7:           equ    7                                         ; Port T Bit 7
+; bit position masks
+mPTT_PTT0:          equ    %00000001
+mPTT_PTT1:          equ    %00000010
+mPTT_PTT2:          equ    %00000100
+mPTT_PTT3:          equ    %00001000
+mPTT_PTT4:          equ    %00010000
+mPTT_PTT5:          equ    %00100000
+mPTT_PTT6:          equ    %01000000
+mPTT_PTT7:          equ    %10000000
+
+
+;*** PTIT - Port T Input Register; 0x00000241 ***
+PTIT:               equ    $00000241                                ;*** PTIT - Port T Input Register; 0x00000241 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PTIT_PTIT0:         equ    0                                         ; Port T Bit 0
+PTIT_PTIT1:         equ    1                                         ; Port T Bit 1
+PTIT_PTIT2:         equ    2                                         ; Port T Bit 2
+PTIT_PTIT3:         equ    3                                         ; Port T Bit 3
+PTIT_PTIT4:         equ    4                                         ; Port T Bit 4
+PTIT_PTIT5:         equ    5                                         ; Port T Bit 5
+PTIT_PTIT6:         equ    6                                         ; Port T Bit 6
+PTIT_PTIT7:         equ    7                                         ; Port T Bit 7
+; bit position masks
+mPTIT_PTIT0:        equ    %00000001
+mPTIT_PTIT1:        equ    %00000010
+mPTIT_PTIT2:        equ    %00000100
+mPTIT_PTIT3:        equ    %00001000
+mPTIT_PTIT4:        equ    %00010000
+mPTIT_PTIT5:        equ    %00100000
+mPTIT_PTIT6:        equ    %01000000
+mPTIT_PTIT7:        equ    %10000000
+
+
+;*** DDRT - Port T Data Direction Register; 0x00000242 ***
+DDRT:               equ    $00000242                                ;*** DDRT - Port T Data Direction Register; 0x00000242 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+DDRT_DDRT0:         equ    0                                         ; Data Direction Port T Bit 0
+DDRT_DDRT1:         equ    1                                         ; Data Direction Port T Bit 1
+DDRT_DDRT2:         equ    2                                         ; Data Direction Port T Bit 2
+DDRT_DDRT3:         equ    3                                         ; Data Direction Port T Bit 3
+DDRT_DDRT4:         equ    4                                         ; Data Direction Port T Bit 4
+DDRT_DDRT5:         equ    5                                         ; Data Direction Port T Bit 5
+DDRT_DDRT6:         equ    6                                         ; Data Direction Port T Bit 6
+DDRT_DDRT7:         equ    7                                         ; Data Direction Port T Bit 7
+; bit position masks
+mDDRT_DDRT0:        equ    %00000001
+mDDRT_DDRT1:        equ    %00000010
+mDDRT_DDRT2:        equ    %00000100
+mDDRT_DDRT3:        equ    %00001000
+mDDRT_DDRT4:        equ    %00010000
+mDDRT_DDRT5:        equ    %00100000
+mDDRT_DDRT6:        equ    %01000000
+mDDRT_DDRT7:        equ    %10000000
+
+
+;*** RDRT - Port T Reduced Drive Register; 0x00000243 ***
+RDRT:               equ    $00000243                                ;*** RDRT - Port T Reduced Drive Register; 0x00000243 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+RDRT_RDRT0:         equ    0                                         ; Reduced Drive Port T Bit 0
+RDRT_RDRT1:         equ    1                                         ; Reduced Drive Port T Bit 1
+RDRT_RDRT2:         equ    2                                         ; Reduced Drive Port T Bit 2
+RDRT_RDRT3:         equ    3                                         ; Reduced Drive Port T Bit 3
+RDRT_RDRT4:         equ    4                                         ; Reduced Drive Port T Bit 4
+RDRT_RDRT5:         equ    5                                         ; Reduced Drive Port T Bit 5
+RDRT_RDRT6:         equ    6                                         ; Reduced Drive Port T Bit 6
+RDRT_RDRT7:         equ    7                                         ; Reduced Drive Port T Bit 7
+; bit position masks
+mRDRT_RDRT0:        equ    %00000001
+mRDRT_RDRT1:        equ    %00000010
+mRDRT_RDRT2:        equ    %00000100
+mRDRT_RDRT3:        equ    %00001000
+mRDRT_RDRT4:        equ    %00010000
+mRDRT_RDRT5:        equ    %00100000
+mRDRT_RDRT6:        equ    %01000000
+mRDRT_RDRT7:        equ    %10000000
+
+
+;*** PERT - Port T Pull Device Enable Register; 0x00000244 ***
+PERT:               equ    $00000244                                ;*** PERT - Port T Pull Device Enable Register; 0x00000244 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PERT_PERT0:         equ    0                                         ; Pull Device Enable Port T Bit 0
+PERT_PERT1:         equ    1                                         ; Pull Device Enable Port T Bit 1
+PERT_PERT2:         equ    2                                         ; Pull Device Enable Port T Bit 2
+PERT_PERT3:         equ    3                                         ; Pull Device Enable Port T Bit 3
+PERT_PERT4:         equ    4                                         ; Pull Device Enable Port T Bit 4
+PERT_PERT5:         equ    5                                         ; Pull Device Enable Port T Bit 5
+PERT_PERT6:         equ    6                                         ; Pull Device Enable Port T Bit 6
+PERT_PERT7:         equ    7                                         ; Pull Device Enable Port T Bit 7
+; bit position masks
+mPERT_PERT0:        equ    %00000001
+mPERT_PERT1:        equ    %00000010
+mPERT_PERT2:        equ    %00000100
+mPERT_PERT3:        equ    %00001000
+mPERT_PERT4:        equ    %00010000
+mPERT_PERT5:        equ    %00100000
+mPERT_PERT6:        equ    %01000000
+mPERT_PERT7:        equ    %10000000
+
+
+;*** PPST - Port T Polarity Select Register; 0x00000245 ***
+PPST:               equ    $00000245                                ;*** PPST - Port T Polarity Select Register; 0x00000245 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PPST_PPST0:         equ    0                                         ; Pull Select Port T Bit 0
+PPST_PPST1:         equ    1                                         ; Pull Select Port T Bit 1
+PPST_PPST2:         equ    2                                         ; Pull Select Port T Bit 2
+PPST_PPST3:         equ    3                                         ; Pull Select Port T Bit 3
+PPST_PPST4:         equ    4                                         ; Pull Select Port T Bit 4
+PPST_PPST5:         equ    5                                         ; Pull Select Port T Bit 5
+PPST_PPST6:         equ    6                                         ; Pull Select Port T Bit 6
+PPST_PPST7:         equ    7                                         ; Pull Select Port T Bit 7
+; bit position masks
+mPPST_PPST0:        equ    %00000001
+mPPST_PPST1:        equ    %00000010
+mPPST_PPST2:        equ    %00000100
+mPPST_PPST3:        equ    %00001000
+mPPST_PPST4:        equ    %00010000
+mPPST_PPST5:        equ    %00100000
+mPPST_PPST6:        equ    %01000000
+mPPST_PPST7:        equ    %10000000
+
+
+;*** PTS - Port S I/O Register; 0x00000248 ***
+PTS:                equ    $00000248                                ;*** PTS - Port S I/O Register; 0x00000248 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PTS_PTS0:           equ    0                                         ; Port S Bit 0
+PTS_PTS1:           equ    1                                         ; Port S Bit 1
+PTS_PTS2:           equ    2                                         ; Port S Bit 2
+PTS_PTS3:           equ    3                                         ; Port S Bit 3
+PTS_PTS4:           equ    4                                         ; Port S Bit 4
+PTS_PTS5:           equ    5                                         ; Port S Bit 5
+PTS_PTS6:           equ    6                                         ; Port S Bit 6
+PTS_PTS7:           equ    7                                         ; Port S Bit 7
+; bit position masks
+mPTS_PTS0:          equ    %00000001
+mPTS_PTS1:          equ    %00000010
+mPTS_PTS2:          equ    %00000100
+mPTS_PTS3:          equ    %00001000
+mPTS_PTS4:          equ    %00010000
+mPTS_PTS5:          equ    %00100000
+mPTS_PTS6:          equ    %01000000
+mPTS_PTS7:          equ    %10000000
+
+
+;*** PTIS - Port S Input Register; 0x00000249 ***
+PTIS:               equ    $00000249                                ;*** PTIS - Port S Input Register; 0x00000249 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PTIS_PTIS0:         equ    0                                         ; Port S Bit 0
+PTIS_PTIS1:         equ    1                                         ; Port S Bit 1
+PTIS_PTIS2:         equ    2                                         ; Port S Bit 2
+PTIS_PTIS3:         equ    3                                         ; Port S Bit 3
+PTIS_PTIS4:         equ    4                                         ; Port S Bit 4
+PTIS_PTIS5:         equ    5                                         ; Port S Bit 5
+PTIS_PTIS6:         equ    6                                         ; Port S Bit 6
+PTIS_PTIS7:         equ    7                                         ; Port S Bit 7
+; bit position masks
+mPTIS_PTIS0:        equ    %00000001
+mPTIS_PTIS1:        equ    %00000010
+mPTIS_PTIS2:        equ    %00000100
+mPTIS_PTIS3:        equ    %00001000
+mPTIS_PTIS4:        equ    %00010000
+mPTIS_PTIS5:        equ    %00100000
+mPTIS_PTIS6:        equ    %01000000
+mPTIS_PTIS7:        equ    %10000000
+
+
+;*** DDRS - Port S Data Direction Register; 0x0000024A ***
+DDRS:               equ    $0000024A                                ;*** DDRS - Port S Data Direction Register; 0x0000024A ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+DDRS_DDRS0:         equ    0                                         ; Data Direction Port S Bit 0
+DDRS_DDRS1:         equ    1                                         ; Data Direction Port S Bit 1
+DDRS_DDRS2:         equ    2                                         ; Data Direction Port S Bit 2
+DDRS_DDRS3:         equ    3                                         ; Data Direction Port S Bit 3
+DDRS_DDRS4:         equ    4                                         ; Data Direction Port S Bit 4
+DDRS_DDRS5:         equ    5                                         ; Data Direction Port S Bit 5
+DDRS_DDRS6:         equ    6                                         ; Data Direction Port S Bit 6
+DDRS_DDRS7:         equ    7                                         ; Data Direction Port S Bit 7
+; bit position masks
+mDDRS_DDRS0:        equ    %00000001
+mDDRS_DDRS1:        equ    %00000010
+mDDRS_DDRS2:        equ    %00000100
+mDDRS_DDRS3:        equ    %00001000
+mDDRS_DDRS4:        equ    %00010000
+mDDRS_DDRS5:        equ    %00100000
+mDDRS_DDRS6:        equ    %01000000
+mDDRS_DDRS7:        equ    %10000000
+
+
+;*** RDRS - Port S Reduced Drive Register; 0x0000024B ***
+RDRS:               equ    $0000024B                                ;*** RDRS - Port S Reduced Drive Register; 0x0000024B ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+RDRS_RDRS0:         equ    0                                         ; Reduced Drive Port S Bit 0
+RDRS_RDRS1:         equ    1                                         ; Reduced Drive Port S Bit 1
+RDRS_RDRS2:         equ    2                                         ; Reduced Drive Port S Bit 2
+RDRS_RDRS3:         equ    3                                         ; Reduced Drive Port S Bit 3
+RDRS_RDRS4:         equ    4                                         ; Reduced Drive Port S Bit 4
+RDRS_RDRS5:         equ    5                                         ; Reduced Drive Port S Bit 5
+RDRS_RDRS6:         equ    6                                         ; Reduced Drive Port S Bit 6
+RDRS_RDRS7:         equ    7                                         ; Reduced Drive Port S Bit 7
+; bit position masks
+mRDRS_RDRS0:        equ    %00000001
+mRDRS_RDRS1:        equ    %00000010
+mRDRS_RDRS2:        equ    %00000100
+mRDRS_RDRS3:        equ    %00001000
+mRDRS_RDRS4:        equ    %00010000
+mRDRS_RDRS5:        equ    %00100000
+mRDRS_RDRS6:        equ    %01000000
+mRDRS_RDRS7:        equ    %10000000
+
+
+;*** PERS - Port S Pull Device Enable Register; 0x0000024C ***
+PERS:               equ    $0000024C                                ;*** PERS - Port S Pull Device Enable Register; 0x0000024C ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PERS_PERS0:         equ    0                                         ; Pull Device Enable Port S Bit 0
+PERS_PERS1:         equ    1                                         ; Pull Device Enable Port S Bit 1
+PERS_PERS2:         equ    2                                         ; Pull Device Enable Port S Bit 2
+PERS_PERS3:         equ    3                                         ; Pull Device Enable Port S Bit 3
+PERS_PERS4:         equ    4                                         ; Pull Device Enable Port S Bit 4
+PERS_PERS5:         equ    5                                         ; Pull Device Enable Port S Bit 5
+PERS_PERS6:         equ    6                                         ; Pull Device Enable Port S Bit 6
+PERS_PERS7:         equ    7                                         ; Pull Device Enable Port S Bit 7
+; bit position masks
+mPERS_PERS0:        equ    %00000001
+mPERS_PERS1:        equ    %00000010
+mPERS_PERS2:        equ    %00000100
+mPERS_PERS3:        equ    %00001000
+mPERS_PERS4:        equ    %00010000
+mPERS_PERS5:        equ    %00100000
+mPERS_PERS6:        equ    %01000000
+mPERS_PERS7:        equ    %10000000
+
+
+;*** PPSS - Port S Polarity Select Register; 0x0000024D ***
+PPSS:               equ    $0000024D                                ;*** PPSS - Port S Polarity Select Register; 0x0000024D ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PPSS_PPSS0:         equ    0                                         ; Pull Select Port S Bit 0
+PPSS_PPSS1:         equ    1                                         ; Pull Select Port S Bit 1
+PPSS_PPSS2:         equ    2                                         ; Pull Select Port S Bit 2
+PPSS_PPSS3:         equ    3                                         ; Pull Select Port S Bit 3
+PPSS_PPSS4:         equ    4                                         ; Pull Select Port S Bit 4
+PPSS_PPSS5:         equ    5                                         ; Pull Select Port S Bit 5
+PPSS_PPSS6:         equ    6                                         ; Pull Select Port S Bit 6
+PPSS_PPSS7:         equ    7                                         ; Pull Select Port S Bit 7
+; bit position masks
+mPPSS_PPSS0:        equ    %00000001
+mPPSS_PPSS1:        equ    %00000010
+mPPSS_PPSS2:        equ    %00000100
+mPPSS_PPSS3:        equ    %00001000
+mPPSS_PPSS4:        equ    %00010000
+mPPSS_PPSS5:        equ    %00100000
+mPPSS_PPSS6:        equ    %01000000
+mPPSS_PPSS7:        equ    %10000000
+
+
+;*** WOMS - Port S Wired-Or Mode Register; 0x0000024E ***
+WOMS:               equ    $0000024E                                ;*** WOMS - Port S Wired-Or Mode Register; 0x0000024E ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+WOMS_WOMS0:         equ    0                                         ; Wired-Or Mode Port S Bit 0
+WOMS_WOMS1:         equ    1                                         ; Wired-Or Mode Port S Bit 1
+WOMS_WOMS2:         equ    2                                         ; Wired-Or Mode Port S Bit 2
+WOMS_WOMS3:         equ    3                                         ; Wired-Or Mode Port S Bit 3
+WOMS_WOMS4:         equ    4                                         ; Wired-Or Mode Port S Bit 4
+WOMS_WOMS5:         equ    5                                         ; Wired-Or Mode Port S Bit 5
+WOMS_WOMS6:         equ    6                                         ; Wired-Or Mode Port S Bit 6
+WOMS_WOMS7:         equ    7                                         ; Wired-Or Mode Port S Bit 7
+; bit position masks
+mWOMS_WOMS0:        equ    %00000001
+mWOMS_WOMS1:        equ    %00000010
+mWOMS_WOMS2:        equ    %00000100
+mWOMS_WOMS3:        equ    %00001000
+mWOMS_WOMS4:        equ    %00010000
+mWOMS_WOMS5:        equ    %00100000
+mWOMS_WOMS6:        equ    %01000000
+mWOMS_WOMS7:        equ    %10000000
+
+
+;*** PTM - Port M I/O Register; 0x00000250 ***
+PTM:                equ    $00000250                                ;*** PTM - Port M I/O Register; 0x00000250 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PTM_PTM0:           equ    0                                         ; Port M Bit 0
+PTM_PTM1:           equ    1                                         ; Port M Bit 1
+PTM_PTM3:           equ    3                                         ; Port M Bit 3
+PTM_PTM4:           equ    4                                         ; Port M Bit 4
+PTM_PTM5:           equ    5                                         ; Port M Bit 5
+PTM_PTM6:           equ    6                                         ; Port M Bit 6
+PTM_PTM7:           equ    7                                         ; Port M Bit 7
+; bit position masks
+mPTM_PTM0:          equ    %00000001
+mPTM_PTM1:          equ    %00000010
+mPTM_PTM3:          equ    %00001000
+mPTM_PTM4:          equ    %00010000
+mPTM_PTM5:          equ    %00100000
+mPTM_PTM6:          equ    %01000000
+mPTM_PTM7:          equ    %10000000
+
+
+;*** PTIM - Port M Input Register; 0x00000251 ***
+PTIM:               equ    $00000251                                ;*** PTIM - Port M Input Register; 0x00000251 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PTIM_PTIM0:         equ    0                                         ; Port M Bit 0
+PTIM_PTIM1:         equ    1                                         ; Port M Bit 1
+PTIM_PTIM3:         equ    3                                         ; Port M Bit 3
+PTIM_PTIM4:         equ    4                                         ; Port M Bit 4
+PTIM_PTIM5:         equ    5                                         ; Port M Bit 5
+PTIM_PTIM6:         equ    6                                         ; Port M Bit 6
+PTIM_PTIM7:         equ    7                                         ; Port M Bit 7
+; bit position masks
+mPTIM_PTIM0:        equ    %00000001
+mPTIM_PTIM1:        equ    %00000010
+mPTIM_PTIM3:        equ    %00001000
+mPTIM_PTIM4:        equ    %00010000
+mPTIM_PTIM5:        equ    %00100000
+mPTIM_PTIM6:        equ    %01000000
+mPTIM_PTIM7:        equ    %10000000
+
+
+;*** DDRM - Port M Data Direction Register; 0x00000252 ***
+DDRM:               equ    $00000252                                ;*** DDRM - Port M Data Direction Register; 0x00000252 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+DDRM_DDRM0:         equ    0                                         ; Data Direction Port M Bit 0
+DDRM_DDRM1:         equ    1                                         ; Data Direction Port M Bit 1
+DDRM_DDRM3:         equ    3                                         ; Data Direction Port M Bit 3
+DDRM_DDRM4:         equ    4                                         ; Data Direction Port M Bit 4
+DDRM_DDRM5:         equ    5                                         ; Data Direction Port M Bit 5
+DDRM_DDRM6:         equ    6                                         ; Data Direction Port M Bit 6
+DDRM_DDRM7:         equ    7                                         ; Data Direction Port M Bit 7
+; bit position masks
+mDDRM_DDRM0:        equ    %00000001
+mDDRM_DDRM1:        equ    %00000010
+mDDRM_DDRM3:        equ    %00001000
+mDDRM_DDRM4:        equ    %00010000
+mDDRM_DDRM5:        equ    %00100000
+mDDRM_DDRM6:        equ    %01000000
+mDDRM_DDRM7:        equ    %10000000
+
+
+;*** RDRM - Port M Reduced Drive Register; 0x00000253 ***
+RDRM:               equ    $00000253                                ;*** RDRM - Port M Reduced Drive Register; 0x00000253 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+RDRM_RDRM0:         equ    0                                         ; Reduced Drive Port M Bit 0
+RDRM_RDRM1:         equ    1                                         ; Reduced Drive Port M Bit 1
+RDRM_RDRM3:         equ    3                                         ; Reduced Drive Port M Bit 3
+RDRM_RDRM4:         equ    4                                         ; Reduced Drive Port M Bit 4
+RDRM_RDRM5:         equ    5                                         ; Reduced Drive Port M Bit 5
+RDRM_RDRM6:         equ    6                                         ; Reduced Drive Port M Bit 6
+RDRM_RDRM7:         equ    7                                         ; Reduced Drive Port M Bit 7
+; bit position masks
+mRDRM_RDRM0:        equ    %00000001
+mRDRM_RDRM1:        equ    %00000010
+mRDRM_RDRM3:        equ    %00001000
+mRDRM_RDRM4:        equ    %00010000
+mRDRM_RDRM5:        equ    %00100000
+mRDRM_RDRM6:        equ    %01000000
+mRDRM_RDRM7:        equ    %10000000
+
+
+;*** PERM - Port M Pull Device Enable Register; 0x00000254 ***
+PERM:               equ    $00000254                                ;*** PERM - Port M Pull Device Enable Register; 0x00000254 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PERM_PERM0:         equ    0                                         ; Pull Device Enable Port M Bit 0
+PERM_PERM1:         equ    1                                         ; Pull Device Enable Port M Bit 1
+PERM_PERM3:         equ    3                                         ; Pull Device Enable Port M Bit 3
+PERM_PERM4:         equ    4                                         ; Pull Device Enable Port M Bit 4
+PERM_PERM5:         equ    5                                         ; Pull Device Enable Port M Bit 5
+PERM_PERM6:         equ    6                                         ; Pull Device Enable Port M Bit 6
+PERM_PERM7:         equ    7                                         ; Pull Device Enable Port M Bit 7
+; bit position masks
+mPERM_PERM0:        equ    %00000001
+mPERM_PERM1:        equ    %00000010
+mPERM_PERM3:        equ    %00001000
+mPERM_PERM4:        equ    %00010000
+mPERM_PERM5:        equ    %00100000
+mPERM_PERM6:        equ    %01000000
+mPERM_PERM7:        equ    %10000000
+
+
+;*** PPSM - Port M Polarity Select Register; 0x00000255 ***
+PPSM:               equ    $00000255                                ;*** PPSM - Port M Polarity Select Register; 0x00000255 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PPSM_PPSM0:         equ    0                                         ; Pull Select Port M Bit 0
+PPSM_PPSM1:         equ    1                                         ; Pull Select Port M Bit 1
+PPSM_PPSM3:         equ    3                                         ; Pull Select Port M Bit 3
+PPSM_PPSM4:         equ    4                                         ; Pull Select Port M Bit 4
+PPSM_PPSM5:         equ    5                                         ; Pull Select Port M Bit 5
+PPSM_PPSM6:         equ    6                                         ; Pull Select Port M Bit 6
+PPSM_PPSM7:         equ    7                                         ; Pull Select Port M Bit 7
+; bit position masks
+mPPSM_PPSM0:        equ    %00000001
+mPPSM_PPSM1:        equ    %00000010
+mPPSM_PPSM3:        equ    %00001000
+mPPSM_PPSM4:        equ    %00010000
+mPPSM_PPSM5:        equ    %00100000
+mPPSM_PPSM6:        equ    %01000000
+mPPSM_PPSM7:        equ    %10000000
+
+
+;*** WOMM - Port M Wired-Or Mode Register; 0x00000256 ***
+WOMM:               equ    $00000256                                ;*** WOMM - Port M Wired-Or Mode Register; 0x00000256 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+WOMM_WOMM4:         equ    4                                         ; Wired-Or Mode Port M Bit 4
+WOMM_WOMM5:         equ    5                                         ; Wired-Or Mode Port M Bit 5
+WOMM_WOMM6:         equ    6                                         ; Wired-Or Mode Port M Bit 6
+WOMM_WOMM7:         equ    7                                         ; Wired-Or Mode Port M Bit 7
+; bit position masks
+mWOMM_WOMM4:        equ    %00010000
+mWOMM_WOMM5:        equ    %00100000
+mWOMM_WOMM6:        equ    %01000000
+mWOMM_WOMM7:        equ    %10000000
+
+
+;*** PTP - Port P I/O Register; 0x00000258 ***
+PTP:                equ    $00000258                                ;*** PTP - Port P I/O Register; 0x00000258 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PTP_PTP0:           equ    0                                         ; Port P Bit 0
+PTP_PTP1:           equ    1                                         ; Port P Bit 1
+PTP_PTP2:           equ    2                                         ; Port P Bit 2
+PTP_PTP3:           equ    3                                         ; Port P Bit 3
+PTP_PTP4:           equ    4                                         ; Port P Bit 4
+PTP_PTP5:           equ    5                                         ; Port P Bit 5
+; bit position masks
+mPTP_PTP0:          equ    %00000001
+mPTP_PTP1:          equ    %00000010
+mPTP_PTP2:          equ    %00000100
+mPTP_PTP3:          equ    %00001000
+mPTP_PTP4:          equ    %00010000
+mPTP_PTP5:          equ    %00100000
+
+
+;*** PTIP - Port P Input Register; 0x00000259 ***
+PTIP:               equ    $00000259                                ;*** PTIP - Port P Input Register; 0x00000259 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PTIP_PTIP0:         equ    0                                         ; Port P Bit 0
+PTIP_PTIP1:         equ    1                                         ; Port P Bit 1
+PTIP_PTIP2:         equ    2                                         ; Port P Bit 2
+PTIP_PTIP3:         equ    3                                         ; Port P Bit 3
+PTIP_PTIP4:         equ    4                                         ; Port P Bit 4
+PTIP_PTIP5:         equ    5                                         ; Port P Bit 5
+; bit position masks
+mPTIP_PTIP0:        equ    %00000001
+mPTIP_PTIP1:        equ    %00000010
+mPTIP_PTIP2:        equ    %00000100
+mPTIP_PTIP3:        equ    %00001000
+mPTIP_PTIP4:        equ    %00010000
+mPTIP_PTIP5:        equ    %00100000
+
+
+;*** DDRP - Port P Data Direction Register; 0x0000025A ***
+DDRP:               equ    $0000025A                                ;*** DDRP - Port P Data Direction Register; 0x0000025A ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+DDRP_DDRP0:         equ    0                                         ; Data Direction Port P Bit 0
+DDRP_DDRP1:         equ    1                                         ; Data Direction Port P Bit 1
+DDRP_DDRP2:         equ    2                                         ; Data Direction Port P Bit 2
+DDRP_DDRP3:         equ    3                                         ; Data Direction Port P Bit 3
+DDRP_DDRP4:         equ    4                                         ; Data Direction Port P Bit 4
+DDRP_DDRP5:         equ    5                                         ; Data Direction Port P Bit 5
+; bit position masks
+mDDRP_DDRP0:        equ    %00000001
+mDDRP_DDRP1:        equ    %00000010
+mDDRP_DDRP2:        equ    %00000100
+mDDRP_DDRP3:        equ    %00001000
+mDDRP_DDRP4:        equ    %00010000
+mDDRP_DDRP5:        equ    %00100000
+
+
+;*** RDRP - Port P Reduced Drive Register; 0x0000025B ***
+RDRP:               equ    $0000025B                                ;*** RDRP - Port P Reduced Drive Register; 0x0000025B ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+RDRP_RDRP0:         equ    0                                         ; Reduced Drive Port P Bit 0
+RDRP_RDRP1:         equ    1                                         ; Reduced Drive Port P Bit 1
+RDRP_RDRP2:         equ    2                                         ; Reduced Drive Port P Bit 2
+RDRP_RDRP3:         equ    3                                         ; Reduced Drive Port P Bit 3
+RDRP_RDRP4:         equ    4                                         ; Reduced Drive Port P Bit 4
+RDRP_RDRP5:         equ    5                                         ; Reduced Drive Port P Bit 5
+; bit position masks
+mRDRP_RDRP0:        equ    %00000001
+mRDRP_RDRP1:        equ    %00000010
+mRDRP_RDRP2:        equ    %00000100
+mRDRP_RDRP3:        equ    %00001000
+mRDRP_RDRP4:        equ    %00010000
+mRDRP_RDRP5:        equ    %00100000
+
+
+;*** PERP - Port P Pull Device Enable Register; 0x0000025C ***
+PERP:               equ    $0000025C                                ;*** PERP - Port P Pull Device Enable Register; 0x0000025C ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PERP_PERP0:         equ    0                                         ; Pull Device Enable Port P Bit 0
+PERP_PERP1:         equ    1                                         ; Pull Device Enable Port P Bit 1
+PERP_PERP2:         equ    2                                         ; Pull Device Enable Port P Bit 2
+PERP_PERP3:         equ    3                                         ; Pull Device Enable Port P Bit 3
+PERP_PERP4:         equ    4                                         ; Pull Device Enable Port P Bit 4
+PERP_PERP5:         equ    5                                         ; Pull Device Enable Port P Bit 5
+; bit position masks
+mPERP_PERP0:        equ    %00000001
+mPERP_PERP1:        equ    %00000010
+mPERP_PERP2:        equ    %00000100
+mPERP_PERP3:        equ    %00001000
+mPERP_PERP4:        equ    %00010000
+mPERP_PERP5:        equ    %00100000
+
+
+;*** PPSP - Port P Polarity Select Register; 0x0000025D ***
+PPSP:               equ    $0000025D                                ;*** PPSP - Port P Polarity Select Register; 0x0000025D ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PPSP_PPSP0:         equ    0                                         ; Pull Select Port P Bit 0
+PPSP_PPSP1:         equ    1                                         ; Pull Select Port P Bit 1
+PPSP_PPSP2:         equ    2                                         ; Pull Select Port P Bit 2
+PPSP_PPSP3:         equ    3                                         ; Pull Select Port P Bit 3
+PPSP_PPSP4:         equ    4                                         ; Pull Select Port P Bit 4
+PPSP_PPSP5:         equ    5                                         ; Pull Select Port P Bit 5
+; bit position masks
+mPPSP_PPSP0:        equ    %00000001
+mPPSP_PPSP1:        equ    %00000010
+mPPSP_PPSP2:        equ    %00000100
+mPPSP_PPSP3:        equ    %00001000
+mPPSP_PPSP4:        equ    %00010000
+mPPSP_PPSP5:        equ    %00100000
+
+
+;*** PTQ - Port Q I/O Register; 0x00000260 ***
+PTQ:                equ    $00000260                                ;*** PTQ - Port Q I/O Register; 0x00000260 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PTQ_PTQ0:           equ    0                                         ; Port Q Bit 0
+PTQ_PTQ1:           equ    1                                         ; Port Q Bit 1
+PTQ_PTQ2:           equ    2                                         ; Port Q Bit 2
+PTQ_PTQ3:           equ    3                                         ; Port Q Bit 3
+PTQ_PTQ4:           equ    4                                         ; Port Q Bit 4
+PTQ_PTQ5:           equ    5                                         ; Port Q Bit 5
+PTQ_PTQ6:           equ    6                                         ; Port Q Bit 6
+; bit position masks
+mPTQ_PTQ0:          equ    %00000001
+mPTQ_PTQ1:          equ    %00000010
+mPTQ_PTQ2:          equ    %00000100
+mPTQ_PTQ3:          equ    %00001000
+mPTQ_PTQ4:          equ    %00010000
+mPTQ_PTQ5:          equ    %00100000
+mPTQ_PTQ6:          equ    %01000000
+
+
+;*** PTIQ - Port Q Input Register; 0x00000261 ***
+PTIQ:               equ    $00000261                                ;*** PTIQ - Port Q Input Register; 0x00000261 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PTIQ_PTIQ0:         equ    0                                         ; Port Q Bit 0
+PTIQ_PTIQ1:         equ    1                                         ; Port Q Bit 1
+PTIQ_PTIQ2:         equ    2                                         ; Port Q Bit 2
+PTIQ_PTIQ3:         equ    3                                         ; Port Q Bit 3
+PTIQ_PTIQ4:         equ    4                                         ; Port Q Bit 4
+PTIQ_PTIQ5:         equ    5                                         ; Port Q Bit 5
+PTIQ_PTIQ6:         equ    6                                         ; Port Q Bit 6
+; bit position masks
+mPTIQ_PTIQ0:        equ    %00000001
+mPTIQ_PTIQ1:        equ    %00000010
+mPTIQ_PTIQ2:        equ    %00000100
+mPTIQ_PTIQ3:        equ    %00001000
+mPTIQ_PTIQ4:        equ    %00010000
+mPTIQ_PTIQ5:        equ    %00100000
+mPTIQ_PTIQ6:        equ    %01000000
+
+
+;*** DDRQ - Port Q Data Direction Register; 0x00000262 ***
+DDRQ:               equ    $00000262                                ;*** DDRQ - Port Q Data Direction Register; 0x00000262 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+DDRQ_DDRQ0:         equ    0                                         ; Data Direction Port Q Bit 0
+DDRQ_DDRQ1:         equ    1                                         ; Data Direction Port Q Bit 1
+DDRQ_DDRQ2:         equ    2                                         ; Data Direction Port Q Bit 2
+DDRQ_DDRQ3:         equ    3                                         ; Data Direction Port Q Bit 3
+DDRQ_DDRQ4:         equ    4                                         ; Data Direction Port Q Bit 4
+DDRQ_DDRQ5:         equ    5                                         ; Data Direction Port Q Bit 5
+DDRQ_DDRQ6:         equ    6                                         ; Data Direction Port Q Bit 6
+; bit position masks
+mDDRQ_DDRQ0:        equ    %00000001
+mDDRQ_DDRQ1:        equ    %00000010
+mDDRQ_DDRQ2:        equ    %00000100
+mDDRQ_DDRQ3:        equ    %00001000
+mDDRQ_DDRQ4:        equ    %00010000
+mDDRQ_DDRQ5:        equ    %00100000
+mDDRQ_DDRQ6:        equ    %01000000
+
+
+;*** RDRQ - Port Q Reduced Drive Register; 0x00000263 ***
+RDRQ:               equ    $00000263                                ;*** RDRQ - Port Q Reduced Drive Register; 0x00000263 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+RDRQ_RDRQ0:         equ    0                                         ; Reduced Drive Port Q Bit 0
+RDRQ_RDRQ1:         equ    1                                         ; Reduced Drive Port Q Bit 1
+RDRQ_RDRQ2:         equ    2                                         ; Reduced Drive Port Q Bit 2
+RDRQ_RDRQ3:         equ    3                                         ; Reduced Drive Port Q Bit 3
+RDRQ_RDRQ4:         equ    4                                         ; Reduced Drive Port Q Bit 4
+RDRQ_RDRQ5:         equ    5                                         ; Reduced Drive Port Q Bit 5
+RDRQ_RDRQ6:         equ    6                                         ; Reduced Drive Port Q Bit 6
+; bit position masks
+mRDRQ_RDRQ0:        equ    %00000001
+mRDRQ_RDRQ1:        equ    %00000010
+mRDRQ_RDRQ2:        equ    %00000100
+mRDRQ_RDRQ3:        equ    %00001000
+mRDRQ_RDRQ4:        equ    %00010000
+mRDRQ_RDRQ5:        equ    %00100000
+mRDRQ_RDRQ6:        equ    %01000000
+
+
+;*** PERQ - Port Q Pull Device Enable Register; 0x00000264 ***
+PERQ:               equ    $00000264                                ;*** PERQ - Port Q Pull Device Enable Register; 0x00000264 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PERQ_PERQ0:         equ    0                                         ; Pull Device Enable Port Q Bit 0
+PERQ_PERQ1:         equ    1                                         ; Pull Device Enable Port Q Bit 1
+PERQ_PERQ2:         equ    2                                         ; Pull Device Enable Port Q Bit 2
+PERQ_PERQ3:         equ    3                                         ; Pull Device Enable Port Q Bit 3
+PERQ_PERQ4:         equ    4                                         ; Pull Device Enable Port Q Bit 4
+PERQ_PERQ5:         equ    5                                         ; Pull Device Enable Port Q Bit 5
+PERQ_PERQ6:         equ    6                                         ; Pull Device Enable Port Q Bit 6
+; bit position masks
+mPERQ_PERQ0:        equ    %00000001
+mPERQ_PERQ1:        equ    %00000010
+mPERQ_PERQ2:        equ    %00000100
+mPERQ_PERQ3:        equ    %00001000
+mPERQ_PERQ4:        equ    %00010000
+mPERQ_PERQ5:        equ    %00100000
+mPERQ_PERQ6:        equ    %01000000
+
+
+;*** PPSQ - Port Q Polarity Select Register; 0x00000265 ***
+PPSQ:               equ    $00000265                                ;*** PPSQ - Port Q Polarity Select Register; 0x00000265 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PPSQ_PPSQ0:         equ    0                                         ; Pull Select Port Q Bit 0
+PPSQ_PPSQ1:         equ    1                                         ; Pull Select Port Q Bit 1
+PPSQ_PPSQ2:         equ    2                                         ; Pull Select Port Q Bit 2
+PPSQ_PPSQ3:         equ    3                                         ; Pull Select Port Q Bit 3
+PPSQ_PPSQ4:         equ    4                                         ; Pull Select Port Q Bit 4
+PPSQ_PPSQ5:         equ    5                                         ; Pull Select Port Q Bit 5
+PPSQ_PPSQ6:         equ    6                                         ; Pull Select Port Q Bit 6
+; bit position masks
+mPPSQ_PPSQ0:        equ    %00000001
+mPPSQ_PPSQ1:        equ    %00000010
+mPPSQ_PPSQ2:        equ    %00000100
+mPPSQ_PPSQ3:        equ    %00001000
+mPPSQ_PPSQ4:        equ    %00010000
+mPPSQ_PPSQ5:        equ    %00100000
+mPPSQ_PPSQ6:        equ    %01000000
+
+
+;*** PTU - Port U I/O Register; 0x00000268 ***
+PTU:                equ    $00000268                                ;*** PTU - Port U I/O Register; 0x00000268 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PTU_PTU0:           equ    0                                         ; Port U Bit 0
+PTU_PTU1:           equ    1                                         ; Port U Bit 1
+PTU_PTU2:           equ    2                                         ; Port U Bit 2
+PTU_PTU3:           equ    3                                         ; Port U Bit 3
+PTU_PTU4:           equ    4                                         ; Port U Bit 4
+PTU_PTU5:           equ    5                                         ; Port U Bit 5
+PTU_PTU6:           equ    6                                         ; Port U Bit 6
+PTU_PTU7:           equ    7                                         ; Port U Bit 7
+; bit position masks
+mPTU_PTU0:          equ    %00000001
+mPTU_PTU1:          equ    %00000010
+mPTU_PTU2:          equ    %00000100
+mPTU_PTU3:          equ    %00001000
+mPTU_PTU4:          equ    %00010000
+mPTU_PTU5:          equ    %00100000
+mPTU_PTU6:          equ    %01000000
+mPTU_PTU7:          equ    %10000000
+
+
+;*** PTIU - Port U Input Register; 0x00000269 ***
+PTIU:               equ    $00000269                                ;*** PTIU - Port U Input Register; 0x00000269 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PTIU_PTIU0:         equ    0                                         ; Port U Bit 0
+PTIU_PTIU1:         equ    1                                         ; Port U Bit 1
+PTIU_PTIU2:         equ    2                                         ; Port U Bit 2
+PTIU_PTIU3:         equ    3                                         ; Port U Bit 3
+PTIU_PTIU4:         equ    4                                         ; Port U Bit 4
+PTIU_PTIU5:         equ    5                                         ; Port U Bit 5
+PTIU_PTIU6:         equ    6                                         ; Port U Bit 6
+PTIU_PTIU7:         equ    7                                         ; Port U Bit 7
+; bit position masks
+mPTIU_PTIU0:        equ    %00000001
+mPTIU_PTIU1:        equ    %00000010
+mPTIU_PTIU2:        equ    %00000100
+mPTIU_PTIU3:        equ    %00001000
+mPTIU_PTIU4:        equ    %00010000
+mPTIU_PTIU5:        equ    %00100000
+mPTIU_PTIU6:        equ    %01000000
+mPTIU_PTIU7:        equ    %10000000
+
+
+;*** DDRU - Port U Data Direction Register; 0x0000026A ***
+DDRU:               equ    $0000026A                                ;*** DDRU - Port U Data Direction Register; 0x0000026A ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+DDRU_DDRU0:         equ    0                                         ; Data Direction Port U Bit 0
+DDRU_DDRU1:         equ    1                                         ; Data Direction Port U Bit 1
+DDRU_DDRU2:         equ    2                                         ; Data Direction Port U Bit 2
+DDRU_DDRU3:         equ    3                                         ; Data Direction Port U Bit 3
+DDRU_DDRU4:         equ    4                                         ; Data Direction Port U Bit 4
+DDRU_DDRU5:         equ    5                                         ; Data Direction Port U Bit 5
+DDRU_DDRU6:         equ    6                                         ; Data Direction Port U Bit 6
+DDRU_DDRU7:         equ    7                                         ; Data Direction Port U Bit 7
+; bit position masks
+mDDRU_DDRU0:        equ    %00000001
+mDDRU_DDRU1:        equ    %00000010
+mDDRU_DDRU2:        equ    %00000100
+mDDRU_DDRU3:        equ    %00001000
+mDDRU_DDRU4:        equ    %00010000
+mDDRU_DDRU5:        equ    %00100000
+mDDRU_DDRU6:        equ    %01000000
+mDDRU_DDRU7:        equ    %10000000
+
+
+;*** RDRU - Port U Reduced Drive Register; 0x0000026B ***
+RDRU:               equ    $0000026B                                ;*** RDRU - Port U Reduced Drive Register; 0x0000026B ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+RDRU_RDRU0:         equ    0                                         ; Reduced Drive Port U Bit 0
+RDRU_RDRU1:         equ    1                                         ; Reduced Drive Port U Bit 1
+RDRU_RDRU2:         equ    2                                         ; Reduced Drive Port U Bit 2
+RDRU_RDRU3:         equ    3                                         ; Reduced Drive Port U Bit 3
+RDRU_RDRU4:         equ    4                                         ; Reduced Drive Port U Bit 4
+RDRU_RDRU5:         equ    5                                         ; Reduced Drive Port U Bit 5
+RDRU_RDRU6:         equ    6                                         ; Reduced Drive Port U Bit 6
+RDRU_RDRU7:         equ    7                                         ; Reduced Drive Port U Bit 7
+; bit position masks
+mRDRU_RDRU0:        equ    %00000001
+mRDRU_RDRU1:        equ    %00000010
+mRDRU_RDRU2:        equ    %00000100
+mRDRU_RDRU3:        equ    %00001000
+mRDRU_RDRU4:        equ    %00010000
+mRDRU_RDRU5:        equ    %00100000
+mRDRU_RDRU6:        equ    %01000000
+mRDRU_RDRU7:        equ    %10000000
+
+
+;*** PERU - Port U Pull Device Enable Register; 0x0000026C ***
+PERU:               equ    $0000026C                                ;*** PERU - Port U Pull Device Enable Register; 0x0000026C ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PERU_PERU0:         equ    0                                         ; Pull Device Enable Port U Bit 0
+PERU_PERU1:         equ    1                                         ; Pull Device Enable Port U Bit 1
+PERU_PERU2:         equ    2                                         ; Pull Device Enable Port U Bit 2
+PERU_PERU3:         equ    3                                         ; Pull Device Enable Port U Bit 3
+PERU_PERU4:         equ    4                                         ; Pull Device Enable Port U Bit 4
+PERU_PERU5:         equ    5                                         ; Pull Device Enable Port U Bit 5
+PERU_PERU6:         equ    6                                         ; Pull Device Enable Port U Bit 6
+PERU_PERU7:         equ    7                                         ; Pull Device Enable Port U Bit 7
+; bit position masks
+mPERU_PERU0:        equ    %00000001
+mPERU_PERU1:        equ    %00000010
+mPERU_PERU2:        equ    %00000100
+mPERU_PERU3:        equ    %00001000
+mPERU_PERU4:        equ    %00010000
+mPERU_PERU5:        equ    %00100000
+mPERU_PERU6:        equ    %01000000
+mPERU_PERU7:        equ    %10000000
+
+
+;*** PPSU - Port U Polarity Select Register; 0x0000026D ***
+PPSU:               equ    $0000026D                                ;*** PPSU - Port U Polarity Select Register; 0x0000026D ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PPSU_PPSU0:         equ    0                                         ; Pull Select Port U Bit 0
+PPSU_PPSU1:         equ    1                                         ; Pull Select Port U Bit 1
+PPSU_PPSU2:         equ    2                                         ; Pull Select Port U Bit 2
+PPSU_PPSU3:         equ    3                                         ; Pull Select Port U Bit 3
+PPSU_PPSU4:         equ    4                                         ; Pull Select Port U Bit 4
+PPSU_PPSU5:         equ    5                                         ; Pull Select Port U Bit 5
+PPSU_PPSU6:         equ    6                                         ; Pull Select Port U Bit 6
+PPSU_PPSU7:         equ    7                                         ; Pull Select Port U Bit 7
+; bit position masks
+mPPSU_PPSU0:        equ    %00000001
+mPPSU_PPSU1:        equ    %00000010
+mPPSU_PPSU2:        equ    %00000100
+mPPSU_PPSU3:        equ    %00001000
+mPPSU_PPSU4:        equ    %00010000
+mPPSU_PPSU5:        equ    %00100000
+mPPSU_PPSU6:        equ    %01000000
+mPPSU_PPSU7:        equ    %10000000
+
+
+;*** MODRR - Module Routing Register; 0x0000026E ***
+MODRR:              equ    $0000026E                                ;*** MODRR - Module Routing Register; 0x0000026E ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+MODRR_MODRR0:       equ    0                                         ; Module Routing Bit 0
+MODRR_MODRR1:       equ    1                                         ; Module Routing Bit 1
+MODRR_MODRR2:       equ    2                                         ; Module Routing Bit 2
+MODRR_MODRR3:       equ    3                                         ; Module Routing Bit 3
+; bit position masks
+mMODRR_MODRR0:      equ    %00000001
+mMODRR_MODRR1:      equ    %00000010
+mMODRR_MODRR2:      equ    %00000100
+mMODRR_MODRR3:      equ    %00001000
+
+
+;*** PTAD - Port AD I/O Register; 0x00000270 ***
+PTAD:               equ    $00000270                                ;*** PTAD - Port AD I/O Register; 0x00000270 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PTAD_PTAD0:         equ    0                                         ; Port AD Bit 0
+PTAD_PTAD1:         equ    1                                         ; Port AD Bit 1
+PTAD_PTAD2:         equ    2                                         ; Port AD Bit 2
+PTAD_PTAD3:         equ    3                                         ; Port AD Bit 3
+PTAD_PTAD4:         equ    4                                         ; Port AD Bit 4
+PTAD_PTAD5:         equ    5                                         ; Port AD Bit 5
+PTAD_PTAD6:         equ    6                                         ; Port AD Bit 6
+PTAD_PTAD7:         equ    7                                         ; Port AD Bit 7
+PTAD_PTAD8:         equ    8                                         ; Port AD Bit 8
+PTAD_PTAD9:         equ    9                                         ; Port AD Bit 9
+PTAD_PTAD10:        equ    10                                        ; Port AD Bit 10
+PTAD_PTAD11:        equ    11                                        ; Port AD Bit 11
+PTAD_PTAD12:        equ    12                                        ; Port AD Bit 12
+PTAD_PTAD13:        equ    13                                        ; Port AD Bit 13
+PTAD_PTAD14:        equ    14                                        ; Port AD Bit 14
+PTAD_PTAD15:        equ    15                                        ; Port AD Bit 15
+; bit position masks
+mPTAD_PTAD0:        equ    %00000001
+mPTAD_PTAD1:        equ    %00000010
+mPTAD_PTAD2:        equ    %00000100
+mPTAD_PTAD3:        equ    %00001000
+mPTAD_PTAD4:        equ    %00010000
+mPTAD_PTAD5:        equ    %00100000
+mPTAD_PTAD6:        equ    %01000000
+mPTAD_PTAD7:        equ    %10000000
+mPTAD_PTAD8:        equ    %100000000
+mPTAD_PTAD9:        equ    %1000000000
+mPTAD_PTAD10:       equ    %10000000000
+mPTAD_PTAD11:       equ    %100000000000
+mPTAD_PTAD12:       equ    %1000000000000
+mPTAD_PTAD13:       equ    %10000000000000
+mPTAD_PTAD14:       equ    %100000000000000
+mPTAD_PTAD15:       equ    %1000000000000000
+
+
+;*** PTADHi - Port AD I/O Register High; 0x00000270 ***
+PTADHi:             equ    $00000270                                ;*** PTADHi - Port AD I/O Register High; 0x00000270 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PTADHi_PTAD8:       equ    0                                         ; Port AD Bit 8
+PTADHi_PTAD9:       equ    1                                         ; Port AD Bit 9
+PTADHi_PTAD10:      equ    2                                         ; Port AD Bit 10
+PTADHi_PTAD11:      equ    3                                         ; Port AD Bit 11
+PTADHi_PTAD12:      equ    4                                         ; Port AD Bit 12
+PTADHi_PTAD13:      equ    5                                         ; Port AD Bit 13
+PTADHi_PTAD14:      equ    6                                         ; Port AD Bit 14
+PTADHi_PTAD15:      equ    7                                         ; Port AD Bit 15
+; bit position masks
+mPTADHi_PTAD8:      equ    %00000001
+mPTADHi_PTAD9:      equ    %00000010
+mPTADHi_PTAD10:     equ    %00000100
+mPTADHi_PTAD11:     equ    %00001000
+mPTADHi_PTAD12:     equ    %00010000
+mPTADHi_PTAD13:     equ    %00100000
+mPTADHi_PTAD14:     equ    %01000000
+mPTADHi_PTAD15:     equ    %10000000
+
+
+;*** PTADLo - Port AD I/O Register Low; 0x00000271 ***
+PTADLo:             equ    $00000271                                ;*** PTADLo - Port AD I/O Register Low; 0x00000271 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PTADLo_PTAD0:       equ    0                                         ; Port AD Bit 0
+PTADLo_PTAD1:       equ    1                                         ; Port AD Bit 1
+PTADLo_PTAD2:       equ    2                                         ; Port AD Bit 2
+PTADLo_PTAD3:       equ    3                                         ; Port AD Bit 3
+PTADLo_PTAD4:       equ    4                                         ; Port AD Bit 4
+PTADLo_PTAD5:       equ    5                                         ; Port AD Bit 5
+PTADLo_PTAD6:       equ    6                                         ; Port AD Bit 6
+PTADLo_PTAD7:       equ    7                                         ; Port AD Bit 7
+; bit position masks
+mPTADLo_PTAD0:      equ    %00000001
+mPTADLo_PTAD1:      equ    %00000010
+mPTADLo_PTAD2:      equ    %00000100
+mPTADLo_PTAD3:      equ    %00001000
+mPTADLo_PTAD4:      equ    %00010000
+mPTADLo_PTAD5:      equ    %00100000
+mPTADLo_PTAD6:      equ    %01000000
+mPTADLo_PTAD7:      equ    %10000000
+
+
+;*** PTIAD - Port AD Input Register; 0x00000272 ***
+PTIAD:              equ    $00000272                                ;*** PTIAD - Port AD Input Register; 0x00000272 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PTIAD_PTIAD0:       equ    0                                         ; Port AD Bit 0
+PTIAD_PTIAD1:       equ    1                                         ; Port AD Bit 1
+PTIAD_PTIAD2:       equ    2                                         ; Port AD Bit 2
+PTIAD_PTIAD3:       equ    3                                         ; Port AD Bit 3
+PTIAD_PTIAD4:       equ    4                                         ; Port AD Bit 4
+PTIAD_PTIAD5:       equ    5                                         ; Port AD Bit 5
+PTIAD_PTIAD6:       equ    6                                         ; Port AD Bit 6
+PTIAD_PTIAD7:       equ    7                                         ; Port AD Bit 7
+PTIAD_PTIAD8:       equ    8                                         ; Port AD Bit 8
+PTIAD_PTIAD9:       equ    9                                         ; Port AD Bit 9
+PTIAD_PTIAD10:      equ    10                                        ; Port AD Bit 10
+PTIAD_PTIAD11:      equ    11                                        ; Port AD Bit 11
+PTIAD_PTIAD12:      equ    12                                        ; Port AD Bit 12
+PTIAD_PTIAD13:      equ    13                                        ; Port AD Bit 13
+PTIAD_PTIAD14:      equ    14                                        ; Port AD Bit 14
+PTIAD_PTIAD15:      equ    15                                        ; Port AD Bit 15
+; bit position masks
+mPTIAD_PTIAD0:      equ    %00000001
+mPTIAD_PTIAD1:      equ    %00000010
+mPTIAD_PTIAD2:      equ    %00000100
+mPTIAD_PTIAD3:      equ    %00001000
+mPTIAD_PTIAD4:      equ    %00010000
+mPTIAD_PTIAD5:      equ    %00100000
+mPTIAD_PTIAD6:      equ    %01000000
+mPTIAD_PTIAD7:      equ    %10000000
+mPTIAD_PTIAD8:      equ    %100000000
+mPTIAD_PTIAD9:      equ    %1000000000
+mPTIAD_PTIAD10:     equ    %10000000000
+mPTIAD_PTIAD11:     equ    %100000000000
+mPTIAD_PTIAD12:     equ    %1000000000000
+mPTIAD_PTIAD13:     equ    %10000000000000
+mPTIAD_PTIAD14:     equ    %100000000000000
+mPTIAD_PTIAD15:     equ    %1000000000000000
+
+
+;*** PTIADHi - Port AD Input Register High; 0x00000272 ***
+PTIADHi:            equ    $00000272                                ;*** PTIADHi - Port AD Input Register High; 0x00000272 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PTIADHi_PTIAD8:     equ    0                                         ; Port AD Bit 8
+PTIADHi_PTIAD9:     equ    1                                         ; Port AD Bit 9
+PTIADHi_PTIAD10:    equ    2                                         ; Port AD Bit 10
+PTIADHi_PTIAD11:    equ    3                                         ; Port AD Bit 11
+PTIADHi_PTIAD12:    equ    4                                         ; Port AD Bit 12
+PTIADHi_PTIAD13:    equ    5                                         ; Port AD Bit 13
+PTIADHi_PTIAD14:    equ    6                                         ; Port AD Bit 14
+PTIADHi_PTIAD15:    equ    7                                         ; Port AD Bit 15
+; bit position masks
+mPTIADHi_PTIAD8:    equ    %00000001
+mPTIADHi_PTIAD9:    equ    %00000010
+mPTIADHi_PTIAD10:   equ    %00000100
+mPTIADHi_PTIAD11:   equ    %00001000
+mPTIADHi_PTIAD12:   equ    %00010000
+mPTIADHi_PTIAD13:   equ    %00100000
+mPTIADHi_PTIAD14:   equ    %01000000
+mPTIADHi_PTIAD15:   equ    %10000000
+
+
+;*** PTIADLo - Port AD Input Register Low; 0x00000273 ***
+PTIADLo:            equ    $00000273                                ;*** PTIADLo - Port AD Input Register Low; 0x00000273 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PTIADLo_PTIAD0:     equ    0                                         ; Port AD Bit 0
+PTIADLo_PTIAD1:     equ    1                                         ; Port AD Bit 1
+PTIADLo_PTIAD2:     equ    2                                         ; Port AD Bit 2
+PTIADLo_PTIAD3:     equ    3                                         ; Port AD Bit 3
+PTIADLo_PTIAD4:     equ    4                                         ; Port AD Bit 4
+PTIADLo_PTIAD5:     equ    5                                         ; Port AD Bit 5
+PTIADLo_PTIAD6:     equ    6                                         ; Port AD Bit 6
+PTIADLo_PTIAD7:     equ    7                                         ; Port AD Bit 7
+; bit position masks
+mPTIADLo_PTIAD0:    equ    %00000001
+mPTIADLo_PTIAD1:    equ    %00000010
+mPTIADLo_PTIAD2:    equ    %00000100
+mPTIADLo_PTIAD3:    equ    %00001000
+mPTIADLo_PTIAD4:    equ    %00010000
+mPTIADLo_PTIAD5:    equ    %00100000
+mPTIADLo_PTIAD6:    equ    %01000000
+mPTIADLo_PTIAD7:    equ    %10000000
+
+
+;*** DDRAD - Port AD Data Direction Register; 0x00000274 ***
+DDRAD:              equ    $00000274                                ;*** DDRAD - Port AD Data Direction Register; 0x00000274 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+DDRAD_DDRAD0:       equ    0                                         ; Port AD Data Direction Bit 0
+DDRAD_DDRAD1:       equ    1                                         ; Port AD Data Direction Bit 1
+DDRAD_DDRAD2:       equ    2                                         ; Port AD Data Direction Bit 2
+DDRAD_DDRAD3:       equ    3                                         ; Port AD Data Direction Bit 3
+DDRAD_DDRAD4:       equ    4                                         ; Port AD Data Direction Bit 4
+DDRAD_DDRAD5:       equ    5                                         ; Port AD Data Direction Bit 5
+DDRAD_DDRAD6:       equ    6                                         ; Port AD Data Direction Bit 6
+DDRAD_DDRAD7:       equ    7                                         ; Port AD Data Direction Bit 7
+DDRAD_DDRAD8:       equ    8                                         ; Port AD Data Direction Bit 8
+DDRAD_DDRAD9:       equ    9                                         ; Port AD Data Direction Bit 9
+DDRAD_DDRAD10:      equ    10                                        ; Port AD Data Direction Bit 10
+DDRAD_DDRAD11:      equ    11                                        ; Port AD Data Direction Bit 11
+DDRAD_DDRAD12:      equ    12                                        ; Port AD Data Direction Bit 12
+DDRAD_DDRAD13:      equ    13                                        ; Port AD Data Direction Bit 13
+DDRAD_DDRAD14:      equ    14                                        ; Port AD Data Direction Bit 14
+DDRAD_DDRAD15:      equ    15                                        ; Port AD Data Direction Bit 15
+; bit position masks
+mDDRAD_DDRAD0:      equ    %00000001
+mDDRAD_DDRAD1:      equ    %00000010
+mDDRAD_DDRAD2:      equ    %00000100
+mDDRAD_DDRAD3:      equ    %00001000
+mDDRAD_DDRAD4:      equ    %00010000
+mDDRAD_DDRAD5:      equ    %00100000
+mDDRAD_DDRAD6:      equ    %01000000
+mDDRAD_DDRAD7:      equ    %10000000
+mDDRAD_DDRAD8:      equ    %100000000
+mDDRAD_DDRAD9:      equ    %1000000000
+mDDRAD_DDRAD10:     equ    %10000000000
+mDDRAD_DDRAD11:     equ    %100000000000
+mDDRAD_DDRAD12:     equ    %1000000000000
+mDDRAD_DDRAD13:     equ    %10000000000000
+mDDRAD_DDRAD14:     equ    %100000000000000
+mDDRAD_DDRAD15:     equ    %1000000000000000
+
+
+;*** DDRADHi - Port AD Data Direction Register High; 0x00000274 ***
+DDRADHi:            equ    $00000274                                ;*** DDRADHi - Port AD Data Direction Register High; 0x00000274 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+DDRADHi_DDRAD8:     equ    0                                         ; Port AD Data Direction Bit 8
+DDRADHi_DDRAD9:     equ    1                                         ; Port AD Data Direction Bit 9
+DDRADHi_DDRAD10:    equ    2                                         ; Port AD Data Direction Bit 10
+DDRADHi_DDRAD11:    equ    3                                         ; Port AD Data Direction Bit 11
+DDRADHi_DDRAD12:    equ    4                                         ; Port AD Data Direction Bit 12
+DDRADHi_DDRAD13:    equ    5                                         ; Port AD Data Direction Bit 13
+DDRADHi_DDRAD14:    equ    6                                         ; Port AD Data Direction Bit 14
+DDRADHi_DDRAD15:    equ    7                                         ; Port AD Data Direction Bit 15
+; bit position masks
+mDDRADHi_DDRAD8:    equ    %00000001
+mDDRADHi_DDRAD9:    equ    %00000010
+mDDRADHi_DDRAD10:   equ    %00000100
+mDDRADHi_DDRAD11:   equ    %00001000
+mDDRADHi_DDRAD12:   equ    %00010000
+mDDRADHi_DDRAD13:   equ    %00100000
+mDDRADHi_DDRAD14:   equ    %01000000
+mDDRADHi_DDRAD15:   equ    %10000000
+
+
+;*** DDRADLo - Port AD Data Direction Register Low; 0x00000275 ***
+DDRADLo:            equ    $00000275                                ;*** DDRADLo - Port AD Data Direction Register Low; 0x00000275 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+DDRADLo_DDRAD0:     equ    0                                         ; Port AD Data Direction Bit 0
+DDRADLo_DDRAD1:     equ    1                                         ; Port AD Data Direction Bit 1
+DDRADLo_DDRAD2:     equ    2                                         ; Port AD Data Direction Bit 2
+DDRADLo_DDRAD3:     equ    3                                         ; Port AD Data Direction Bit 3
+DDRADLo_DDRAD4:     equ    4                                         ; Port AD Data Direction Bit 4
+DDRADLo_DDRAD5:     equ    5                                         ; Port AD Data Direction Bit 5
+DDRADLo_DDRAD6:     equ    6                                         ; Port AD Data Direction Bit 6
+DDRADLo_DDRAD7:     equ    7                                         ; Port AD Data Direction Bit 7
+; bit position masks
+mDDRADLo_DDRAD0:    equ    %00000001
+mDDRADLo_DDRAD1:    equ    %00000010
+mDDRADLo_DDRAD2:    equ    %00000100
+mDDRADLo_DDRAD3:    equ    %00001000
+mDDRADLo_DDRAD4:    equ    %00010000
+mDDRADLo_DDRAD5:    equ    %00100000
+mDDRADLo_DDRAD6:    equ    %01000000
+mDDRADLo_DDRAD7:    equ    %10000000
+
+
+;*** RDRAD - Port AD Reduced Drive Register; 0x00000276 ***
+RDRAD:              equ    $00000276                                ;*** RDRAD - Port AD Reduced Drive Register; 0x00000276 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+RDRAD_RDRAD0:       equ    0                                         ; Port AD Reduced Drive Bit 0
+RDRAD_RDRAD1:       equ    1                                         ; Port AD Reduced Drive Bit 1
+RDRAD_RDRAD2:       equ    2                                         ; Port AD Reduced Drive Bit 2
+RDRAD_RDRAD3:       equ    3                                         ; Port AD Reduced Drive Bit 3
+RDRAD_RDRAD4:       equ    4                                         ; Port AD Reduced Drive Bit 4
+RDRAD_RDRAD5:       equ    5                                         ; Port AD Reduced Drive Bit 5
+RDRAD_RDRAD6:       equ    6                                         ; Port AD Reduced Drive Bit 6
+RDRAD_RDRAD7:       equ    7                                         ; Port AD Reduced Drive Bit 7
+RDRAD_RDRAD8:       equ    8                                         ; Port AD Reduced Drive Bit 8
+RDRAD_RDRAD9:       equ    9                                         ; Port AD Reduced Drive Bit 9
+RDRAD_RDRAD10:      equ    10                                        ; Port AD Reduced Drive Bit 10
+RDRAD_RDRAD11:      equ    11                                        ; Port AD Reduced Drive Bit 11
+RDRAD_RDRAD12:      equ    12                                        ; Port AD Reduced Drive Bit 12
+RDRAD_RDRAD13:      equ    13                                        ; Port AD Reduced Drive Bit 13
+RDRAD_RDRAD14:      equ    14                                        ; Port AD Reduced Drive Bit 14
+RDRAD_RDRAD15:      equ    15                                        ; Port AD Reduced Drive Bit 15
+; bit position masks
+mRDRAD_RDRAD0:      equ    %00000001
+mRDRAD_RDRAD1:      equ    %00000010
+mRDRAD_RDRAD2:      equ    %00000100
+mRDRAD_RDRAD3:      equ    %00001000
+mRDRAD_RDRAD4:      equ    %00010000
+mRDRAD_RDRAD5:      equ    %00100000
+mRDRAD_RDRAD6:      equ    %01000000
+mRDRAD_RDRAD7:      equ    %10000000
+mRDRAD_RDRAD8:      equ    %100000000
+mRDRAD_RDRAD9:      equ    %1000000000
+mRDRAD_RDRAD10:     equ    %10000000000
+mRDRAD_RDRAD11:     equ    %100000000000
+mRDRAD_RDRAD12:     equ    %1000000000000
+mRDRAD_RDRAD13:     equ    %10000000000000
+mRDRAD_RDRAD14:     equ    %100000000000000
+mRDRAD_RDRAD15:     equ    %1000000000000000
+
+
+;*** RDRADHi - Port AD Reduced Drive Register High; 0x00000276 ***
+RDRADHi:            equ    $00000276                                ;*** RDRADHi - Port AD Reduced Drive Register High; 0x00000276 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+RDRADHi_RDRAD8:     equ    0                                         ; Port AD Reduced Drive Bit 8
+RDRADHi_RDRAD9:     equ    1                                         ; Port AD Reduced Drive Bit 9
+RDRADHi_RDRAD10:    equ    2                                         ; Port AD Reduced Drive Bit 10
+RDRADHi_RDRAD11:    equ    3                                         ; Port AD Reduced Drive Bit 11
+RDRADHi_RDRAD12:    equ    4                                         ; Port AD Reduced Drive Bit 12
+RDRADHi_RDRAD13:    equ    5                                         ; Port AD Reduced Drive Bit 13
+RDRADHi_RDRAD14:    equ    6                                         ; Port AD Reduced Drive Bit 14
+RDRADHi_RDRAD15:    equ    7                                         ; Port AD Reduced Drive Bit 15
+; bit position masks
+mRDRADHi_RDRAD8:    equ    %00000001
+mRDRADHi_RDRAD9:    equ    %00000010
+mRDRADHi_RDRAD10:   equ    %00000100
+mRDRADHi_RDRAD11:   equ    %00001000
+mRDRADHi_RDRAD12:   equ    %00010000
+mRDRADHi_RDRAD13:   equ    %00100000
+mRDRADHi_RDRAD14:   equ    %01000000
+mRDRADHi_RDRAD15:   equ    %10000000
+
+
+;*** RDRADLo - Port AD Reduced Drive Register Low; 0x00000277 ***
+RDRADLo:            equ    $00000277                                ;*** RDRADLo - Port AD Reduced Drive Register Low; 0x00000277 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+RDRADLo_RDRAD0:     equ    0                                         ; Port AD Reduced Drive Bit 0
+RDRADLo_RDRAD1:     equ    1                                         ; Port AD Reduced Drive Bit 1
+RDRADLo_RDRAD2:     equ    2                                         ; Port AD Reduced Drive Bit 2
+RDRADLo_RDRAD3:     equ    3                                         ; Port AD Reduced Drive Bit 3
+RDRADLo_RDRAD4:     equ    4                                         ; Port AD Reduced Drive Bit 4
+RDRADLo_RDRAD5:     equ    5                                         ; Port AD Reduced Drive Bit 5
+RDRADLo_RDRAD6:     equ    6                                         ; Port AD Reduced Drive Bit 6
+RDRADLo_RDRAD7:     equ    7                                         ; Port AD Reduced Drive Bit 7
+; bit position masks
+mRDRADLo_RDRAD0:    equ    %00000001
+mRDRADLo_RDRAD1:    equ    %00000010
+mRDRADLo_RDRAD2:    equ    %00000100
+mRDRADLo_RDRAD3:    equ    %00001000
+mRDRADLo_RDRAD4:    equ    %00010000
+mRDRADLo_RDRAD5:    equ    %00100000
+mRDRADLo_RDRAD6:    equ    %01000000
+mRDRADLo_RDRAD7:    equ    %10000000
+
+
+;*** PERAD - Port AD Pull Device Enable Register; 0x00000278 ***
+PERAD:              equ    $00000278                                ;*** PERAD - Port AD Pull Device Enable Register; 0x00000278 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PERAD_PERAD0:       equ    0                                         ; Port AD Pull Device Enable Bit 0
+PERAD_PERAD1:       equ    1                                         ; Port AD Pull Device Enable Bit 1
+PERAD_PERAD2:       equ    2                                         ; Port AD Pull Device Enable Bit 2
+PERAD_PERAD3:       equ    3                                         ; Port AD Pull Device Enable Bit 3
+PERAD_PERAD4:       equ    4                                         ; Port AD Pull Device Enable Bit 4
+PERAD_PERAD5:       equ    5                                         ; Port AD Pull Device Enable Bit 5
+PERAD_PERAD6:       equ    6                                         ; Port AD Pull Device Enable Bit 6
+PERAD_PERAD7:       equ    7                                         ; Port AD Pull Device Enable Bit 7
+PERAD_PERAD8:       equ    8                                         ; Port AD Pull Device Enable Bit 8
+PERAD_PERAD9:       equ    9                                         ; Port AD Pull Device Enable Bit 9
+PERAD_PERAD10:      equ    10                                        ; Port AD Pull Device Enable Bit 10
+PERAD_PERAD11:      equ    11                                        ; Port AD Pull Device Enable Bit 11
+PERAD_PERAD12:      equ    12                                        ; Port AD Pull Device Enable Bit 12
+PERAD_PERAD13:      equ    13                                        ; Port AD Pull Device Enable Bit 13
+PERAD_PERAD14:      equ    14                                        ; Port AD Pull Device Enable Bit 14
+PERAD_PERAD15:      equ    15                                        ; Port AD Pull Device Enable Bit 15
+; bit position masks
+mPERAD_PERAD0:      equ    %00000001
+mPERAD_PERAD1:      equ    %00000010
+mPERAD_PERAD2:      equ    %00000100
+mPERAD_PERAD3:      equ    %00001000
+mPERAD_PERAD4:      equ    %00010000
+mPERAD_PERAD5:      equ    %00100000
+mPERAD_PERAD6:      equ    %01000000
+mPERAD_PERAD7:      equ    %10000000
+mPERAD_PERAD8:      equ    %100000000
+mPERAD_PERAD9:      equ    %1000000000
+mPERAD_PERAD10:     equ    %10000000000
+mPERAD_PERAD11:     equ    %100000000000
+mPERAD_PERAD12:     equ    %1000000000000
+mPERAD_PERAD13:     equ    %10000000000000
+mPERAD_PERAD14:     equ    %100000000000000
+mPERAD_PERAD15:     equ    %1000000000000000
+
+
+;*** PERADHi - Port AD Pull Device Enable Register High; 0x00000278 ***
+PERADHi:            equ    $00000278                                ;*** PERADHi - Port AD Pull Device Enable Register High; 0x00000278 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PERADHi_PERAD8:     equ    0                                         ; Port AD Pull Device Enable Bit 8
+PERADHi_PERAD9:     equ    1                                         ; Port AD Pull Device Enable Bit 9
+PERADHi_PERAD10:    equ    2                                         ; Port AD Pull Device Enable Bit 10
+PERADHi_PERAD11:    equ    3                                         ; Port AD Pull Device Enable Bit 11
+PERADHi_PERAD12:    equ    4                                         ; Port AD Pull Device Enable Bit 12
+PERADHi_PERAD13:    equ    5                                         ; Port AD Pull Device Enable Bit 13
+PERADHi_PERAD14:    equ    6                                         ; Port AD Pull Device Enable Bit 14
+PERADHi_PERAD15:    equ    7                                         ; Port AD Pull Device Enable Bit 15
+; bit position masks
+mPERADHi_PERAD8:    equ    %00000001
+mPERADHi_PERAD9:    equ    %00000010
+mPERADHi_PERAD10:   equ    %00000100
+mPERADHi_PERAD11:   equ    %00001000
+mPERADHi_PERAD12:   equ    %00010000
+mPERADHi_PERAD13:   equ    %00100000
+mPERADHi_PERAD14:   equ    %01000000
+mPERADHi_PERAD15:   equ    %10000000
+
+
+;*** PERADLo - Port AD Pull Device Enable Register Low; 0x00000279 ***
+PERADLo:            equ    $00000279                                ;*** PERADLo - Port AD Pull Device Enable Register Low; 0x00000279 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PERADLo_PERAD0:     equ    0                                         ; Port AD Pull Device Enable Bit 0
+PERADLo_PERAD1:     equ    1                                         ; Port AD Pull Device Enable Bit 1
+PERADLo_PERAD2:     equ    2                                         ; Port AD Pull Device Enable Bit 2
+PERADLo_PERAD3:     equ    3                                         ; Port AD Pull Device Enable Bit 3
+PERADLo_PERAD4:     equ    4                                         ; Port AD Pull Device Enable Bit 4
+PERADLo_PERAD5:     equ    5                                         ; Port AD Pull Device Enable Bit 5
+PERADLo_PERAD6:     equ    6                                         ; Port AD Pull Device Enable Bit 6
+PERADLo_PERAD7:     equ    7                                         ; Port AD Pull Device Enable Bit 7
+; bit position masks
+mPERADLo_PERAD0:    equ    %00000001
+mPERADLo_PERAD1:    equ    %00000010
+mPERADLo_PERAD2:    equ    %00000100
+mPERADLo_PERAD3:    equ    %00001000
+mPERADLo_PERAD4:    equ    %00010000
+mPERADLo_PERAD5:    equ    %00100000
+mPERADLo_PERAD6:    equ    %01000000
+mPERADLo_PERAD7:    equ    %10000000
+
+
+;*** PPSAD - Port AD Polarity Select Register; 0x0000027A ***
+PPSAD:              equ    $0000027A                                ;*** PPSAD - Port AD Polarity Select Register; 0x0000027A ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PPSAD_PPSAD0:       equ    0                                         ; Port AD Polarity Select Bit 0
+PPSAD_PPSAD1:       equ    1                                         ; Port AD Polarity Select Bit 1
+PPSAD_PPSAD2:       equ    2                                         ; Port AD Polarity Select Bit 2
+PPSAD_PPSAD3:       equ    3                                         ; Port AD Polarity Select Bit 3
+PPSAD_PPSAD4:       equ    4                                         ; Port AD Polarity Select Bit 4
+PPSAD_PPSAD5:       equ    5                                         ; Port AD Polarity Select Bit 5
+PPSAD_PPSAD6:       equ    6                                         ; Port AD Polarity Select Bit 6
+PPSAD_PPSAD7:       equ    7                                         ; Port AD Polarity Select Bit 7
+PPSAD_PPSAD8:       equ    8                                         ; Port AD Polarity Select Bit 8
+PPSAD_PPSAD9:       equ    9                                         ; Port AD Polarity Select Bit 9
+PPSAD_PPSAD10:      equ    10                                        ; Port AD Polarity Select Bit 10
+PPSAD_PPSAD11:      equ    11                                        ; Port AD Polarity Select Bit 11
+PPSAD_PPSAD12:      equ    12                                        ; Port AD Polarity Select Bit 12
+PPSAD_PPSAD13:      equ    13                                        ; Port AD Polarity Select Bit 13
+PPSAD_PPSAD14:      equ    14                                        ; Port AD Polarity Select Bit 14
+PPSAD_PPSAD15:      equ    15                                        ; Port AD Polarity Select Bit 15
+; bit position masks
+mPPSAD_PPSAD0:      equ    %00000001
+mPPSAD_PPSAD1:      equ    %00000010
+mPPSAD_PPSAD2:      equ    %00000100
+mPPSAD_PPSAD3:      equ    %00001000
+mPPSAD_PPSAD4:      equ    %00010000
+mPPSAD_PPSAD5:      equ    %00100000
+mPPSAD_PPSAD6:      equ    %01000000
+mPPSAD_PPSAD7:      equ    %10000000
+mPPSAD_PPSAD8:      equ    %100000000
+mPPSAD_PPSAD9:      equ    %1000000000
+mPPSAD_PPSAD10:     equ    %10000000000
+mPPSAD_PPSAD11:     equ    %100000000000
+mPPSAD_PPSAD12:     equ    %1000000000000
+mPPSAD_PPSAD13:     equ    %10000000000000
+mPPSAD_PPSAD14:     equ    %100000000000000
+mPPSAD_PPSAD15:     equ    %1000000000000000
+
+
+;*** PPSADHi - Port AD Polarity Select Register High; 0x0000027A ***
+PPSADHi:            equ    $0000027A                                ;*** PPSADHi - Port AD Polarity Select Register High; 0x0000027A ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PPSADHi_PPSAD8:     equ    0                                         ; Port AD Polarity Select Bit 8
+PPSADHi_PPSAD9:     equ    1                                         ; Port AD Polarity Select Bit 9
+PPSADHi_PPSAD10:    equ    2                                         ; Port AD Polarity Select Bit 10
+PPSADHi_PPSAD11:    equ    3                                         ; Port AD Polarity Select Bit 11
+PPSADHi_PPSAD12:    equ    4                                         ; Port AD Polarity Select Bit 12
+PPSADHi_PPSAD13:    equ    5                                         ; Port AD Polarity Select Bit 13
+PPSADHi_PPSAD14:    equ    6                                         ; Port AD Polarity Select Bit 14
+PPSADHi_PPSAD15:    equ    7                                         ; Port AD Polarity Select Bit 15
+; bit position masks
+mPPSADHi_PPSAD8:    equ    %00000001
+mPPSADHi_PPSAD9:    equ    %00000010
+mPPSADHi_PPSAD10:   equ    %00000100
+mPPSADHi_PPSAD11:   equ    %00001000
+mPPSADHi_PPSAD12:   equ    %00010000
+mPPSADHi_PPSAD13:   equ    %00100000
+mPPSADHi_PPSAD14:   equ    %01000000
+mPPSADHi_PPSAD15:   equ    %10000000
+
+
+;*** PPSADLo - Port AD Polarity Select Register Low; 0x0000027B ***
+PPSADLo:            equ    $0000027B                                ;*** PPSADLo - Port AD Polarity Select Register Low; 0x0000027B ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PPSADLo_PPSAD0:     equ    0                                         ; Port AD Polarity Select Bit 0
+PPSADLo_PPSAD1:     equ    1                                         ; Port AD Polarity Select Bit 1
+PPSADLo_PPSAD2:     equ    2                                         ; Port AD Polarity Select Bit 2
+PPSADLo_PPSAD3:     equ    3                                         ; Port AD Polarity Select Bit 3
+PPSADLo_PPSAD4:     equ    4                                         ; Port AD Polarity Select Bit 4
+PPSADLo_PPSAD5:     equ    5                                         ; Port AD Polarity Select Bit 5
+PPSADLo_PPSAD6:     equ    6                                         ; Port AD Polarity Select Bit 6
+PPSADLo_PPSAD7:     equ    7                                         ; Port AD Polarity Select Bit 7
+; bit position masks
+mPPSADLo_PPSAD0:    equ    %00000001
+mPPSADLo_PPSAD1:    equ    %00000010
+mPPSADLo_PPSAD2:    equ    %00000100
+mPPSADLo_PPSAD3:    equ    %00001000
+mPPSADLo_PPSAD4:    equ    %00010000
+mPPSADLo_PPSAD5:    equ    %00100000
+mPPSADLo_PPSAD6:    equ    %01000000
+mPPSADLo_PPSAD7:    equ    %10000000
+
+
+;*** PIEAD - Port AD Interrupt Enable Register; 0x0000027C ***
+PIEAD:              equ    $0000027C                                ;*** PIEAD - Port AD Interrupt Enable Register; 0x0000027C ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PIEAD_PIEAD0:       equ    0                                         ; Port AD Interrupt Enable Bit 0
+PIEAD_PIEAD1:       equ    1                                         ; Port AD Interrupt Enable Bit 1
+PIEAD_PIEAD2:       equ    2                                         ; Port AD Interrupt Enable Bit 2
+PIEAD_PIEAD3:       equ    3                                         ; Port AD Interrupt Enable Bit 3
+PIEAD_PIEAD4:       equ    4                                         ; Port AD Interrupt Enable Bit 4
+PIEAD_PIEAD5:       equ    5                                         ; Port AD Interrupt Enable Bit 5
+PIEAD_PIEAD6:       equ    6                                         ; Port AD Interrupt Enable Bit 6
+PIEAD_PIEAD7:       equ    7                                         ; Port AD Interrupt Enable Bit 7
+PIEAD_PIEAD8:       equ    8                                         ; Port AD Interrupt Enable Bit 8
+PIEAD_PIEAD9:       equ    9                                         ; Port AD Interrupt Enable Bit 9
+PIEAD_PIEAD10:      equ    10                                        ; Port AD Interrupt Enable Bit 10
+PIEAD_PIEAD11:      equ    11                                        ; Port AD Interrupt Enable Bit 11
+PIEAD_PIEAD12:      equ    12                                        ; Port AD Interrupt Enable Bit 12
+PIEAD_PIEAD13:      equ    13                                        ; Port AD Interrupt Enable Bit 13
+PIEAD_PIEAD14:      equ    14                                        ; Port AD Interrupt Enable Bit 14
+PIEAD_PIEAD15:      equ    15                                        ; Port AD Interrupt Enable Bit 15
+; bit position masks
+mPIEAD_PIEAD0:      equ    %00000001
+mPIEAD_PIEAD1:      equ    %00000010
+mPIEAD_PIEAD2:      equ    %00000100
+mPIEAD_PIEAD3:      equ    %00001000
+mPIEAD_PIEAD4:      equ    %00010000
+mPIEAD_PIEAD5:      equ    %00100000
+mPIEAD_PIEAD6:      equ    %01000000
+mPIEAD_PIEAD7:      equ    %10000000
+mPIEAD_PIEAD8:      equ    %100000000
+mPIEAD_PIEAD9:      equ    %1000000000
+mPIEAD_PIEAD10:     equ    %10000000000
+mPIEAD_PIEAD11:     equ    %100000000000
+mPIEAD_PIEAD12:     equ    %1000000000000
+mPIEAD_PIEAD13:     equ    %10000000000000
+mPIEAD_PIEAD14:     equ    %100000000000000
+mPIEAD_PIEAD15:     equ    %1000000000000000
+
+
+;*** PIEADHi - Port AD Interrupt Enable Register High; 0x0000027C ***
+PIEADHi:            equ    $0000027C                                ;*** PIEADHi - Port AD Interrupt Enable Register High; 0x0000027C ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PIEADHi_PIEAD8:     equ    0                                         ; Port AD Interrupt Enable Bit 8
+PIEADHi_PIEAD9:     equ    1                                         ; Port AD Interrupt Enable Bit 9
+PIEADHi_PIEAD10:    equ    2                                         ; Port AD Interrupt Enable Bit 10
+PIEADHi_PIEAD11:    equ    3                                         ; Port AD Interrupt Enable Bit 11
+PIEADHi_PIEAD12:    equ    4                                         ; Port AD Interrupt Enable Bit 12
+PIEADHi_PIEAD13:    equ    5                                         ; Port AD Interrupt Enable Bit 13
+PIEADHi_PIEAD14:    equ    6                                         ; Port AD Interrupt Enable Bit 14
+PIEADHi_PIEAD15:    equ    7                                         ; Port AD Interrupt Enable Bit 15
+; bit position masks
+mPIEADHi_PIEAD8:    equ    %00000001
+mPIEADHi_PIEAD9:    equ    %00000010
+mPIEADHi_PIEAD10:   equ    %00000100
+mPIEADHi_PIEAD11:   equ    %00001000
+mPIEADHi_PIEAD12:   equ    %00010000
+mPIEADHi_PIEAD13:   equ    %00100000
+mPIEADHi_PIEAD14:   equ    %01000000
+mPIEADHi_PIEAD15:   equ    %10000000
+
+
+;*** PIEADLo - Port AD Interrupt Enable Register Low; 0x0000027D ***
+PIEADLo:            equ    $0000027D                                ;*** PIEADLo - Port AD Interrupt Enable Register Low; 0x0000027D ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PIEADLo_PIEAD0:     equ    0                                         ; Port AD Interrupt Enable Bit 0
+PIEADLo_PIEAD1:     equ    1                                         ; Port AD Interrupt Enable Bit 1
+PIEADLo_PIEAD2:     equ    2                                         ; Port AD Interrupt Enable Bit 2
+PIEADLo_PIEAD3:     equ    3                                         ; Port AD Interrupt Enable Bit 3
+PIEADLo_PIEAD4:     equ    4                                         ; Port AD Interrupt Enable Bit 4
+PIEADLo_PIEAD5:     equ    5                                         ; Port AD Interrupt Enable Bit 5
+PIEADLo_PIEAD6:     equ    6                                         ; Port AD Interrupt Enable Bit 6
+PIEADLo_PIEAD7:     equ    7                                         ; Port AD Interrupt Enable Bit 7
+; bit position masks
+mPIEADLo_PIEAD0:    equ    %00000001
+mPIEADLo_PIEAD1:    equ    %00000010
+mPIEADLo_PIEAD2:    equ    %00000100
+mPIEADLo_PIEAD3:    equ    %00001000
+mPIEADLo_PIEAD4:    equ    %00010000
+mPIEADLo_PIEAD5:    equ    %00100000
+mPIEADLo_PIEAD6:    equ    %01000000
+mPIEADLo_PIEAD7:    equ    %10000000
+
+
+;*** PIFAD - Port AD Interrupt Flag Register; 0x0000027E ***
+PIFAD:              equ    $0000027E                                ;*** PIFAD - Port AD Interrupt Flag Register; 0x0000027E ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PIFAD_PIFAD0:       equ    0                                         ; Port AD Interrupt Flag Bit 0
+PIFAD_PIFAD1:       equ    1                                         ; Port AD Interrupt Flag Bit 1
+PIFAD_PIFAD2:       equ    2                                         ; Port AD Interrupt Flag Bit 2
+PIFAD_PIFAD3:       equ    3                                         ; Port AD Interrupt Flag Bit 3
+PIFAD_PIFAD4:       equ    4                                         ; Port AD Interrupt Flag Bit 4
+PIFAD_PIFAD5:       equ    5                                         ; Port AD Interrupt Flag Bit 5
+PIFAD_PIFAD6:       equ    6                                         ; Port AD Interrupt Flag Bit 6
+PIFAD_PIFAD7:       equ    7                                         ; Port AD Interrupt Flag Bit 7
+PIFAD_PIFAD8:       equ    8                                         ; Port AD Interrupt Flag Bit 8
+PIFAD_PIFAD9:       equ    9                                         ; Port AD Interrupt Flag Bit 9
+PIFAD_PIFAD10:      equ    10                                        ; Port AD Interrupt Flag Bit 10
+PIFAD_PIFAD11:      equ    11                                        ; Port AD Interrupt Flag Bit 11
+PIFAD_PIFAD12:      equ    12                                        ; Port AD Interrupt Flag Bit 12
+PIFAD_PIFAD13:      equ    13                                        ; Port AD Interrupt Flag Bit 13
+PIFAD_PIFAD14:      equ    14                                        ; Port AD Interrupt Flag Bit 14
+PIFAD_PIFAD15:      equ    15                                        ; Port AD Interrupt Flag Bit 15
+; bit position masks
+mPIFAD_PIFAD0:      equ    %00000001
+mPIFAD_PIFAD1:      equ    %00000010
+mPIFAD_PIFAD2:      equ    %00000100
+mPIFAD_PIFAD3:      equ    %00001000
+mPIFAD_PIFAD4:      equ    %00010000
+mPIFAD_PIFAD5:      equ    %00100000
+mPIFAD_PIFAD6:      equ    %01000000
+mPIFAD_PIFAD7:      equ    %10000000
+mPIFAD_PIFAD8:      equ    %100000000
+mPIFAD_PIFAD9:      equ    %1000000000
+mPIFAD_PIFAD10:     equ    %10000000000
+mPIFAD_PIFAD11:     equ    %100000000000
+mPIFAD_PIFAD12:     equ    %1000000000000
+mPIFAD_PIFAD13:     equ    %10000000000000
+mPIFAD_PIFAD14:     equ    %100000000000000
+mPIFAD_PIFAD15:     equ    %1000000000000000
+
+
+;*** PIFADHi - Port AD Interrupt Flag Register High; 0x0000027E ***
+PIFADHi:            equ    $0000027E                                ;*** PIFADHi - Port AD Interrupt Flag Register High; 0x0000027E ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PIFADHi_PIFAD8:     equ    0                                         ; Port AD Interrupt Flag Bit 8
+PIFADHi_PIFAD9:     equ    1                                         ; Port AD Interrupt Flag Bit 9
+PIFADHi_PIFAD10:    equ    2                                         ; Port AD Interrupt Flag Bit 10
+PIFADHi_PIFAD11:    equ    3                                         ; Port AD Interrupt Flag Bit 11
+PIFADHi_PIFAD12:    equ    4                                         ; Port AD Interrupt Flag Bit 12
+PIFADHi_PIFAD13:    equ    5                                         ; Port AD Interrupt Flag Bit 13
+PIFADHi_PIFAD14:    equ    6                                         ; Port AD Interrupt Flag Bit 14
+PIFADHi_PIFAD15:    equ    7                                         ; Port AD Interrupt Flag Bit 15
+; bit position masks
+mPIFADHi_PIFAD8:    equ    %00000001
+mPIFADHi_PIFAD9:    equ    %00000010
+mPIFADHi_PIFAD10:   equ    %00000100
+mPIFADHi_PIFAD11:   equ    %00001000
+mPIFADHi_PIFAD12:   equ    %00010000
+mPIFADHi_PIFAD13:   equ    %00100000
+mPIFADHi_PIFAD14:   equ    %01000000
+mPIFADHi_PIFAD15:   equ    %10000000
+
+
+;*** PIFADLo - Port AD Interrupt Flag Register Low; 0x0000027F ***
+PIFADLo:            equ    $0000027F                                ;*** PIFADLo - Port AD Interrupt Flag Register Low; 0x0000027F ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+PIFADLo_PIFAD0:     equ    0                                         ; Port AD Interrupt Flag Bit 0
+PIFADLo_PIFAD1:     equ    1                                         ; Port AD Interrupt Flag Bit 1
+PIFADLo_PIFAD2:     equ    2                                         ; Port AD Interrupt Flag Bit 2
+PIFADLo_PIFAD3:     equ    3                                         ; Port AD Interrupt Flag Bit 3
+PIFADLo_PIFAD4:     equ    4                                         ; Port AD Interrupt Flag Bit 4
+PIFADLo_PIFAD5:     equ    5                                         ; Port AD Interrupt Flag Bit 5
+PIFADLo_PIFAD6:     equ    6                                         ; Port AD Interrupt Flag Bit 6
+PIFADLo_PIFAD7:     equ    7                                         ; Port AD Interrupt Flag Bit 7
+; bit position masks
+mPIFADLo_PIFAD0:    equ    %00000001
+mPIFADLo_PIFAD1:    equ    %00000010
+mPIFADLo_PIFAD2:    equ    %00000100
+mPIFADLo_PIFAD3:    equ    %00001000
+mPIFADLo_PIFAD4:    equ    %00010000
+mPIFADLo_PIFAD5:    equ    %00100000
+mPIFADLo_PIFAD6:    equ    %01000000
+mPIFADLo_PIFAD7:    equ    %10000000
+
+
+;*** BAKEY0 - Backdoor Access Key 0; 0x0000FF00 ***
+BAKEY0:             equ    $0000FF00                                ;*** BAKEY0 - Backdoor Access Key 0; 0x0000FF00 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+BAKEY0_KEY0:        equ    0                                         ; Backdoor Access Key bits, bit 0
+BAKEY0_KEY1:        equ    1                                         ; Backdoor Access Key bits, bit 1
+BAKEY0_KEY2:        equ    2                                         ; Backdoor Access Key bits, bit 2
+BAKEY0_KEY3:        equ    3                                         ; Backdoor Access Key bits, bit 3
+BAKEY0_KEY4:        equ    4                                         ; Backdoor Access Key bits, bit 4
+BAKEY0_KEY5:        equ    5                                         ; Backdoor Access Key bits, bit 5
+BAKEY0_KEY6:        equ    6                                         ; Backdoor Access Key bits, bit 6
+BAKEY0_KEY7:        equ    7                                         ; Backdoor Access Key bits, bit 7
+BAKEY0_KEY8:        equ    8                                         ; Backdoor Access Key bits, bit 8
+BAKEY0_KEY9:        equ    9                                         ; Backdoor Access Key bits, bit 9
+BAKEY0_KEY10:       equ    10                                        ; Backdoor Access Key bits, bit 10
+BAKEY0_KEY11:       equ    11                                        ; Backdoor Access Key bits, bit 11
+BAKEY0_KEY12:       equ    12                                        ; Backdoor Access Key bits, bit 12
+BAKEY0_KEY13:       equ    13                                        ; Backdoor Access Key bits, bit 13
+BAKEY0_KEY14:       equ    14                                        ; Backdoor Access Key bits, bit 14
+BAKEY0_KEY15:       equ    15                                        ; Backdoor Access Key bits, bit 15
+; bit position masks
+mBAKEY0_KEY0:       equ    %00000001
+mBAKEY0_KEY1:       equ    %00000010
+mBAKEY0_KEY2:       equ    %00000100
+mBAKEY0_KEY3:       equ    %00001000
+mBAKEY0_KEY4:       equ    %00010000
+mBAKEY0_KEY5:       equ    %00100000
+mBAKEY0_KEY6:       equ    %01000000
+mBAKEY0_KEY7:       equ    %10000000
+mBAKEY0_KEY8:       equ    %100000000
+mBAKEY0_KEY9:       equ    %1000000000
+mBAKEY0_KEY10:      equ    %10000000000
+mBAKEY0_KEY11:      equ    %100000000000
+mBAKEY0_KEY12:      equ    %1000000000000
+mBAKEY0_KEY13:      equ    %10000000000000
+mBAKEY0_KEY14:      equ    %100000000000000
+mBAKEY0_KEY15:      equ    %1000000000000000
+
+
+;*** BAKEY1 - Backdoor Access Key 1; 0x0000FF02 ***
+BAKEY1:             equ    $0000FF02                                ;*** BAKEY1 - Backdoor Access Key 1; 0x0000FF02 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+BAKEY1_KEY0:        equ    0                                         ; Backdoor Access Key bits, bit 0
+BAKEY1_KEY1:        equ    1                                         ; Backdoor Access Key bits, bit 1
+BAKEY1_KEY2:        equ    2                                         ; Backdoor Access Key bits, bit 2
+BAKEY1_KEY3:        equ    3                                         ; Backdoor Access Key bits, bit 3
+BAKEY1_KEY4:        equ    4                                         ; Backdoor Access Key bits, bit 4
+BAKEY1_KEY5:        equ    5                                         ; Backdoor Access Key bits, bit 5
+BAKEY1_KEY6:        equ    6                                         ; Backdoor Access Key bits, bit 6
+BAKEY1_KEY7:        equ    7                                         ; Backdoor Access Key bits, bit 7
+BAKEY1_KEY8:        equ    8                                         ; Backdoor Access Key bits, bit 8
+BAKEY1_KEY9:        equ    9                                         ; Backdoor Access Key bits, bit 9
+BAKEY1_KEY10:       equ    10                                        ; Backdoor Access Key bits, bit 10
+BAKEY1_KEY11:       equ    11                                        ; Backdoor Access Key bits, bit 11
+BAKEY1_KEY12:       equ    12                                        ; Backdoor Access Key bits, bit 12
+BAKEY1_KEY13:       equ    13                                        ; Backdoor Access Key bits, bit 13
+BAKEY1_KEY14:       equ    14                                        ; Backdoor Access Key bits, bit 14
+BAKEY1_KEY15:       equ    15                                        ; Backdoor Access Key bits, bit 15
+; bit position masks
+mBAKEY1_KEY0:       equ    %00000001
+mBAKEY1_KEY1:       equ    %00000010
+mBAKEY1_KEY2:       equ    %00000100
+mBAKEY1_KEY3:       equ    %00001000
+mBAKEY1_KEY4:       equ    %00010000
+mBAKEY1_KEY5:       equ    %00100000
+mBAKEY1_KEY6:       equ    %01000000
+mBAKEY1_KEY7:       equ    %10000000
+mBAKEY1_KEY8:       equ    %100000000
+mBAKEY1_KEY9:       equ    %1000000000
+mBAKEY1_KEY10:      equ    %10000000000
+mBAKEY1_KEY11:      equ    %100000000000
+mBAKEY1_KEY12:      equ    %1000000000000
+mBAKEY1_KEY13:      equ    %10000000000000
+mBAKEY1_KEY14:      equ    %100000000000000
+mBAKEY1_KEY15:      equ    %1000000000000000
+
+
+;*** BAKEY2 - Backdoor Access Key 2; 0x0000FF04 ***
+BAKEY2:             equ    $0000FF04                                ;*** BAKEY2 - Backdoor Access Key 2; 0x0000FF04 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+BAKEY2_KEY0:        equ    0                                         ; Backdoor Access Key bits, bit 0
+BAKEY2_KEY1:        equ    1                                         ; Backdoor Access Key bits, bit 1
+BAKEY2_KEY2:        equ    2                                         ; Backdoor Access Key bits, bit 2
+BAKEY2_KEY3:        equ    3                                         ; Backdoor Access Key bits, bit 3
+BAKEY2_KEY4:        equ    4                                         ; Backdoor Access Key bits, bit 4
+BAKEY2_KEY5:        equ    5                                         ; Backdoor Access Key bits, bit 5
+BAKEY2_KEY6:        equ    6                                         ; Backdoor Access Key bits, bit 6
+BAKEY2_KEY7:        equ    7                                         ; Backdoor Access Key bits, bit 7
+BAKEY2_KEY8:        equ    8                                         ; Backdoor Access Key bits, bit 8
+BAKEY2_KEY9:        equ    9                                         ; Backdoor Access Key bits, bit 9
+BAKEY2_KEY10:       equ    10                                        ; Backdoor Access Key bits, bit 10
+BAKEY2_KEY11:       equ    11                                        ; Backdoor Access Key bits, bit 11
+BAKEY2_KEY12:       equ    12                                        ; Backdoor Access Key bits, bit 12
+BAKEY2_KEY13:       equ    13                                        ; Backdoor Access Key bits, bit 13
+BAKEY2_KEY14:       equ    14                                        ; Backdoor Access Key bits, bit 14
+BAKEY2_KEY15:       equ    15                                        ; Backdoor Access Key bits, bit 15
+; bit position masks
+mBAKEY2_KEY0:       equ    %00000001
+mBAKEY2_KEY1:       equ    %00000010
+mBAKEY2_KEY2:       equ    %00000100
+mBAKEY2_KEY3:       equ    %00001000
+mBAKEY2_KEY4:       equ    %00010000
+mBAKEY2_KEY5:       equ    %00100000
+mBAKEY2_KEY6:       equ    %01000000
+mBAKEY2_KEY7:       equ    %10000000
+mBAKEY2_KEY8:       equ    %100000000
+mBAKEY2_KEY9:       equ    %1000000000
+mBAKEY2_KEY10:      equ    %10000000000
+mBAKEY2_KEY11:      equ    %100000000000
+mBAKEY2_KEY12:      equ    %1000000000000
+mBAKEY2_KEY13:      equ    %10000000000000
+mBAKEY2_KEY14:      equ    %100000000000000
+mBAKEY2_KEY15:      equ    %1000000000000000
+
+
+;*** BAKEY3 - Backdoor Access Key 3; 0x0000FF06 ***
+BAKEY3:             equ    $0000FF06                                ;*** BAKEY3 - Backdoor Access Key 3; 0x0000FF06 ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+BAKEY3_KEY0:        equ    0                                         ; Backdoor Access Key bits, bit 0
+BAKEY3_KEY1:        equ    1                                         ; Backdoor Access Key bits, bit 1
+BAKEY3_KEY2:        equ    2                                         ; Backdoor Access Key bits, bit 2
+BAKEY3_KEY3:        equ    3                                         ; Backdoor Access Key bits, bit 3
+BAKEY3_KEY4:        equ    4                                         ; Backdoor Access Key bits, bit 4
+BAKEY3_KEY5:        equ    5                                         ; Backdoor Access Key bits, bit 5
+BAKEY3_KEY6:        equ    6                                         ; Backdoor Access Key bits, bit 6
+BAKEY3_KEY7:        equ    7                                         ; Backdoor Access Key bits, bit 7
+BAKEY3_KEY8:        equ    8                                         ; Backdoor Access Key bits, bit 8
+BAKEY3_KEY9:        equ    9                                         ; Backdoor Access Key bits, bit 9
+BAKEY3_KEY10:       equ    10                                        ; Backdoor Access Key bits, bit 10
+BAKEY3_KEY11:       equ    11                                        ; Backdoor Access Key bits, bit 11
+BAKEY3_KEY12:       equ    12                                        ; Backdoor Access Key bits, bit 12
+BAKEY3_KEY13:       equ    13                                        ; Backdoor Access Key bits, bit 13
+BAKEY3_KEY14:       equ    14                                        ; Backdoor Access Key bits, bit 14
+BAKEY3_KEY15:       equ    15                                        ; Backdoor Access Key bits, bit 15
+; bit position masks
+mBAKEY3_KEY0:       equ    %00000001
+mBAKEY3_KEY1:       equ    %00000010
+mBAKEY3_KEY2:       equ    %00000100
+mBAKEY3_KEY3:       equ    %00001000
+mBAKEY3_KEY4:       equ    %00010000
+mBAKEY3_KEY5:       equ    %00100000
+mBAKEY3_KEY6:       equ    %01000000
+mBAKEY3_KEY7:       equ    %10000000
+mBAKEY3_KEY8:       equ    %100000000
+mBAKEY3_KEY9:       equ    %1000000000
+mBAKEY3_KEY10:      equ    %10000000000
+mBAKEY3_KEY11:      equ    %100000000000
+mBAKEY3_KEY12:      equ    %1000000000000
+mBAKEY3_KEY13:      equ    %10000000000000
+mBAKEY3_KEY14:      equ    %100000000000000
+mBAKEY3_KEY15:      equ    %1000000000000000
+
+
+;*** NVFPROT0 - Non volatile Block 0 Flash Protection Register; 0x0000FF0D ***
+NVFPROT0:           equ    $0000FF0D                                ;*** NVFPROT0 - Non volatile Block 0 Flash Protection Register; 0x0000FF0D ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+NVFPROT0_FPLS0:     equ    0                                         ; Flash Protection Lower Address size 0
+NVFPROT0_FPLS1:     equ    1                                         ; Flash Protection Lower Address size 1
+NVFPROT0_FPLDIS:    equ    2                                         ; Flash Protection Lower address range disable
+NVFPROT0_FPHS0:     equ    3                                         ; Flash Protection Higher address size 0
+NVFPROT0_FPHS1:     equ    4                                         ; Flash Protection Higher address size 1
+NVFPROT0_FPHDIS:    equ    5                                         ; Flash Protection Higher address range disable
+NVFPROT0_NV6:       equ    6                                         ; Non Volatile Flag Bit
+NVFPROT0_FPOPEN:    equ    7                                         ; Opens the flash block or subsections of it for program or erase
+; bit position masks
+mNVFPROT0_FPLS0:    equ    %00000001
+mNVFPROT0_FPLS1:    equ    %00000010
+mNVFPROT0_FPLDIS:   equ    %00000100
+mNVFPROT0_FPHS0:    equ    %00001000
+mNVFPROT0_FPHS1:    equ    %00010000
+mNVFPROT0_FPHDIS:   equ    %00100000
+mNVFPROT0_NV6:      equ    %01000000
+mNVFPROT0_FPOPEN:   equ    %10000000
+
+
+;*** NVFSEC - Non volatile Flash Security Register; 0x0000FF0F ***
+NVFSEC:             equ    $0000FF0F                                ;*** NVFSEC - Non volatile Flash Security Register; 0x0000FF0F ***
+; bit numbers for usage in BCLR, BSET, BRCLR and BRSET
+NVFSEC_SEC0:        equ    0                                         ; Memory security bit 0
+NVFSEC_SEC1:        equ    1                                         ; Memory security bit 1
+NVFSEC_NV2:         equ    2                                         ; Non Volatile flag bit 2
+NVFSEC_NV3:         equ    3                                         ; Non Volatile flag bit 3
+NVFSEC_NV4:         equ    4                                         ; Non Volatile flag bit 4
+NVFSEC_NV5:         equ    5                                         ; Non Volatile flag bit 5
+NVFSEC_NV6:         equ    6                                         ; Non Volatile flag bit 6
+NVFSEC_KEYEN:       equ    7                                         ; Backdoor Key Security Enable
+; bit position masks
+mNVFSEC_SEC0:       equ    %00000001
+mNVFSEC_SEC1:       equ    %00000010
+mNVFSEC_NV2:        equ    %00000100
+mNVFSEC_NV3:        equ    %00001000
+mNVFSEC_NV4:        equ    %00010000
+mNVFSEC_NV5:        equ    %00100000
+mNVFSEC_NV6:        equ    %01000000
+mNVFSEC_KEYEN:      equ    %10000000
+
+
+
+;***********************************************
+;**   D E P R E C I A T E D   S Y M B O L S   **
+;***********************************************
+        IFNDEF  __GENERATE_APPLICATION__                            ; not supported for absolute assembler
+                    XREF    This_symb_has_been_depreciated
+        ENDIF
+; ---------------------------------------------------------------------------
+; The following symbols were removed, because they were invalid or irrelevant
+; ---------------------------------------------------------------------------
+;
+; Follows changes from the database 2.87.489 version
+VportAD                                  EQU        Vportad
+;
+; Follows changes from the database 2.87.501 version
+        IFNDEF __GENERATE_APPLICATION__
+mPMFVAL0_PMFVAL00                        EQU        This_symb_has_been_depreciated
+mPMFVAL0_PMFVAL01                        EQU        This_symb_has_been_depreciated
+mPMFVAL0_PMFVAL02                        EQU        This_symb_has_been_depreciated
+mPMFVAL0_PMFVAL03                        EQU        This_symb_has_been_depreciated
+mPMFVAL0_PMFVAL04                        EQU        This_symb_has_been_depreciated
+mPMFVAL0_PMFVAL05                        EQU        This_symb_has_been_depreciated
+mPMFVAL0_PMFVAL06                        EQU        This_symb_has_been_depreciated
+mPMFVAL0_PMFVAL07                        EQU        This_symb_has_been_depreciated
+mPMFVAL0_PMFVAL08                        EQU        This_symb_has_been_depreciated
+mPMFVAL0_PMFVAL09                        EQU        This_symb_has_been_depreciated
+mPMFVAL0_PMFVAL010                       EQU        This_symb_has_been_depreciated
+mPMFVAL0_PMFVAL011                       EQU        This_symb_has_been_depreciated
+mPMFVAL0_PMFVAL012                       EQU        This_symb_has_been_depreciated
+mPMFVAL0_PMFVAL013                       EQU        This_symb_has_been_depreciated
+mPMFVAL0_PMFVAL014                       EQU        This_symb_has_been_depreciated
+        ENDIF
+
+        IFNDEF __GENERATE_APPLICATION__
+mPMFVAL1_PMFVAL10                        EQU        This_symb_has_been_depreciated
+mPMFVAL1_PMFVAL11                        EQU        This_symb_has_been_depreciated
+mPMFVAL1_PMFVAL12                        EQU        This_symb_has_been_depreciated
+mPMFVAL1_PMFVAL13                        EQU        This_symb_has_been_depreciated
+mPMFVAL1_PMFVAL14                        EQU        This_symb_has_been_depreciated
+mPMFVAL1_PMFVAL15                        EQU        This_symb_has_been_depreciated
+mPMFVAL1_PMFVAL16                        EQU        This_symb_has_been_depreciated
+mPMFVAL1_PMFVAL17                        EQU        This_symb_has_been_depreciated
+mPMFVAL1_PMFVAL18                        EQU        This_symb_has_been_depreciated
+mPMFVAL1_PMFVAL19                        EQU        This_symb_has_been_depreciated
+mPMFVAL1_PMFVAL110                       EQU        This_symb_has_been_depreciated
+mPMFVAL1_PMFVAL111                       EQU        This_symb_has_been_depreciated
+mPMFVAL1_PMFVAL112                       EQU        This_symb_has_been_depreciated
+mPMFVAL1_PMFVAL113                       EQU        This_symb_has_been_depreciated
+mPMFVAL1_PMFVAL114                       EQU        This_symb_has_been_depreciated
+        ENDIF
+
+        IFNDEF __GENERATE_APPLICATION__
+mPMFVAL2_PMFVAL20                        EQU        This_symb_has_been_depreciated
+mPMFVAL2_PMFVAL21                        EQU        This_symb_has_been_depreciated
+mPMFVAL2_PMFVAL22                        EQU        This_symb_has_been_depreciated
+mPMFVAL2_PMFVAL23                        EQU        This_symb_has_been_depreciated
+mPMFVAL2_PMFVAL24                        EQU        This_symb_has_been_depreciated
+mPMFVAL2_PMFVAL25                        EQU        This_symb_has_been_depreciated
+mPMFVAL2_PMFVAL26                        EQU        This_symb_has_been_depreciated
+mPMFVAL2_PMFVAL27                        EQU        This_symb_has_been_depreciated
+mPMFVAL2_PMFVAL28                        EQU        This_symb_has_been_depreciated
+mPMFVAL2_PMFVAL29                        EQU        This_symb_has_been_depreciated
+mPMFVAL2_PMFVAL210                       EQU        This_symb_has_been_depreciated
+mPMFVAL2_PMFVAL211                       EQU        This_symb_has_been_depreciated
+mPMFVAL2_PMFVAL212                       EQU        This_symb_has_been_depreciated
+mPMFVAL2_PMFVAL213                       EQU        This_symb_has_been_depreciated
+mPMFVAL2_PMFVAL214                       EQU        This_symb_has_been_depreciated
+        ENDIF
+
+        IFNDEF __GENERATE_APPLICATION__
+mPMFVAL3_PMFVAL30                        EQU        This_symb_has_been_depreciated
+mPMFVAL3_PMFVAL31                        EQU        This_symb_has_been_depreciated
+mPMFVAL3_PMFVAL32                        EQU        This_symb_has_been_depreciated
+mPMFVAL3_PMFVAL33                        EQU        This_symb_has_been_depreciated
+mPMFVAL3_PMFVAL34                        EQU        This_symb_has_been_depreciated
+mPMFVAL3_PMFVAL35                        EQU        This_symb_has_been_depreciated
+mPMFVAL3_PMFVAL36                        EQU        This_symb_has_been_depreciated
+mPMFVAL3_PMFVAL37                        EQU        This_symb_has_been_depreciated
+mPMFVAL3_PMFVAL38                        EQU        This_symb_has_been_depreciated
+mPMFVAL3_PMFVAL39                        EQU        This_symb_has_been_depreciated
+mPMFVAL3_PMFVAL310                       EQU        This_symb_has_been_depreciated
+mPMFVAL3_PMFVAL311                       EQU        This_symb_has_been_depreciated
+mPMFVAL3_PMFVAL312                       EQU        This_symb_has_been_depreciated
+mPMFVAL3_PMFVAL313                       EQU        This_symb_has_been_depreciated
+mPMFVAL3_PMFVAL314                       EQU        This_symb_has_been_depreciated
+        ENDIF
+
+        IFNDEF __GENERATE_APPLICATION__
+mPMFVAL4_PMFVAL40                        EQU        This_symb_has_been_depreciated
+mPMFVAL4_PMFVAL41                        EQU        This_symb_has_been_depreciated
+mPMFVAL4_PMFVAL42                        EQU        This_symb_has_been_depreciated
+mPMFVAL4_PMFVAL43                        EQU        This_symb_has_been_depreciated
+mPMFVAL4_PMFVAL44                        EQU        This_symb_has_been_depreciated
+mPMFVAL4_PMFVAL45                        EQU        This_symb_has_been_depreciated
+mPMFVAL4_PMFVAL46                        EQU        This_symb_has_been_depreciated
+mPMFVAL4_PMFVAL47                        EQU        This_symb_has_been_depreciated
+mPMFVAL4_PMFVAL48                        EQU        This_symb_has_been_depreciated
+mPMFVAL4_PMFVAL49                        EQU        This_symb_has_been_depreciated
+mPMFVAL4_PMFVAL410                       EQU        This_symb_has_been_depreciated
+mPMFVAL4_PMFVAL411                       EQU        This_symb_has_been_depreciated
+mPMFVAL4_PMFVAL412                       EQU        This_symb_has_been_depreciated
+mPMFVAL4_PMFVAL413                       EQU        This_symb_has_been_depreciated
+mPMFVAL4_PMFVAL414                       EQU        This_symb_has_been_depreciated
+        ENDIF
+
+        IFNDEF __GENERATE_APPLICATION__
+mPMFVAL5_PMFVAL50                        EQU        This_symb_has_been_depreciated
+mPMFVAL5_PMFVAL51                        EQU        This_symb_has_been_depreciated
+mPMFVAL5_PMFVAL52                        EQU        This_symb_has_been_depreciated
+mPMFVAL5_PMFVAL53                        EQU        This_symb_has_been_depreciated
+mPMFVAL5_PMFVAL54                        EQU        This_symb_has_been_depreciated
+mPMFVAL5_PMFVAL55                        EQU        This_symb_has_been_depreciated
+mPMFVAL5_PMFVAL56                        EQU        This_symb_has_been_depreciated
+mPMFVAL5_PMFVAL57                        EQU        This_symb_has_been_depreciated
+mPMFVAL5_PMFVAL58                        EQU        This_symb_has_been_depreciated
+mPMFVAL5_PMFVAL59                        EQU        This_symb_has_been_depreciated
+mPMFVAL5_PMFVAL510                       EQU        This_symb_has_been_depreciated
+mPMFVAL5_PMFVAL511                       EQU        This_symb_has_been_depreciated
+mPMFVAL5_PMFVAL512                       EQU        This_symb_has_been_depreciated
+mPMFVAL5_PMFVAL513                       EQU        This_symb_has_been_depreciated
+mPMFVAL5_PMFVAL514                       EQU        This_symb_has_been_depreciated
+        ENDIF
+
+
+
+;
+; Follows changes from the database 2.87.521 version
+VREGCTRL0                                EQU        VREGCTRL
+VREGCTRL0_LVIF                           EQU        VREGCTRL_LVIF
+mVREGCTRL0_LVIF                          EQU        mVREGCTRL_LVIF
+VREGCTRL0_LVIE                           EQU        VREGCTRL_LVIE
+mVREGCTRL0_LVIE                          EQU        mVREGCTRL_LVIE
+VREGCTRL0_LVDS                           EQU        VREGCTRL_LVDS
+mVREGCTRL0_LVDS                          EQU        mVREGCTRL_LVDS
+
+
+; **** 6.8.2009 10:22:24
+
+        IFNDEF __GENERATE_APPLICATION__
+PMFCNTA_PMFCNTA0:                        equ        This_symb_has_been_depreciated
+PMFCNTA_PMFCNTA1:                        equ        This_symb_has_been_depreciated
+PMFCNTA_PMFCNTA2:                        equ        This_symb_has_been_depreciated
+PMFCNTA_PMFCNTA3:                        equ        This_symb_has_been_depreciated
+PMFCNTA_PMFCNTA4:                        equ        This_symb_has_been_depreciated
+PMFCNTA_PMFCNTA5:                        equ        This_symb_has_been_depreciated
+PMFCNTA_PMFCNTA6:                        equ        This_symb_has_been_depreciated
+PMFCNTA_PMFCNTA7:                        equ        This_symb_has_been_depreciated
+PMFCNTA_PMFCNTA8:                        equ        This_symb_has_been_depreciated
+PMFCNTA_PMFCNTA9:                        equ        This_symb_has_been_depreciated
+PMFCNTA_PMFCNTA10:                       equ        This_symb_has_been_depreciated
+PMFCNTA_PMFCNTA11:                       equ        This_symb_has_been_depreciated
+PMFCNTA_PMFCNTA12:                       equ        This_symb_has_been_depreciated
+PMFCNTA_PMFCNTA13:                       equ        This_symb_has_been_depreciated
+PMFCNTA_PMFCNTA14:                       equ        This_symb_has_been_depreciated
+mPMFCNTA_PMFCNTA0:                       equ        This_symb_has_been_depreciated
+mPMFCNTA_PMFCNTA1:                       equ        This_symb_has_been_depreciated
+mPMFCNTA_PMFCNTA2:                       equ        This_symb_has_been_depreciated
+mPMFCNTA_PMFCNTA3:                       equ        This_symb_has_been_depreciated
+mPMFCNTA_PMFCNTA4:                       equ        This_symb_has_been_depreciated
+mPMFCNTA_PMFCNTA5:                       equ        This_symb_has_been_depreciated
+mPMFCNTA_PMFCNTA6:                       equ        This_symb_has_been_depreciated
+mPMFCNTA_PMFCNTA7:                       equ        This_symb_has_been_depreciated
+mPMFCNTA_PMFCNTA8:                       equ        This_symb_has_been_depreciated
+mPMFCNTA_PMFCNTA9:                       equ        This_symb_has_been_depreciated
+mPMFCNTA_PMFCNTA10:                      equ        This_symb_has_been_depreciated
+mPMFCNTA_PMFCNTA11:                      equ        This_symb_has_been_depreciated
+mPMFCNTA_PMFCNTA12:                      equ        This_symb_has_been_depreciated
+mPMFCNTA_PMFCNTA13:                      equ        This_symb_has_been_depreciated
+mPMFCNTA_PMFCNTA14:                      equ        This_symb_has_been_depreciated
+PMFMODA_PMFMODA0:                        equ        This_symb_has_been_depreciated
+PMFMODA_PMFMODA1:                        equ        This_symb_has_been_depreciated
+PMFMODA_PMFMODA2:                        equ        This_symb_has_been_depreciated
+PMFMODA_PMFMODA3:                        equ        This_symb_has_been_depreciated
+PMFMODA_PMFMODA4:                        equ        This_symb_has_been_depreciated
+PMFMODA_PMFMODA5:                        equ        This_symb_has_been_depreciated
+PMFMODA_PMFMODA6:                        equ        This_symb_has_been_depreciated
+PMFMODA_PMFMODA7:                        equ        This_symb_has_been_depreciated
+PMFMODA_PMFMODA8:                        equ        This_symb_has_been_depreciated
+PMFMODA_PMFMODA9:                        equ        This_symb_has_been_depreciated
+PMFMODA_PMFMODA10:                       equ        This_symb_has_been_depreciated
+PMFMODA_PMFMODA11:                       equ        This_symb_has_been_depreciated
+PMFMODA_PMFMODA12:                       equ        This_symb_has_been_depreciated
+PMFMODA_PMFMODA13:                       equ        This_symb_has_been_depreciated
+PMFMODA_PMFMODA14:                       equ        This_symb_has_been_depreciated
+mPMFMODA_PMFMODA0:                       equ        This_symb_has_been_depreciated
+mPMFMODA_PMFMODA1:                       equ        This_symb_has_been_depreciated
+mPMFMODA_PMFMODA2:                       equ        This_symb_has_been_depreciated
+mPMFMODA_PMFMODA3:                       equ        This_symb_has_been_depreciated
+mPMFMODA_PMFMODA4:                       equ        This_symb_has_been_depreciated
+mPMFMODA_PMFMODA5:                       equ        This_symb_has_been_depreciated
+mPMFMODA_PMFMODA6:                       equ        This_symb_has_been_depreciated
+mPMFMODA_PMFMODA7:                       equ        This_symb_has_been_depreciated
+mPMFMODA_PMFMODA8:                       equ        This_symb_has_been_depreciated
+mPMFMODA_PMFMODA9:                       equ        This_symb_has_been_depreciated
+mPMFMODA_PMFMODA10:                      equ        This_symb_has_been_depreciated
+mPMFMODA_PMFMODA11:                      equ        This_symb_has_been_depreciated
+mPMFMODA_PMFMODA12:                      equ        This_symb_has_been_depreciated
+mPMFMODA_PMFMODA13:                      equ        This_symb_has_been_depreciated
+mPMFMODA_PMFMODA14:                      equ        This_symb_has_been_depreciated
+PMFDTMA_PMFDTMA0:                        equ        This_symb_has_been_depreciated
+PMFDTMA_PMFDTMA1:                        equ        This_symb_has_been_depreciated
+PMFDTMA_PMFDTMA2:                        equ        This_symb_has_been_depreciated
+PMFDTMA_PMFDTMA3:                        equ        This_symb_has_been_depreciated
+PMFDTMA_PMFDTMA4:                        equ        This_symb_has_been_depreciated
+PMFDTMA_PMFDTMA5:                        equ        This_symb_has_been_depreciated
+PMFDTMA_PMFDTMA6:                        equ        This_symb_has_been_depreciated
+PMFDTMA_PMFDTMA7:                        equ        This_symb_has_been_depreciated
+PMFDTMA_PMFDTMA8:                        equ        This_symb_has_been_depreciated
+PMFDTMA_PMFDTMA9:                        equ        This_symb_has_been_depreciated
+PMFDTMA_PMFDTMA10:                       equ        This_symb_has_been_depreciated
+PMFDTMA_PMFDTMA11:                       equ        This_symb_has_been_depreciated
+mPMFDTMA_PMFDTMA0:                       equ        This_symb_has_been_depreciated
+mPMFDTMA_PMFDTMA1:                       equ        This_symb_has_been_depreciated
+mPMFDTMA_PMFDTMA2:                       equ        This_symb_has_been_depreciated
+mPMFDTMA_PMFDTMA3:                       equ        This_symb_has_been_depreciated
+mPMFDTMA_PMFDTMA4:                       equ        This_symb_has_been_depreciated
+mPMFDTMA_PMFDTMA5:                       equ        This_symb_has_been_depreciated
+mPMFDTMA_PMFDTMA6:                       equ        This_symb_has_been_depreciated
+mPMFDTMA_PMFDTMA7:                       equ        This_symb_has_been_depreciated
+mPMFDTMA_PMFDTMA8:                       equ        This_symb_has_been_depreciated
+mPMFDTMA_PMFDTMA9:                       equ        This_symb_has_been_depreciated
+mPMFDTMA_PMFDTMA10:                      equ        This_symb_has_been_depreciated
+mPMFDTMA_PMFDTMA11:                      equ        This_symb_has_been_depreciated
+PMFCNTB_PMFCNTB0:                        equ        This_symb_has_been_depreciated
+PMFCNTB_PMFCNTB1:                        equ        This_symb_has_been_depreciated
+PMFCNTB_PMFCNTB2:                        equ        This_symb_has_been_depreciated
+PMFCNTB_PMFCNTB3:                        equ        This_symb_has_been_depreciated
+PMFCNTB_PMFCNTB4:                        equ        This_symb_has_been_depreciated
+PMFCNTB_PMFCNTB5:                        equ        This_symb_has_been_depreciated
+PMFCNTB_PMFCNTB6:                        equ        This_symb_has_been_depreciated
+PMFCNTB_PMFCNTB7:                        equ        This_symb_has_been_depreciated
+PMFCNTB_PMFCNTB8:                        equ        This_symb_has_been_depreciated
+PMFCNTB_PMFCNTB9:                        equ        This_symb_has_been_depreciated
+PMFCNTB_PMFCNTB10:                       equ        This_symb_has_been_depreciated
+PMFCNTB_PMFCNTB11:                       equ        This_symb_has_been_depreciated
+PMFCNTB_PMFCNTB12:                       equ        This_symb_has_been_depreciated
+PMFCNTB_PMFCNTB13:                       equ        This_symb_has_been_depreciated
+PMFCNTB_PMFCNTB14:                       equ        This_symb_has_been_depreciated
+mPMFCNTB_PMFCNTB0:                       equ        This_symb_has_been_depreciated
+mPMFCNTB_PMFCNTB1:                       equ        This_symb_has_been_depreciated
+mPMFCNTB_PMFCNTB2:                       equ        This_symb_has_been_depreciated
+mPMFCNTB_PMFCNTB3:                       equ        This_symb_has_been_depreciated
+mPMFCNTB_PMFCNTB4:                       equ        This_symb_has_been_depreciated
+mPMFCNTB_PMFCNTB5:                       equ        This_symb_has_been_depreciated
+mPMFCNTB_PMFCNTB6:                       equ        This_symb_has_been_depreciated
+mPMFCNTB_PMFCNTB7:                       equ        This_symb_has_been_depreciated
+mPMFCNTB_PMFCNTB8:                       equ        This_symb_has_been_depreciated
+mPMFCNTB_PMFCNTB9:                       equ        This_symb_has_been_depreciated
+mPMFCNTB_PMFCNTB10:                      equ        This_symb_has_been_depreciated
+mPMFCNTB_PMFCNTB11:                      equ        This_symb_has_been_depreciated
+mPMFCNTB_PMFCNTB12:                      equ        This_symb_has_been_depreciated
+mPMFCNTB_PMFCNTB13:                      equ        This_symb_has_been_depreciated
+mPMFCNTB_PMFCNTB14:                      equ        This_symb_has_been_depreciated
+PMFMODB_PMFMODB0:                        equ        This_symb_has_been_depreciated
+PMFMODB_PMFMODB1:                        equ        This_symb_has_been_depreciated
+PMFMODB_PMFMODB2:                        equ        This_symb_has_been_depreciated
+PMFMODB_PMFMODB3:                        equ        This_symb_has_been_depreciated
+PMFMODB_PMFMODB4:                        equ        This_symb_has_been_depreciated
+PMFMODB_PMFMODB5:                        equ        This_symb_has_been_depreciated
+PMFMODB_PMFMODB6:                        equ        This_symb_has_been_depreciated
+PMFMODB_PMFMODB7:                        equ        This_symb_has_been_depreciated
+PMFMODB_PMFMODB8:                        equ        This_symb_has_been_depreciated
+PMFMODB_PMFMODB9:                        equ        This_symb_has_been_depreciated
+PMFMODB_PMFMODB10:                       equ        This_symb_has_been_depreciated
+PMFMODB_PMFMODB11:                       equ        This_symb_has_been_depreciated
+PMFMODB_PMFMODB12:                       equ        This_symb_has_been_depreciated
+PMFMODB_PMFMODB13:                       equ        This_symb_has_been_depreciated
+PMFMODB_PMFMODB14:                       equ        This_symb_has_been_depreciated
+mPMFMODB_PMFMODB0:                       equ        This_symb_has_been_depreciated
+mPMFMODB_PMFMODB1:                       equ        This_symb_has_been_depreciated
+mPMFMODB_PMFMODB2:                       equ        This_symb_has_been_depreciated
+mPMFMODB_PMFMODB3:                       equ        This_symb_has_been_depreciated
+mPMFMODB_PMFMODB4:                       equ        This_symb_has_been_depreciated
+mPMFMODB_PMFMODB5:                       equ        This_symb_has_been_depreciated
+mPMFMODB_PMFMODB6:                       equ        This_symb_has_been_depreciated
+mPMFMODB_PMFMODB7:                       equ        This_symb_has_been_depreciated
+mPMFMODB_PMFMODB8:                       equ        This_symb_has_been_depreciated
+mPMFMODB_PMFMODB9:                       equ        This_symb_has_been_depreciated
+mPMFMODB_PMFMODB10:                      equ        This_symb_has_been_depreciated
+mPMFMODB_PMFMODB11:                      equ        This_symb_has_been_depreciated
+mPMFMODB_PMFMODB12:                      equ        This_symb_has_been_depreciated
+mPMFMODB_PMFMODB13:                      equ        This_symb_has_been_depreciated
+mPMFMODB_PMFMODB14:                      equ        This_symb_has_been_depreciated
+PMFDTMB_PMFDTMB0:                        equ        This_symb_has_been_depreciated
+PMFDTMB_PMFDTMB1:                        equ        This_symb_has_been_depreciated
+PMFDTMB_PMFDTMB2:                        equ        This_symb_has_been_depreciated
+PMFDTMB_PMFDTMB3:                        equ        This_symb_has_been_depreciated
+PMFDTMB_PMFDTMB4:                        equ        This_symb_has_been_depreciated
+PMFDTMB_PMFDTMB5:                        equ        This_symb_has_been_depreciated
+PMFDTMB_PMFDTMB6:                        equ        This_symb_has_been_depreciated
+PMFDTMB_PMFDTMB7:                        equ        This_symb_has_been_depreciated
+PMFDTMB_PMFDTMB8:                        equ        This_symb_has_been_depreciated
+PMFDTMB_PMFDTMB9:                        equ        This_symb_has_been_depreciated
+PMFDTMB_PMFDTMB10:                       equ        This_symb_has_been_depreciated
+PMFDTMB_PMFDTMB11:                       equ        This_symb_has_been_depreciated
+mPMFDTMB_PMFDTMB0:                       equ        This_symb_has_been_depreciated
+mPMFDTMB_PMFDTMB1:                       equ        This_symb_has_been_depreciated
+mPMFDTMB_PMFDTMB2:                       equ        This_symb_has_been_depreciated
+mPMFDTMB_PMFDTMB3:                       equ        This_symb_has_been_depreciated
+mPMFDTMB_PMFDTMB4:                       equ        This_symb_has_been_depreciated
+mPMFDTMB_PMFDTMB5:                       equ        This_symb_has_been_depreciated
+mPMFDTMB_PMFDTMB6:                       equ        This_symb_has_been_depreciated
+mPMFDTMB_PMFDTMB7:                       equ        This_symb_has_been_depreciated
+mPMFDTMB_PMFDTMB8:                       equ        This_symb_has_been_depreciated
+mPMFDTMB_PMFDTMB9:                       equ        This_symb_has_been_depreciated
+mPMFDTMB_PMFDTMB10:                      equ        This_symb_has_been_depreciated
+mPMFDTMB_PMFDTMB11:                      equ        This_symb_has_been_depreciated
+PMFCNTC_PMFCNTC0:                        equ        This_symb_has_been_depreciated
+PMFCNTC_PMFCNTC1:                        equ        This_symb_has_been_depreciated
+PMFCNTC_PMFCNTC2:                        equ        This_symb_has_been_depreciated
+PMFCNTC_PMFCNTC3:                        equ        This_symb_has_been_depreciated
+PMFCNTC_PMFCNTC4:                        equ        This_symb_has_been_depreciated
+PMFCNTC_PMFCNTC5:                        equ        This_symb_has_been_depreciated
+PMFCNTC_PMFCNTC6:                        equ        This_symb_has_been_depreciated
+PMFCNTC_PMFCNTC7:                        equ        This_symb_has_been_depreciated
+PMFCNTC_PMFCNTC8:                        equ        This_symb_has_been_depreciated
+PMFCNTC_PMFCNTC9:                        equ        This_symb_has_been_depreciated
+PMFCNTC_PMFCNTC10:                       equ        This_symb_has_been_depreciated
+PMFCNTC_PMFCNTC11:                       equ        This_symb_has_been_depreciated
+PMFCNTC_PMFCNTC12:                       equ        This_symb_has_been_depreciated
+PMFCNTC_PMFCNTC13:                       equ        This_symb_has_been_depreciated
+PMFCNTC_PMFCNTC14:                       equ        This_symb_has_been_depreciated
+mPMFCNTC_PMFCNTC0:                       equ        This_symb_has_been_depreciated
+mPMFCNTC_PMFCNTC1:                       equ        This_symb_has_been_depreciated
+mPMFCNTC_PMFCNTC2:                       equ        This_symb_has_been_depreciated
+mPMFCNTC_PMFCNTC3:                       equ        This_symb_has_been_depreciated
+mPMFCNTC_PMFCNTC4:                       equ        This_symb_has_been_depreciated
+mPMFCNTC_PMFCNTC5:                       equ        This_symb_has_been_depreciated
+mPMFCNTC_PMFCNTC6:                       equ        This_symb_has_been_depreciated
+mPMFCNTC_PMFCNTC7:                       equ        This_symb_has_been_depreciated
+mPMFCNTC_PMFCNTC8:                       equ        This_symb_has_been_depreciated
+mPMFCNTC_PMFCNTC9:                       equ        This_symb_has_been_depreciated
+mPMFCNTC_PMFCNTC10:                      equ        This_symb_has_been_depreciated
+mPMFCNTC_PMFCNTC11:                      equ        This_symb_has_been_depreciated
+mPMFCNTC_PMFCNTC12:                      equ        This_symb_has_been_depreciated
+mPMFCNTC_PMFCNTC13:                      equ        This_symb_has_been_depreciated
+mPMFCNTC_PMFCNTC14:                      equ        This_symb_has_been_depreciated
+PMFMODC_PMFMODC0:                        equ        This_symb_has_been_depreciated
+PMFMODC_PMFMODC1:                        equ        This_symb_has_been_depreciated
+PMFMODC_PMFMODC2:                        equ        This_symb_has_been_depreciated
+PMFMODC_PMFMODC3:                        equ        This_symb_has_been_depreciated
+PMFMODC_PMFMODC4:                        equ        This_symb_has_been_depreciated
+PMFMODC_PMFMODC5:                        equ        This_symb_has_been_depreciated
+PMFMODC_PMFMODC6:                        equ        This_symb_has_been_depreciated
+PMFMODC_PMFMODC7:                        equ        This_symb_has_been_depreciated
+PMFMODC_PMFMODC8:                        equ        This_symb_has_been_depreciated
+PMFMODC_PMFMODC9:                        equ        This_symb_has_been_depreciated
+PMFMODC_PMFMODC10:                       equ        This_symb_has_been_depreciated
+PMFMODC_PMFMODC11:                       equ        This_symb_has_been_depreciated
+PMFMODC_PMFMODC12:                       equ        This_symb_has_been_depreciated
+PMFMODC_PMFMODC13:                       equ        This_symb_has_been_depreciated
+PMFMODC_PMFMODC14:                       equ        This_symb_has_been_depreciated
+mPMFMODC_PMFMODC0:                       equ        This_symb_has_been_depreciated
+mPMFMODC_PMFMODC1:                       equ        This_symb_has_been_depreciated
+mPMFMODC_PMFMODC2:                       equ        This_symb_has_been_depreciated
+mPMFMODC_PMFMODC3:                       equ        This_symb_has_been_depreciated
+mPMFMODC_PMFMODC4:                       equ        This_symb_has_been_depreciated
+mPMFMODC_PMFMODC5:                       equ        This_symb_has_been_depreciated
+mPMFMODC_PMFMODC6:                       equ        This_symb_has_been_depreciated
+mPMFMODC_PMFMODC7:                       equ        This_symb_has_been_depreciated
+mPMFMODC_PMFMODC8:                       equ        This_symb_has_been_depreciated
+mPMFMODC_PMFMODC9:                       equ        This_symb_has_been_depreciated
+mPMFMODC_PMFMODC10:                      equ        This_symb_has_been_depreciated
+mPMFMODC_PMFMODC11:                      equ        This_symb_has_been_depreciated
+mPMFMODC_PMFMODC12:                      equ        This_symb_has_been_depreciated
+mPMFMODC_PMFMODC13:                      equ        This_symb_has_been_depreciated
+mPMFMODC_PMFMODC14:                      equ        This_symb_has_been_depreciated
+PMFDTMC_PMFDTMC0:                        equ        This_symb_has_been_depreciated
+PMFDTMC_PMFDTMC1:                        equ        This_symb_has_been_depreciated
+PMFDTMC_PMFDTMC2:                        equ        This_symb_has_been_depreciated
+PMFDTMC_PMFDTMC3:                        equ        This_symb_has_been_depreciated
+PMFDTMC_PMFDTMC4:                        equ        This_symb_has_been_depreciated
+PMFDTMC_PMFDTMC5:                        equ        This_symb_has_been_depreciated
+PMFDTMC_PMFDTMC6:                        equ        This_symb_has_been_depreciated
+PMFDTMC_PMFDTMC7:                        equ        This_symb_has_been_depreciated
+PMFDTMC_PMFDTMC8:                        equ        This_symb_has_been_depreciated
+PMFDTMC_PMFDTMC9:                        equ        This_symb_has_been_depreciated
+PMFDTMC_PMFDTMC10:                       equ        This_symb_has_been_depreciated
+PMFDTMC_PMFDTMC11:                       equ        This_symb_has_been_depreciated
+mPMFDTMC_PMFDTMC0:                       equ        This_symb_has_been_depreciated
+mPMFDTMC_PMFDTMC1:                       equ        This_symb_has_been_depreciated
+mPMFDTMC_PMFDTMC2:                       equ        This_symb_has_been_depreciated
+mPMFDTMC_PMFDTMC3:                       equ        This_symb_has_been_depreciated
+mPMFDTMC_PMFDTMC4:                       equ        This_symb_has_been_depreciated
+mPMFDTMC_PMFDTMC5:                       equ        This_symb_has_been_depreciated
+mPMFDTMC_PMFDTMC6:                       equ        This_symb_has_been_depreciated
+mPMFDTMC_PMFDTMC7:                       equ        This_symb_has_been_depreciated
+mPMFDTMC_PMFDTMC8:                       equ        This_symb_has_been_depreciated
+mPMFDTMC_PMFDTMC9:                       equ        This_symb_has_been_depreciated
+mPMFDTMC_PMFDTMC10:                      equ        This_symb_has_been_depreciated
+mPMFDTMC_PMFDTMC11:                      equ        This_symb_has_been_depreciated
+        ENDIF
+
+; EOF
+
+		
+
+            
+            XREF __SEG_END_SSTACK      ; symbol defined by the linker for the end of the stack
+            ; LCD References
+	          XREF  init_LCD
+
+; export symbols
+            ; we use export 'Entry' as symbol. This allows us to
+            ; reference 'Entry' either in the linker .prm file
+            ; or from C/C++ later on
+            XDEF  Entry,_Startup,disp,CRGFLG
+            
+            ;==================== variables =================================
+            ;password
+            XDEF  password,new_password,pw_prompt_shown,pw_check,pw_correct,pw_set,pw_incorrect,entered_password,pw_required
+            ;keypad
+            XDEF  pressed_key,pressed_num,await_key_release,await_key_press
+            ;menu
+            XDEF  menu_active,toast_timer,menu_option_num,menu_timer,display_timeout
+            ;watering (menu option 1)
+            XDEF  is_watering,watering_timer,sprinkler_event,sprinkler_timer,sprinkler_arr_i
+            ;temperature (menu option 2)
+            XDEF  show_temperature,fan_speed,circulation_count,dc_on
+            ;wall clock (menu option 3)
+            XDEF  current_year,current_month,current_day,current_hour,current_minute,current_second
+            XDEF  display_time,wall_timer,clock_event,second_passed,ms_counter
+            ;adjust clock (menu option 4)
+            XDEF  change_time
+            ;reset password (menu option 5)
+            XDEF  pw_reset
+            
+            ;================== constants =================================
+            ;ports and peripherals 
+            XDEF  PSR_U,PDR_U,PORT_U,DDR_T,PORT_T,DDR_P,PORT_P,DDR_S,PORT_S
+            ;keypad
+            XDEF  KVS,SEQUENCE
+            ;stepper motor
+            XDEF  SPRINKLER_ARR
+
+            ;===================== subroutines =============================
+            ; Potentiometer References
+            XREF  display_string
+            XREF  pot_value
+
+            ;subroutines
+            XREF  Password,Menu,Keypad,Water,Circulation,Wall,Growlights
+            
+            ;================= debugging ===================================
+            XDEF  word_out,byte_out
+            
+            
+            
+            
+; ================= general notes =====================
+; - routines should generally be asynchronous            
+; - need a way to marshall values into single characters
+;     like the pot. resistance display from lab
+; - use two seperate routines, one for each song
+; - set all the flags with the 1 ms RTI
+; - reading the password asychronously will be a
+;     pain in the ass, maybe skip that
+;     - think about the last lab and skipping the await
+;====================================================== 
+   
+   
+            
+;================ flow of the program =================
+; 1. Prompt for the password. Nothing will happen until the password is set.
+; 2. Acknowlege the password, wait, then show help, wait, then show menu
+; 3. Show help, wait (press 0 to show help)
+; 4. Show main menu, start air circulation, and start grow light control
+;======================================================
+
+
+
+;==================== main menu =======================
+; 1. water the plants
+; 2. show temperature (adjusts when the pot is turned)
+; 3. show time
+; 4. set time (passord protected)
+; 5. change password (password protected)
+;======================================================
+
+; variable/data section
+my_variable: SECTION
+disp            	ds.b    33        ;the character string to output to the LCD (given)
+
+;password variables
+password:         ds.b    8         ;the byte array that stores the password
+entered_password  ds.b    8         ;will be check against the password
+new_password      ds.b    8         ;overwrite the old password with a new one
+pw_prompt_shown   ds.b    1         ;only print the initial password prompt once
+pw_check          ds.b    1         ;require the password before continueing
+pw_correct        ds.b    1         ;check the correctness of the password
+pw_set            ds.b    1         ;flag to fire after the password has been entered
+pw_incorrect      ds.b    1         ;will determine if the password needs to be tried again
+pw_required       ds.b    1         ;flag to set if a password is required to enter a screen
+
+;keypad variables
+pressed_key       ds.b    1         ;the keypad value in the LUT
+pressed_num       ds.b    1         ;the numeral of the pressed key or the index of PRESSED in the LUT
+await_key_release ds.b    1         ;whether or not to await the keypad release
+await_key_press   ds.b    1
+
+;================== state variables =====================
+
+; Primary UI 
+menu_active       ds.b    1         ;show the main menu
+toast_timer       ds.w    1         ;(counter) used to delay the screen outputs so that the user can read them
+menu_option_num   ds.b    1         ;which menu option is displayed
+menu_timer        ds.w    1         ;timer to check the menu cycle
+display_timeout   ds.b    1         ;(flag) to go back to the menu when an input is made
+
+; menu item 1 (watering state)
+is_watering       ds.b    1         ;flag that sets the state to watering (spin the motor, play the tune, and
+                                    ;show "Watering in \nprogress..." on the LCD
+                                    ;also one or more LED's should illuminate
+                                    ;also the stepper motor should spin like a sprinkler
+                                    ;also this should only run for a period of time
+watering_timer    ds.w    1         ;(counter) to time the watering, stop after some time
+sprinkler_event   ds.b    1         ;event to fire to spin stepper motor like a sprinkler
+sprinkler_timer   ds.b    1         ;(counter) time delay for sprinkler
+sprinkler_arr_i   ds.b    1         ;sprinkler array index
+; menu item 2 (air circulation state, show temperature)
+show_temperature  ds.b    1         ;display the current temperature    
+fan_speed         ds.b    1         ;reads the potentiometer
+circulation_count ds.b    1         ;counter to spin the DC motor
+dc_on             ds.b    1         ;event pulse for DC motor
+
+; menu item 3 (display time)
+display_time      ds.b    1         ;show the time on the screen
+current_year      ds.w    1         ;what year is it 
+current_month     ds.b    1         ;what month is it (a number)
+current_day       ds.b    1         ;day of the month
+current_hour      ds.b    1         ;hour of the day (military time)
+current_minute    ds.b    1         ;...
+current_second    ds.b    1         ;...
+wall_timer        ds.w    1         ;timeout for the clock display
+clock_event       ds.b    1         ;event that will fire every 4 milliseconds
+ms_counter        ds.w    1         ;counter for the milliseconds
+second_passed     ds.b    1         ;event that fires when a second has passed
+setting_wall      ds.b    1         ;will flag when the clock is being set by the user
+
+; menu item 4 (change time)
+change_time       ds.b    1         ;the user has elected to change the date and the time
+                                    ;all or nothing on this; everything must be entered
+                                    
+; menu item 5 (change password)
+pw_reset          ds.b    1         ;flag to trigger that a password should be reset
+                                    ;this should be done in an async manner when prompted by the user
+                                    ;(in an emergency, this process should be synchronous)
+                                    ;in order to not stop the air or watering or grow lights
+
+; menu item 6 (plant seeds)
+
+
+
+; menu option 7 (show plot)
+               
+                                    
+                                    
+; debugging
+word_out          ds.w    1                                    
+byte_out          ds.b    1                                    
+;=============================== END state variables =====================================
+
+my_constant:  SECTION
+;ports
+DDR_U	      equ		  $26A
+PSR_U       equ     $26D
+PDR_U       equ     $26C
+PORT_U      equ     $268
+
+DDR_T       equ     $242  ;the DIP switches and DC motor
+PORT_T      equ     $240
+
+PORT_P    	equ   	$258         ;stepper motor
+DDR_P     	equ 	  $25A  
+
+DDR_S       equ     $24A   ;LED's
+PORT_S      equ     $248
+
+;keypad           ;key value pairs from 4.3
+KVS         dc.b  $EB,$77,$7B,$7D,$B7,$BB,$BD,$D7,$DB,$DD,$E7,$ED,$7E,$BE,$DE,$EE
+                  ;given sequence from lab instructions (with trailing zero)
+SEQUENCE    dc.b  $70,$B0,$D0,$E0,$00
+;stepper motor
+SPRINKLER_ARR dc.b $0A,$12,$14,$12,$14,$0C,$14,$0C 
+                    
+MyCode:     SECTION
+_Startup:
+Entry:
+            lds     #__SEG_END_SSTACK
+            ;keypad stuff 
+            BSET    DDR_U,#$F0        ;bits 1-3 in bits 4-7 out
+            BSET    PSR_U,#$F0        ;pins 1-3 pull up
+            BSET    PDR_U,#$0F        ;pull up pins 1-3
+            CLR     await_key_release ;do not await by default
+            MOVB    #$FF,await_key_press;await presses by default
+            
+            ;LED stuff
+            BSET    DDR_S,#$FF        ;all outputs on LED port
+            MOVB    #$00,PORT_S       ;off initally
+            
+            ;switch and DC motor stuff
+            MOVB    #$08,DDR_T        ;needs to be set for the motor to spin
+
+            ;LCD stuff
+            JSR  init_LCD
+            
+            ;event loop stuff
+            MOVB    #$80,CRGINT       ;enable real-time interrupts
+            MOVB    #$60,RTICTL       ;set RTI interval to 4 ms; "#$40,RTICTL" would be 1 ms
+            ;MOVB    #$40,RTICTL
+            CLI                       ;enable interrupts
+            
+            ;state variable stuff (password
+            MOVB  #$FF,password       ;this password will never be correct, it needs to be changed
+            MOVB  #$FF,password+1 
+            MOVB  #$FF,password+2 
+            MOVB  #$FF,password+3 
+            MOVB  #$FF,password+4 
+            MOVB  #$FF,password+5 
+            MOVB  #$FF,password+6 
+            MOVB  #$FF,password+7
+            CLR   pw_set              ;the password is not inititally set
+            CLR   pw_incorrect        ;the password will not start out as incorrect because it hasn't been set
+            CLR   pw_correct
+            
+            ;menu stuff
+            CLR   menu_active         ;menu is not inititally active
+            MOVB  #$01,menu_option_num;start on option '1'
+            CLR   menu_timer          ;set the menu timer at '0' this will be incremented in the event loop
+            
+            ;watering and stepper motor stuff
+            CLR   is_watering         ;watering
+            CLR   watering_timer      ;duration of watering
+            CLR   sprinkler_event     ;fired to the stepper motor
+            CLR   sprinkler_timer     ;duration of delay among items of the stepper array sequence
+            MOVB  #$1E,DDR_P          ;DDR setting for the stepper
+            MOVB  #$00,sprinkler_arr_i;start at the beginning of the array
+            
+            ;other menu items
+            CLR   show_temperature    ;menu item
+            CLR   change_time         ;menu item
+            CLR   pw_reset            ;menu item
+            
+            ;circulation             
+            CLR   fan_speed          
+            CLR   circulation_count
+            
+            ;wall clock
+            MOVW  #1970,current_year  ;UNIX time
+            MOVB  #1,current_month    ;start on Jan. 1
+            MOVB  #1,current_day      ;...
+            CLR   current_hour        ;start at 00:00:00
+            CLR   current_minute      ;...
+            CLR   current_second      ;...
+            CLR   wall_timer          ;the timer that sets whether or not the clock displays
+            CLR   clock_event         ;event is not initially fired
+            CLR   second_passed       ;event that will fire each time one second has passed
+            CLR   ms_counter          ;count milliseconds in the event loop
+            CLR   display_time
+
+                        
+Init:
+            ;run any password related things first
+            JSR   Password
+            
+            ;do nothing until the password is set
+            LDAA  pw_set
+            CMPA  #$FF
+            BNE   Init
+            
+            ;activate the menu after the password is set
+            MOVB  #$FF,menu_active
+            ;hide evey other display element
+            
+            
+            ;set the keypress to an impossible value
+            ;this clears the value from the password
+            ;before reading the keypress in the menu
+            MOVB  #$FF,pressed_num
+Main:           
+            ;go to the menu when the password is set
+            JSR   Menu
+            
+            ;call each subroutine
+            ;subroutines are controlled by events fired in the RTI
+            JSR   Circulation
+            JSR   Water
+            JSR   Growlights; <- should be uncommented (using LED's for debugging)
+            JSR   Wall
+            JSR   Password
+            
+            ;read the keypad when the menu is showing
+            ;make the keypad read not branch from the password leftover pressed value
+            ;the keypad being the primary means of controlling the program,
+            ;we have it running in main (for now) 
+            ;get user menu selection (do not await presses or releases)
+            MOVB  #$00,await_key_release
+            MOVB  #$00,await_key_press     
+            JSR   Keypad
+            
+            ;return to the main loop
+            BRA   Main

Final_Project/bin/menu.dbg

@@ -0,0 +1,266 @@
+                         	XDEF	Menu
+	XREF	__SEG_END_SSTACK,pw_set,disp,display_string,menu_option_num,menu_active,menu_selection
+	
+Variables:	    	Section
+
+Constants:	      Section
+
+Code:		  	Section
+
+Menu:      ;push register and accumulator values for retention                   
+            PSHA
+            PSHB
+            PSHD
+            PSHX
+            PSHY
+            
+            LDAA  menu_active ;do nothing if the menu is not active
+            CMPA  #$00
+            LBEQ  Return
+            
+PrintTopLine:
+           ;all menu items print this line
+           movb #'S',disp
+           movb #'e',disp+1
+           movb #'l',disp+2
+           movb #'e',disp+3
+           movb #'c',disp+4
+           movb #'t',disp+5
+           movb #' ',disp+6
+           movb #'o',disp+7
+           movb #'p',disp+8
+           movb #'t',disp+9
+           movb #'i',disp+10
+           movb #'o',disp+11
+           movb #'n',disp+12
+           movb #':',disp+13
+           movb #' ',disp+14
+           movb #' ',disp+15
+           ;next line
+           
+            ;load the menu option and output the correct lower string           
+            LDAA  menu_option_num
+            CMPA  #$01
+            LBEQ  PrintOption1
+                 
+            CMPA  #$02
+            LBEQ   PrintOption2
+            
+            CMPA  #$03
+            LBEQ  PrintOption3
+            
+            CMPA  #$04
+            LBEQ  PrintOption4
+            
+            CMPA  #$05
+            LBEQ  PrintOption5
+            
+            CMPA  #$06
+            LBEQ  PrintOption6
+
+            CMPA  #$07
+            LBEQ  PrintOption7
+            
+Reset:
+            MOVB  #$01,menu_option_num
+            LBRA  PrintTopLine
+              
+           
+;==================== main menu =======================
+; 1. water the plants
+; 2. show temperature (adjusts when the pot is turned)
+; 3. show time
+; 4. set time (passord protected)
+; 5. change password (password protected)
+;======================================================
+
+PrintOption1:
+           movb #'1',disp+16
+           movb #'.',disp+17
+           movb #' ',disp+18
+           movb #'W',disp+19
+           movb #'a',disp+20
+           movb #'t',disp+21
+           movb #'e',disp+22
+           movb #'r',disp+23
+           movb #' ',disp+24
+           movb #'p',disp+25
+           movb #'l',disp+26
+           movb #'a',disp+27
+           movb #'n',disp+28
+           movb #'t',disp+29
+           movb #'s',disp+30
+           movb #' ',disp+31
+           movb #0,disp+32    ;string terminator, acts like '\0'
+		       
+		       ;print the prompt string
+		       LDD   #disp         ;both of these steps are necessary to
+           jsr  display_string ;print to the LCD screen
+           
+           ;get out of the menu, do not go to PrintOption2
+           LBRA  Return
+
+PrintOption2:
+           movb #'2',disp+16
+           movb #'.',disp+17
+           movb #' ',disp+18
+           movb #'S',disp+19
+           movb #'h',disp+20
+           movb #'o',disp+21
+           movb #'w',disp+22
+           movb #' ',disp+23
+           movb #'t',disp+24
+           movb #'e',disp+25
+           movb #'m',disp+26
+           movb #'p',disp+27
+           movb #'.',disp+28
+           movb #' ',disp+29
+           movb #' ',disp+30
+           movb #' ',disp+31
+           movb #0,disp+32    ;string terminator, acts like '\0'
+           
+           ;print the prompt string
+		       LDD   #disp         ;both of these steps are necessary to
+           jsr  display_string ;print to the LCD screen
+           
+           ;get out of the menu, do not go to PrintOption23
+           LBRA  Return
+
+PrintOption3:
+           movb #'3',disp+16
+           movb #'.',disp+17
+           movb #' ',disp+18
+           movb #'S',disp+19
+           movb #'h',disp+20
+           movb #'o',disp+21
+           movb #'w',disp+22
+           movb #' ',disp+23
+           movb #'t',disp+24
+           movb #'i',disp+25
+           movb #'m',disp+26
+           movb #'e',disp+27
+           movb #' ',disp+28
+           movb #' ',disp+29
+           movb #' ',disp+30
+           movb #' ',disp+31
+           movb #0,disp+32    ;string terminator, acts like '\0'
+           
+           ;print the prompt string
+		       LDD   #disp         ;both of these steps are necessary to
+           jsr  display_string ;print to the LCD screen
+           
+           ;get out of the menu, do not go to PrintOption23
+           LBRA  Return
+PrintOption4:
+           movb #'4',disp+16
+           movb #'.',disp+17
+           movb #' ',disp+18
+           movb #'S',disp+19
+           movb #'e',disp+20
+           movb #'t',disp+21
+           movb #' ',disp+22
+           movb #'t',disp+23
+           movb #'i',disp+24
+           movb #'m',disp+25
+           movb #'e',disp+26
+           movb #' ',disp+27
+           movb #' ',disp+28
+           movb #' ',disp+29
+           movb #' ',disp+30
+           movb #' ',disp+31
+           movb #0,disp+32    ;string terminator, acts like '\0'
+           
+           ;print the prompt string
+		       LDD   #disp         ;both of these steps are necessary to
+           jsr  display_string ;print to the LCD screen
+           
+           ;get out of the menu, do not go to PrintOption23
+           LBRA Return
+PrintOption5:
+           movb #'5',disp+16
+           movb #'.',disp+17
+           movb #' ',disp+18
+           movb #'R',disp+19
+           movb #'e',disp+20
+           movb #'s',disp+21
+           movb #'e',disp+22
+           movb #'t',disp+23
+           movb #' ',disp+24
+           movb #'p',disp+25
+           movb #'a',disp+26
+           movb #'s',disp+27
+           movb #'s',disp+28
+           movb #'w',disp+29
+           movb #'d',disp+30
+           movb #'.',disp+31
+           movb #0,disp+32    ;string terminator, acts like '\0'
+           
+           ;print the prompt string
+		       LDD   #disp         ;both of these steps are necessary to
+           jsr  display_string ;print to the LCD screen
+           
+           ;get out of the menu, do not go to PrintOption23
+           LBRA Return
+           
+PrintOption6:
+           movb #'6',disp+16
+           movb #'.',disp+17
+           movb #' ',disp+18
+           movb #'P',disp+19
+           movb #'l',disp+20
+           movb #'a',disp+21
+           movb #'n',disp+22
+           movb #'t',disp+23
+           movb #' ',disp+24
+           movb #'s',disp+25
+           movb #'e',disp+26
+           movb #'e',disp+27
+           movb #'d',disp+28
+           movb #'s',disp+29
+           movb #' ',disp+30
+           movb #' ',disp+31
+           movb #0,disp+32    ;string terminator, acts like '\0'
+           
+           ;print the prompt string
+		       LDD   #disp         ;both of these steps are necessary to
+           jsr  display_string ;print to the LCD screen
+           
+           ;get out of the menu, do not go to PrintOption6
+           BRA  Return
+           
+PrintOption7:
+           movb #'7',disp+16
+           movb #'.',disp+17
+           movb #' ',disp+18
+           movb #'S',disp+19
+           movb #'h',disp+20
+           movb #'o',disp+21
+           movb #'w',disp+22
+           movb #' ',disp+23
+           movb #'p',disp+24
+           movb #'l',disp+25
+           movb #'o',disp+26
+           movb #'t',disp+27
+           movb #' ',disp+28
+           movb #' ',disp+29
+           movb #' ',disp+30
+           movb #' ',disp+31
+           movb #0,disp+32    ;string terminator, acts like '\0'
+           
+           ;print the prompt string
+		       LDD   #disp         ;both of these steps are necessary to
+           jsr  display_string ;print to the LCD screen
+           
+           ;get out of the menu, do not go to PrintOption7
+           BRA  Return
+           
+
+            
+Return:     ;restore registers and accumulators
+            PULY
+            PULX
+            PULD
+            PULB
+            PULA
+            
+            RTS

Final_Project/bin/password.dbg

@@ -0,0 +1,639 @@
+	XDEF	Password
+	XREF	__SEG_END_SSTACK,pw_required,byte_out,disp,Keypad,display_string,pressed_num,password,pw_set,pw_reset,pw_check,PORT_S,await_key_release,await_key_press,entered_password,pw_correct
+	
+Variables:	    	Section
+pw_char_index     ds.b  1
+pw_char           ds.b  1
+
+Constants:	      Section
+
+Code:		  	Section
+
+Password:
+           ;push register and accumulator values for retention                   
+            PSHA
+            PSHB
+            PSHD
+            PSHX
+            PSHY
+            
+            ;setting password for the 1st time
+            LDAA  pw_set
+            CMPA  #$00
+            BEQ   PasswordInit
+            
+            ;user has elected to change the password
+            LDAA  pw_reset
+            CMPA  #$FF
+            LBEQ   PasswordReset
+            
+            ;user has selected something requiring auth
+            LDAA  pw_check
+            CMPA  #$FF
+            LBEQ   PasswordCheck
+            
+            LBRA   Return
+            
+            
+PasswordInit:
+
+            
+           ;MOVB   #$FF,
+            
+            
+           ;inital prompt
+           movb #'S',disp
+           movb #'e',disp+1
+           movb #'t',disp+2
+           movb #' ',disp+3
+           movb #'p',disp+4
+           movb #'a',disp+5
+           movb #'s',disp+6
+           movb #'s',disp+7
+           movb #'w',disp+8
+           movb #'o',disp+9
+           movb #'r',disp+10
+           movb #'d',disp+11
+           movb #':',disp+12
+           movb #' ',disp+13
+           movb #' ',disp+14
+           movb #' ',disp+15
+           ;next line
+           movb #'_',disp+16
+           movb #'_',disp+17
+           movb #'_',disp+18
+           movb #'_',disp+19
+           movb #'_',disp+20
+           movb #'_',disp+21
+           movb #'_',disp+22
+           movb #'_',disp+23
+           movb #' ',disp+24
+           movb #' ',disp+25
+           movb #' ',disp+26
+           movb #' ',disp+27
+           movb #' ',disp+28
+           movb #' ',disp+29
+           movb #' ',disp+30
+           movb #' ',disp+31
+           movb #0,disp+32    ;string terminator, acts like '\0'
+		       
+		       ;print the prompt string
+		       LDD   #disp         ;both of these steps are necessary to
+           jsr  display_string ;print to the LCD screen
+
+
+           ;AWAIT KEYPRESS
+           movb   #$FF,await_key_press
+           
+           ;READ EACH CHARACTER
+           MOVB   #$FF,await_key_release     
+           jsr Keypad                  ;read a keypress
+           movb  #'*',disp+16          ;change the display to acknowledge input
+           MOVB  pressed_num,password  ;store the read value into the password
+           LDD   #disp
+           jsr  display_string
+           ;LBRA  Return
+               
+           MOVB   #$FF,await_key_release           
+           jsr Keypad                  ;read a keypress
+           movb  #'*',disp+17          ;change the display to acknowledge input
+           MOVB  pressed_num,password+1  ;store the read value into the password            
+           LDD   #disp
+           jsr  display_string
+           ;LBRA  Return
+           
+           MOVB   #$FF,await_key_release           
+           jsr Keypad                  ;read a keypress
+           movb  #'*',disp+18          ;change the display to acknowledge input
+           MOVB  pressed_num,password+2  ;store the read value into the password
+           LDD   #disp
+           jsr  display_string
+           
+           MOVB   #$FF,await_key_release                      
+           jsr Keypad                  ;read a keypress
+           movb  #'*',disp+19          ;change the display to acknowledge input
+           MOVB  pressed_num,password+3  ;store the read value into the password
+           LDD   #disp
+           jsr  display_string                      
+           
+           MOVB   #$FF,await_key_release
+           jsr Keypad                  ;read a keypress
+           movb  #'*',disp+20          ;change the display to acknowledge input
+           MOVB  pressed_num,password+4  ;store the read value into the password
+           LDD   #disp
+           jsr  display_string
+           
+           MOVB   #$FF,await_key_release           
+           jsr Keypad                  ;read a keypress
+           movb  #'*',disp+21          ;change the display to acknowledge input
+           MOVB  pressed_num,password+5  ;store the read value into the password
+           LDD   #disp
+           jsr  display_string
+           
+           MOVB   #$FF,await_key_release           
+           jsr Keypad                  ;read a keypress
+           movb  #'*',disp+22          ;change the display to acknowledge input
+           MOVB  pressed_num,password+6  ;store the read value into the password 
+           LDD   #disp
+           jsr  display_string             
+           
+           MOVB   #$FF,await_key_release          
+           jsr Keypad                  ;read a keypress
+           movb  #'*',disp+23          ;change the display to acknowledge input
+           MOVB  pressed_num,password+7  ;store the read value into the password
+           LDD   #disp
+           jsr  display_string
+           
+           ;mark the password as set
+           MOVB   #$FF,pw_set
+           LBRA    Return
+
+
+PasswordReset:
+                      ;MOVB   #$FF,
+            
+            
+           ;inital prompt
+           movb #'C',disp
+           movb #'u',disp+1
+           movb #'r',disp+2
+           movb #'r',disp+3
+           movb #'e',disp+4
+           movb #'n',disp+5
+           movb #'t',disp+6
+           movb #' ',disp+7
+           movb #'p',disp+8
+           movb #'a',disp+9
+           movb #'s',disp+10
+           movb #'s',disp+11
+           movb #'w',disp+12
+           movb #'d',disp+13
+           movb #'.',disp+14
+           movb #':',disp+15
+           ;next line
+           movb #'_',disp+16
+           movb #'_',disp+17
+           movb #'_',disp+18
+           movb #'_',disp+19
+           movb #'_',disp+20
+           movb #'_',disp+21
+           movb #'_',disp+22
+           movb #'_',disp+23
+           movb #' ',disp+24
+           movb #' ',disp+25
+           movb #' ',disp+26
+           movb #' ',disp+27
+           movb #' ',disp+28
+           movb #' ',disp+29
+           movb #' ',disp+30
+           movb #' ',disp+31
+           movb #0,disp+32    ;string terminator, acts like '\0'
+		       
+		       ;print the prompt string
+		       LDD   #disp         ;both of these steps are necessary to
+           jsr  display_string ;print to the LCD screen
+
+
+           ;AWAIT KEYPRESS
+           movb   #$FF,await_key_press
+           
+           ;READ EACH CHARACTER
+           MOVB   #$FF,await_key_release     
+           jsr Keypad                  ;read a keypress
+           movb  #'*',disp+16          ;change the display to acknowledge input
+           MOVB  pressed_num,entered_password  ;store the read value into the password
+           LDD   #disp
+           jsr  display_string
+           ;LBRA  Return
+               
+           MOVB   #$FF,await_key_release           
+           jsr Keypad                  ;read a keypress
+           movb  #'*',disp+17          ;change the display to acknowledge input
+           MOVB  pressed_num,entered_password+1  ;store the read value into the password            
+           LDD   #disp
+           jsr  display_string
+           ;LBRA  Return
+           
+           MOVB   #$FF,await_key_release           
+           jsr Keypad                  ;read a keypress
+           movb  #'*',disp+18          ;change the display to acknowledge input
+           MOVB  pressed_num,entered_password+2  ;store the read value into the password
+           LDD   #disp
+           jsr  display_string
+           
+           MOVB   #$FF,await_key_release                      
+           jsr Keypad                  ;read a keypress
+           movb  #'*',disp+19          ;change the display to acknowledge input
+           MOVB  pressed_num,entered_password+3  ;store the read value into the password
+           LDD   #disp
+           jsr  display_string                      
+           
+           MOVB   #$FF,await_key_release
+           jsr Keypad                  ;read a keypress
+           movb  #'*',disp+20          ;change the display to acknowledge input
+           MOVB  pressed_num,entered_password+4  ;store the read value into the password
+           LDD   #disp
+           jsr  display_string
+           
+           MOVB   #$FF,await_key_release           
+           jsr Keypad                  ;read a keypress
+           movb  #'*',disp+21          ;change the display to acknowledge input
+           MOVB  pressed_num,entered_password+5  ;store the read value into the password
+           LDD   #disp
+           jsr  display_string
+           
+           MOVB   #$FF,await_key_release           
+           jsr Keypad                  ;read a keypress
+           movb  #'*',disp+22          ;change the display to acknowledge input
+           MOVB  pressed_num,entered_password+6  ;store the read value into the password 
+           LDD   #disp
+           jsr  display_string             
+           
+           MOVB   #$FF,await_key_release          
+           jsr Keypad                  ;read a keypress
+           movb  #'*',disp+23          ;change the display to acknowledge input
+           MOVB  pressed_num,entered_password+7  ;store the read value into the password
+           LDD   #disp
+           jsr  display_string
+           
+           ;check if the password is correct
+           LDX    #password
+           LDY    #entered_password
+           
+           ;read the current password character and compare it to the new password character
+           ;this resets if the password is incorrect
+           ;1.
+           LDAA   0,X
+           LDAB   0,Y
+           CBA
+           LBNE    PasswordReset
+           
+           INX
+           INY
+           
+           ;2.
+           LDAA   0,X
+           LDAB   0,Y
+           CBA
+           LBNE    PasswordReset
+           
+           INX
+           INY
+           
+           ;3.
+           LDAA   0,X
+           LDAB   0,Y
+           CBA
+           LBNE    PasswordReset
+           
+           INX
+           INY
+           
+           ;4.
+           LDAA   0,X
+           LDAB   0,Y
+           CBA
+           LBNE    PasswordReset
+           
+           INX
+           INY
+           
+           ;5.
+           LDAA   0,X
+           LDAB   0,Y
+           CBA
+           LBNE    PasswordReset
+           
+           INX
+           INY
+           
+           ;6.
+           LDAA   0,X
+           LDAB   0,Y
+           CBA
+           LBNE    PasswordReset
+           
+           INX
+           INY
+           
+           ;7.
+           LDAA   0,X
+           LDAB   0,Y
+           CBA
+           LBNE    PasswordReset
+           
+           INX
+           INY
+           
+           ;8.
+           LDAA   0,X
+           LDAB   0,Y
+           CBA
+           LBNE    PasswordReset
+           
+                      ;inital prompt
+           movb #'N',disp
+           movb #'e',disp+1
+           movb #'w',disp+2
+           movb #' ',disp+3
+           movb #'p',disp+4
+           movb #'a',disp+5
+           movb #'s',disp+6
+           movb #'s',disp+7
+           movb #'w',disp+8
+           movb #'o',disp+9
+           movb #'r',disp+10
+           movb #'d',disp+11
+           movb #':',disp+12
+           movb #' ',disp+13
+           movb #' ',disp+14
+           movb #' ',disp+15
+           ;next line
+           movb #'_',disp+16
+           movb #'_',disp+17
+           movb #'_',disp+18
+           movb #'_',disp+19
+           movb #'_',disp+20
+           movb #'_',disp+21
+           movb #'_',disp+22
+           movb #'_',disp+23
+           movb #' ',disp+24
+           movb #' ',disp+25
+           movb #' ',disp+26
+           movb #' ',disp+27
+           movb #' ',disp+28
+           movb #' ',disp+29
+           movb #' ',disp+30
+           movb #' ',disp+31
+           movb #0,disp+32    ;string terminator, acts like '\0'
+		       
+		       ;print the prompt string
+		       LDD   #disp         ;both of these steps are necessary to
+           jsr  display_string ;print to the LCD screen
+
+
+           ;AWAIT KEYPRESS
+           movb   #$FF,await_key_press
+           
+           ;READ EACH CHARACTER
+           MOVB   #$FF,await_key_release     
+           jsr Keypad                  ;read a keypress
+           movb  #'*',disp+16          ;change the display to acknowledge input
+           MOVB  pressed_num,password  ;store the read value into the password
+           LDD   #disp
+           jsr  display_string
+           ;LBRA  Return
+               
+           MOVB   #$FF,await_key_release           
+           jsr Keypad                  ;read a keypress
+           movb  #'*',disp+17          ;change the display to acknowledge input
+           MOVB  pressed_num,password+1  ;store the read value into the password            
+           LDD   #disp
+           jsr  display_string
+           ;LBRA  Return
+           
+           MOVB   #$FF,await_key_release           
+           jsr Keypad                  ;read a keypress
+           movb  #'*',disp+18          ;change the display to acknowledge input
+           MOVB  pressed_num,password+2  ;store the read value into the password
+           LDD   #disp
+           jsr  display_string
+           
+           MOVB   #$FF,await_key_release                      
+           jsr Keypad                  ;read a keypress
+           movb  #'*',disp+19          ;change the display to acknowledge input
+           MOVB  pressed_num,password+3  ;store the read value into the password
+           LDD   #disp
+           jsr  display_string                      
+           
+           MOVB   #$FF,await_key_release
+           jsr Keypad                  ;read a keypress
+           movb  #'*',disp+20          ;change the display to acknowledge input
+           MOVB  pressed_num,password+4  ;store the read value into the password
+           LDD   #disp
+           jsr  display_string
+           
+           MOVB   #$FF,await_key_release           
+           jsr Keypad                  ;read a keypress
+           movb  #'*',disp+21          ;change the display to acknowledge input
+           MOVB  pressed_num,password+5  ;store the read value into the password
+           LDD   #disp
+           jsr  display_string
+           
+           MOVB   #$FF,await_key_release           
+           jsr Keypad                  ;read a keypress
+           movb  #'*',disp+22          ;change the display to acknowledge input
+           MOVB  pressed_num,password+6  ;store the read value into the password 
+           LDD   #disp
+           jsr  display_string             
+           
+           MOVB   #$FF,await_key_release          
+           jsr Keypad                  ;read a keypress
+           movb  #'*',disp+23          ;change the display to acknowledge input
+           MOVB  pressed_num,password+7  ;store the read value into the password
+           LDD   #disp
+           jsr  display_string
+           
+           ;password has been reset
+           MOVB  #$00,pw_reset
+
+           LBRA    Return
+
+PasswordCheck:
+                      ;MOVB   #$FF,
+            
+            
+           ;inital prompt
+           movb #'E',disp
+           movb #'n',disp+1
+           movb #'t',disp+2
+           movb #'e',disp+3
+           movb #'r',disp+4
+           movb #' ',disp+5
+           movb #'p',disp+6
+           movb #'a',disp+7
+           movb #'s',disp+8
+           movb #'s',disp+9
+           movb #'w',disp+10
+           movb #'o',disp+11
+           movb #'r',disp+12
+           movb #'d',disp+13
+           movb #':',disp+14
+           movb #' ',disp+15
+           ;next line
+           movb #'_',disp+16
+           movb #'_',disp+17
+           movb #'_',disp+18
+           movb #'_',disp+19
+           movb #'_',disp+20
+           movb #'_',disp+21
+           movb #'_',disp+22
+           movb #'_',disp+23
+           movb #' ',disp+24
+           movb #' ',disp+25
+           movb #' ',disp+26
+           movb #' ',disp+27
+           movb #' ',disp+28
+           movb #' ',disp+29
+           movb #' ',disp+30
+           movb #' ',disp+31
+           movb #0,disp+32    ;string terminator, acts like '\0'
+		       
+		       ;print the prompt string
+		       LDD   #disp         ;both of these steps are necessary to
+           jsr  display_string ;print to the LCD screen
+
+
+           ;AWAIT KEYPRESS
+           movb   #$FF,await_key_press
+           
+           ;READ EACH CHARACTER
+           MOVB   #$FF,await_key_release     
+           jsr Keypad                  ;read a keypress
+           movb  #'*',disp+16          ;change the display to acknowledge input
+           MOVB  pressed_num,entered_password  ;store the read value into the password
+           LDD   #disp
+           jsr  display_string
+           ;LBRA  Return
+               
+           MOVB   #$FF,await_key_release           
+           jsr Keypad                  ;read a keypress
+           movb  #'*',disp+17          ;change the display to acknowledge input
+           MOVB  pressed_num,entered_password+1  ;store the read value into the password            
+           LDD   #disp
+           jsr  display_string
+           ;LBRA  Return
+           
+           MOVB   #$FF,await_key_release           
+           jsr Keypad                  ;read a keypress
+           movb  #'*',disp+18          ;change the display to acknowledge input
+           MOVB  pressed_num,entered_password+2  ;store the read value into the password
+           LDD   #disp
+           jsr  display_string
+           
+           MOVB   #$FF,await_key_release                      
+           jsr Keypad                  ;read a keypress
+           movb  #'*',disp+19          ;change the display to acknowledge input
+           MOVB  pressed_num,entered_password+3  ;store the read value into the password
+           LDD   #disp
+           jsr  display_string                      
+           
+           MOVB   #$FF,await_key_release
+           jsr Keypad                  ;read a keypress
+           movb  #'*',disp+20          ;change the display to acknowledge input
+           MOVB  pressed_num,entered_password+4  ;store the read value into the password
+           LDD   #disp
+           jsr  display_string
+           
+           MOVB   #$FF,await_key_release           
+           jsr Keypad                  ;read a keypress
+           movb  #'*',disp+21          ;change the display to acknowledge input
+           MOVB  pressed_num,entered_password+5  ;store the read value into the password
+           LDD   #disp
+           jsr  display_string
+           
+           MOVB   #$FF,await_key_release           
+           jsr Keypad                  ;read a keypress
+           movb  #'*',disp+22          ;change the display to acknowledge input
+           MOVB  pressed_num,entered_password+6  ;store the read value into the password 
+           LDD   #disp
+           jsr  display_string             
+           
+           MOVB   #$FF,await_key_release          
+           jsr Keypad                  ;read a keypress
+           movb  #'*',disp+23          ;change the display to acknowledge input
+           MOVB  pressed_num,entered_password+7  ;store the read value into the password
+           LDD   #disp
+           jsr  display_string
+           
+           ;check if the password is correct
+           LDX    #password
+           LDY    #entered_password
+           
+           ;read the current password character and compare it to the new password character
+           ;this resets if the password is incorrect
+           ;1.
+           LDAA   0,X
+           LDAB   0,Y
+           CBA
+           LBNE    PasswordCheck
+           
+           INX
+           INY
+           
+           ;2.
+           LDAA   0,X
+           LDAB   0,Y
+           CBA
+           LBNE    PasswordCheck
+           
+           INX
+           INY
+           
+           ;3.
+           LDAA   0,X
+           LDAB   0,Y
+           CBA
+           LBNE    PasswordCheck
+           
+           INX
+           INY
+           
+           ;4.
+           LDAA   0,X
+           LDAB   0,Y
+           CBA
+           LBNE    PasswordCheck
+           
+           INX
+           INY
+           
+           ;5.
+           LDAA   0,X
+           LDAB   0,Y
+           CBA
+           LBNE    PasswordCheck
+           
+           INX
+           INY
+           
+           ;6.
+           LDAA   0,X
+           LDAB   0,Y
+           CBA
+           LBNE    PasswordCheck
+           
+           INX
+           INY
+           
+           ;7.
+           LDAA   0,X
+           LDAB   0,Y
+           CBA
+           LBNE    PasswordCheck
+           
+           INX
+           INY
+           
+           ;8.
+           LDAA   0,X
+           LDAB   0,Y
+           CBA
+           LBNE    PasswordCheck
+           
+           CLR    pw_required
+           
+           BRA    Return           
+            
+Return:    
+            ;here, set the pressed number to something impossible so that
+            ;the password input doesn't spill into other code
+            MOVB  #$FF,pressed_num    ;set the pressed_num to something impossible
+            ;restore registers and accumulators
+            PULY
+            PULX
+            PULD
+            PULB
+            PULA
+            
+            RTS

Final_Project/bin/wall.dbg

@@ -0,0 +1,233 @@
+	XDEF	Wall
+	XREF	__SEG_END_SSTACK,display_time,display_string,disp
+  ;counters and variables
+  XREF  current_year,current_month,current_day,current_hour,current_minute,current_second
+  
+	;events
+	XREF  second_passed
+	
+	;debug
+	XREF  byte_out,word_out
+	
+clock_digits: Section
+;digits to display
+seconds_tens  ds.b  1
+seconds_ones  ds.b  1
+minutes_tens  ds.b  1
+minutes_ones  ds.b  1
+hours_tens    ds.b  1
+hours_ones    ds.b  1
+
+clock_code:   Section	
+Wall: ;push register and accumulator values for retention                   
+            PSHA
+            PSHB
+            PSHD
+            PSHX
+            PSHY
+            
+            ;handle the event that fires evey second
+            LDAA  second_passed
+            CMPA  #$FF
+            LBNE   PrintWall       ;display time between seconds
+            
+            ;if a second has passed
+            LDAA  current_second
+            INCA                  ;increment the seconds counter
+            STAA  current_second
+            CMPA  #60             ;less than a minute has passed
+            LBLT   PrintWall       ;display the time if required
+            CLR   current_second  ;resest the seconds counter to zero
+            
+            ;one minute has passed
+            LDAA  current_minute
+            INCA
+            STAA  current_minute
+            CMPA  #60
+            LBLT   PrintWall
+            CLR   current_minute
+            
+            ;one hour has passed
+            LDAA  current_hour
+            INCA
+            STAA  current_hour
+            CMPA  #24
+            LBLT   PrintWall
+            CLR   current_hour
+            
+            ;one day has passed (30 days in a month)
+            LDAA  current_day
+            INCA  
+            STAA  current_day
+            CMPA  #30
+            LBLT   PrintWall
+            MOVB  #$01,current_day
+            
+            ;one month has passed
+            LDAA  current_month
+            INCA
+            STAA  current_month
+            CMPA  #12
+            LBLT   PrintWall
+            MOVB  #$01,current_month
+            
+            ;one year has passed
+            LDX   current_year
+            INX
+            STX  current_year
+            ;no need to do anything else, years counts up indefinitely
+            
+SetWall:
+           movb #'M',disp
+           movb #'M',disp+1
+           movb #'/',disp+2
+           movb #'D',disp+3
+           movb #'D',disp+4
+           movb #'/',disp+5
+           movb #'Y',disp+6
+           movb #'Y',disp+7
+           movb #'Y',disp+8
+           movb #'Y',disp+9
+           movb #' ',disp+10
+           movb #'h',disp+11
+           movb #'h',disp+12
+           movb #':',disp+13
+           movb #'m',disp+14
+           movb #'m',disp+15
+           ;
+           ;next line
+           ;
+           movb #'_',disp+16
+           movb #'_',disp+17
+           movb #'/',disp+18
+           movb #'_',disp+19                                                                                                      
+           movb #'_',disp+20
+           movb #'/',disp+21
+           movb #'_',disp+22
+           movb #'_',disp+23
+           movb #'_',disp+24
+           movb #'_',disp+25
+           movb #' ',disp+26
+           movb #'_',disp+27
+           movb #'_',disp+28
+           movb #':',disp+29
+           
+           movb #'_',disp+30
+           movb #'_',disp+31
+           movb #0,disp+32    ;string terminator, acts like '\0'
+            
+            
+PrintWall: 
+
+           ;check if the time should show
+           LDAA  display_time
+           CMPA  #$00
+           LBEQ  Return
+           
+           ;if the time should show, calculate the ASCII values
+           ; (seconds)
+           LDX    #10		          ;load the bottom part of the divide (forget what it's called)
+           LDD    current_second  ;two-digit seconds number
+           IDIV                   ;D / X -> X (remainder D) (D has the one's place and X has the 10's)
+           
+           ADDD   #$30            ;convert the one's place to ascii
+           STAB   seconds_ones
+           XGDX
+           ADDD   #$30
+           STAB   seconds_tens
+           
+           ;from lab 6.3
+           ;XGDX                   ;X <-> D, X will now have the 1's and D has the 10's
+           ;ADDD   #$30            ;convert to ASCII
+           ;STAB   seconds_tens    ;lower byte of d has the 10's place for the seconds
+           ;STAB   word_out
+           ;XGDX                   ;swap back X and D (X still has the 1's)
+           ;ADDD   #$30            ;conver the ones place to ASCII
+           ;STAB   seconds_ones    ;X has the remainer, i.e. the one's place
+           ;STAB   byte_out
+           
+           ;STAB   byte_out
+           ;STX    word_out 
+           
+           ; (minutes)
+           ;LDX    #10		          ;load the bottom part of the divide (forget what it's called)
+           ;LDD    current_minute  ;two-digit minutes number
+           ;IDIV                   ;D / X -> X (remainder D)
+           ;XGDX                   ;X <-> D, X now has remainder and D has quotient
+           ;ADDD   #$30            ;convert to ASCII
+           ;STAB   minutes_tens     ;lower byte of d has the 10's place for the seconds
+           ;STX    minutes_ones    ;X has the remainer, i.e. the one's place 
+           
+           ;print the time and date (includes placeholders)
+           movb #'D',disp
+           movb #'a',disp+1
+           movb #'t',disp+2
+           movb #'e',disp+3
+           movb #':',disp+4
+           movb #' ',disp+5
+           ;month
+           movb #'1',disp+6
+           movb #'2',disp+7
+           movb #'/',disp+8
+           ;day
+           movb #'0',disp+9
+           movb #'2',disp+10
+           movb #'/',disp+11
+           ;year
+           movb #'1',disp+12
+           movb #'9',disp+13
+           movb #'9',disp+14
+           movb #'3',disp+15
+           ;
+           ;next line
+           ;
+           movb #'T',disp+16
+           movb #'i',disp+17
+           movb #'m',disp+18
+           movb #'e',disp+19                                                                                                      
+           movb #':',disp+20
+           movb #' ',disp+21
+           
+           ;hour
+           movb #'1',disp+22
+           movb #'1',disp+23
+           
+           movb #':',disp+24
+           ;minute
+           movb #'1',disp+25
+           movb #'1',disp+26
+           
+           movb #':',disp+27
+           ;seconds
+           ;movb #'1',disp+28
+           ;movb #'8',disp+29
+           
+           movb #' ',disp+30
+           movb #' ',disp+31
+           movb #0,disp+32    ;string terminator, acts like '\0'
+           
+           ;store out calculated ascii values in the appropriate places in the display
+           MOVB   seconds_tens,disp+28
+           MOVB   seconds_ones,disp+29
+           
+           ;MOVB   minutes_tens,disp+25
+           ;MOVB   minutes_ones,disp+26
+           
+           LDD   #disp         ;both of these steps are necessary to
+           jsr  display_string ;print to the LCD screen          
+
+Return:     
+            ;clear the flag that is set evey second
+            CLR   second_passed
+            
+            ;restore registers and accumulators
+            PULY
+            PULX
+            PULD
+            PULB
+            PULA
+            
+            RTS
+   
+	
+	

Final_Project/bin/water.dbg

@@ -0,0 +1,98 @@
+  XDEF	Water
+	XREF	__SEG_END_SSTACK,grow_lights,PORT_T,display_string,disp,is_watering,PORT_S,PORT_P,sprinkler_event,word_out,SPRINKLER_ARR,byte_out,sprinkler_arr_i
+
+
+Constants:	     Section
+;STEP_ARR   	dc.b  $0A,$12,$14,$0C,$0 ;array sequence to spin motor
+ARRAY_LENGTH  dc.b  $04
+Variables:        Section
+	
+	
+Water:      ;push register and accumulator values for retention                   
+            PSHA
+            PSHB
+            PSHD
+            PSHX
+            PSHY
+
+            ;get out of here if we should not be watering (don't do anything with sprinkler) or the display
+            LDAB  is_watering
+            CMPB  #$FF
+            LBNE  Return
+            
+            ;sprinkler stuff
+            LDAB    sprinkler_event   ;check the event flag
+            CMPB    #$FF              ;all 1's indicates that the event has fired, if it's not equal, show watering
+            LBNE    ShowWatering      ;still display the watering... message
+            
+            ;handle sprinkle event
+            LDAB    sprinkler_arr_i       ;check which array position we are at
+            INCB                      ;go to next index
+            STAB    sprinkler_arr_i       ; ^
+            CMPB    #8                ;check if we have reached the end of the array
+            BLT     Continue          ;continue if not at the end of the array
+            MOVB    #$00,sprinkler_arr_i  ;reset the array index to the beginning
+            LDAB    #$00
+Continue:   
+            LDX     #SPRINKLER_ARR
+            ABX
+            STX     word_out         
+            LDAA    0,X
+            STAA    PORT_P
+            STAB    byte_out
+            
+            
+            CLR       sprinkler_event
+            
+                                      ;...
+ShowWatering:
+          ;print the temperature
+           movb #'W',disp
+           movb #'a',disp+1
+           movb #'t',disp+2
+           movb #'e',disp+3
+           movb #'r',disp+4
+           movb #'i',disp+5
+           movb #'n',disp+6
+           movb #'g',disp+7
+           movb #'.',disp+8
+           movb #'.',disp+9
+           movb #'.',disp+10
+           movb #' ',disp+11
+           movb #' ',disp+12
+           movb #' ',disp+13
+           movb #' ',disp+14
+           movb #' ',disp+15
+           ;next line
+           movb #' ',disp+16
+           movb #' ',disp+17
+           movb #' ',disp+18
+           movb #' ',disp+19
+           movb #' ',disp+20
+           movb #' ',disp+21
+           movb #' ',disp+22
+           movb #' ',disp+23
+           movb #' ',disp+24
+           movb #' ',disp+25
+           movb #' ',disp+26
+           movb #' ',disp+27
+           movb #' ',disp+28
+           movb #' ',disp+29
+           movb #' ',disp+30
+           movb #' ',disp+31
+           movb #0,disp+32    ;string terminator, acts like '\0'
+           
+           LDD  #disp         ;both of these steps are necessary to
+           jsr  display_string ;print to the LCD screen           
+    
+Return:     ;restore registers and accumulators
+            PULY
+            PULX
+            PULD
+            PULB
+            PULA
+            
+            RTS
+   
+	
+	

Final_Project/cmd/Full_Chip_Simulation_Postload.cmd

@@ -0,0 +1 @@
+// After load the commands written below will be executed

Final_Project/cmd/Full_Chip_Simulation_Preload.cmd

@@ -0,0 +1 @@
+// Before load the commands written below will be executed

Final_Project/cmd/Full_Chip_Simulation_Reset.cmd

@@ -0,0 +1 @@
+// After reset the commands written below will be executed

Final_Project/cmd/Full_Chip_Simulation_SetCPU.cmd

@@ -0,0 +1 @@
+// At startup the commands written below will be executed

Final_Project/cmd/Full_Chip_Simulation_Startup.cmd

@@ -0,0 +1 @@
+// At startup the commands written below will be executed

Final_Project/cmd/P&E_Multilink_CyclonePro_Erase_unsecure_hcs12.cmd

@@ -0,0 +1,78 @@
+// ver 1.1 (7/7/04)
+// HCS12X Core erasing + unsecuring command file:
+// These commands mass erase the chip then program the security byte to 0xFE (unsecured state).
+
+// Evaluate the clock divider to set in ECLKDIV/FCLKDIV registers:
+
+DEFINEVALUEDLG "Information required to unsecure the device" "CLKDIV" 0x49 "To unsecure the device, the command script needs \nthe correct value for ECLKDIV/FCLKDIV onchip\nregisters.\nIf the bus frequency is less than 10 MHz, the value\nto store in ECLKDIV/FCLKDIV is equal to:\n \"bus frequency (kHz) / 175\"\n\nIf the bus frequency is higher than 10 MHz, the value\nto store in ECLKDIV/FCLKDIV is equal to:\n \" bus frequency (kHz) / 1400  + 64\"\n(+64 (0x40) is to set PRDIV8 flag)\n\nDatasheet proposed values:\n\nbus frequency\t\tE/FCLKDIV value (decimal)\n\n 16 \tMHz\t\t73\n  8 \tMHz\t\t39\n  4 \tMHz\t\t19\n  2 \tMHz\t\t9\n  1 \tMHz\t\t4\n"
+
+// An average programming clock of 175 kHz is chosen.
+
+// If the oscillator frequency is less than 10 MHz, the value to store
+// in ECLKDIV/FCLKDIV is equal to " oscillator frequency (kHz) / 175 ".
+
+// If the oscillator frequency is higher than 10 MHz, the value to store
+// in ECLKDIV/FCLKDIV is equal to " oscillator frequency (kHz) / 1400  + 0x40 (to set PRDIV8 flag)".
+
+// Datasheet proposed values:
+//
+// oscillator frequency     ECLKDIV/FCLKDIV value (hexadecimal)
+// 
+//  16 MHz            		$49
+//   8 MHz            		$27
+//   4 MHz            		$13
+//   2 MHz             		$9
+//   1 MHz             		$4
+
+
+FLASH RELEASE   // do not interact with regular flash programming monitor
+
+//mass erase flash
+reset
+wb 0x03c 0x00	 //disable cop
+wait 20
+wb 0x100 CLKDIV  // set FCLKDIV clock divider
+wb 0x104 0xFF    // FPROT all protection disabled
+wb 0x105 0x30    // clear PVIOL and ACCERR in FSTAT register 
+wb 0x102 0x00    // clear the WRALL bit in FTSTMOD
+wb 0x105 0x02
+wb 0x102 0x10    // set the WRALL bit in FTSTMOD to affect all blocks
+ww 0x108 0xFFFE
+ww 0x10A 0xFFFF
+wb 0x106 0x41    // write MASS ERASE command in FCMD register
+wb 0x105 0x80    // clear CBEIF in FSTAT register to execute the command 
+wait 20          // wait for command to complete
+
+//mass erase eeprom
+wb 0x110 CLKDIV  // set ECLKDV clock divider 
+wb 0x114 0xFF    // EPROT all protection disabled
+wb 0x115 0x30    // clear PVIOL and ACCERR in ESTAT register 
+wb 0x112 0x00    // clear the WRALL bit in FTSTMOD
+wb 0x115 0x02
+ww 0x118 0x0C00  // write to EADDR eeprom address register
+ww 0x11A 0x0000  // write to EDATA eeprom data register
+wb 0x116 0x41    // write MASS ERASE command in ECMD register
+wb 0x115 0x80    // clear CBEIF in ESTAT register to execute the command
+wait 20          // wait for command to complete
+
+//reprogram Security byte to Unsecure state
+reset
+wb 0x03c 0x00	//disable cop
+wait 20
+wb 0x102 0x00    // clear the WRALL bit in FTSTMOD
+wb 0x105 0x02
+wb 0x100 CLKDIV  // set FCLKDIV clock divider
+wb 0x100 CLKDIV  // set FCLKDIV clock divider
+wb 0x104 0xFF    // FPROT all protection disabled
+wb 0x105 0x30    // clear PVIOL and ACCERR in FSTAT register 
+wb 0x102 0x00    // clear the WRALL bit in FTSTMOD
+wb 0x105 0x02
+ww 0xFF0E 0xFFFE // write security byte to "Unsecured" state
+wb 0x106 0x20    // write MEMORY PROGRAM command in FCMD register
+wb 0x105 0x80    // clear CBEIF in FSTAT register to execute the command 
+wait 20          // wait for command to complete
+
+reset
+
+undef CLKDIV     // undefine variable 
+

Final_Project/cmd/P&E_Multilink_CyclonePro_Postload.cmd

@@ -0,0 +1 @@
+// After load the commands written below will be executed

Final_Project/cmd/P&E_Multilink_CyclonePro_Preload.cmd

@@ -0,0 +1 @@
+// Before load the commands written below will be executed

Final_Project/cmd/P&E_Multilink_CyclonePro_Reset.cmd

@@ -0,0 +1 @@
+// After reset the commands written below will be executed

Final_Project/cmd/P&E_Multilink_CyclonePro_Startup.cmd

@@ -0,0 +1 @@
+// At startup the commands written below will be executed

Final_Project/cmd/P&E_Multilink_CyclonePro_Vppoff.cmd

@@ -0,0 +1 @@
+// After programming the flash, the commands written below will be executed

Final_Project/cmd/P&E_Multilink_CyclonePro_Vppon.cmd

@@ -0,0 +1 @@
+// Before programming the flash, the commands written below will be executed

Final_Project/cmd/P&E_Multilink_USB_Erase_unsecure_hcs12.cmd

@@ -0,0 +1,78 @@
+// ver 1.1 (7/7/04)
+// HCS12X Core erasing + unsecuring command file:
+// These commands mass erase the chip then program the security byte to 0xFE (unsecured state).
+
+// Evaluate the clock divider to set in ECLKDIV/FCLKDIV registers:
+
+DEFINEVALUEDLG "Information required to unsecure the device" "CLKDIV" 0x49 "To unsecure the device, the command script needs \nthe correct value for ECLKDIV/FCLKDIV onchip\nregisters.\nIf the bus frequency is less than 10 MHz, the value\nto store in ECLKDIV/FCLKDIV is equal to:\n \"bus frequency (kHz) / 175\"\n\nIf the bus frequency is higher than 10 MHz, the value\nto store in ECLKDIV/FCLKDIV is equal to:\n \" bus frequency (kHz) / 1400  + 64\"\n(+64 (0x40) is to set PRDIV8 flag)\n\nDatasheet proposed values:\n\nbus frequency\t\tE/FCLKDIV value (decimal)\n\n 16 \tMHz\t\t73\n  8 \tMHz\t\t39\n  4 \tMHz\t\t19\n  2 \tMHz\t\t9\n  1 \tMHz\t\t4\n"
+
+// An average programming clock of 175 kHz is chosen.
+
+// If the oscillator frequency is less than 10 MHz, the value to store
+// in ECLKDIV/FCLKDIV is equal to " oscillator frequency (kHz) / 175 ".
+
+// If the oscillator frequency is higher than 10 MHz, the value to store
+// in ECLKDIV/FCLKDIV is equal to " oscillator frequency (kHz) / 1400  + 0x40 (to set PRDIV8 flag)".
+
+// Datasheet proposed values:
+//
+// oscillator frequency     ECLKDIV/FCLKDIV value (hexadecimal)
+// 
+//  16 MHz            		$49
+//   8 MHz            		$27
+//   4 MHz            		$13
+//   2 MHz             		$9
+//   1 MHz             		$4
+
+
+FLASH RELEASE   // do not interact with regular flash programming monitor
+
+//mass erase flash
+reset
+wb 0x03c 0x00	 //disable cop
+wait 20
+wb 0x100 CLKDIV  // set FCLKDIV clock divider
+wb 0x104 0xFF    // FPROT all protection disabled
+wb 0x105 0x30    // clear PVIOL and ACCERR in FSTAT register 
+wb 0x102 0x00    // clear the WRALL bit in FTSTMOD
+wb 0x105 0x02
+wb 0x102 0x10    // set the WRALL bit in FTSTMOD to affect all blocks
+ww 0x108 0xFFFE
+ww 0x10A 0xFFFF
+wb 0x106 0x41    // write MASS ERASE command in FCMD register
+wb 0x105 0x80    // clear CBEIF in FSTAT register to execute the command 
+wait 20          // wait for command to complete
+
+//mass erase eeprom
+wb 0x110 CLKDIV  // set ECLKDV clock divider 
+wb 0x114 0xFF    // EPROT all protection disabled
+wb 0x115 0x30    // clear PVIOL and ACCERR in ESTAT register 
+wb 0x112 0x00    // clear the WRALL bit in FTSTMOD
+wb 0x115 0x02
+ww 0x118 0x0C00  // write to EADDR eeprom address register
+ww 0x11A 0x0000  // write to EDATA eeprom data register
+wb 0x116 0x41    // write MASS ERASE command in ECMD register
+wb 0x115 0x80    // clear CBEIF in ESTAT register to execute the command
+wait 20          // wait for command to complete
+
+//reprogram Security byte to Unsecure state
+reset
+wb 0x03c 0x00	//disable cop
+wait 20
+wb 0x102 0x00    // clear the WRALL bit in FTSTMOD
+wb 0x105 0x02
+wb 0x100 CLKDIV  // set FCLKDIV clock divider
+wb 0x100 CLKDIV  // set FCLKDIV clock divider
+wb 0x104 0xFF    // FPROT all protection disabled
+wb 0x105 0x30    // clear PVIOL and ACCERR in FSTAT register 
+wb 0x102 0x00    // clear the WRALL bit in FTSTMOD
+wb 0x105 0x02
+ww 0xFF0E 0xFFFE // write security byte to "Unsecured" state
+wb 0x106 0x20    // write MEMORY PROGRAM command in FCMD register
+wb 0x105 0x80    // clear CBEIF in FSTAT register to execute the command 
+wait 20          // wait for command to complete
+
+reset
+
+undef CLKDIV     // undefine variable 
+

Final_Project/cmd/P&E_Multilink_USB_Postload.cmd

@@ -0,0 +1 @@
+// After load the commands written below will be executed

Final_Project/cmd/P&E_Multilink_USB_Preload.cmd

@@ -0,0 +1 @@
+// Before load the commands written below will be executed

Final_Project/cmd/P&E_Multilink_USB_Reset.cmd

@@ -0,0 +1 @@
+// After reset the commands written below will be executed

Final_Project/cmd/P&E_Multilink_USB_Startup.cmd

@@ -0,0 +1 @@
+// At startup the commands written below will be executed

Final_Project/cmd/P&E_Multilink_USB_Vppoff.cmd

@@ -0,0 +1 @@
+// After programming the flash, the commands written below will be executed

Final_Project/cmd/P&E_Multilink_USB_Vppon.cmd

@@ -0,0 +1 @@
+// Before programming the flash, the commands written below will be executed

Final_Project/prm/Project.prm

@@ -0,0 +1,65 @@
+/* This is a linker parameter file for the MC9S12E128 */
+NAMES END /* CodeWarrior will pass all the needed files to the linker by command line. But here you may add your own files too. */
+
+SEGMENTS  /* Here all RAM/ROM areas of the device are listed. Used in PLACEMENT below. */
+
+/* Register space  */
+/*    IO_SEG        = PAGED         0x0000 TO   0x03FF; intentionally not defined */
+
+/* RAM */
+      RAM           = READ_WRITE    0x0400 TO   0x1FFF;
+
+/* non-paged FLASHs */
+      ROM_4000      = READ_ONLY     0x4000 TO   0x7FFF;
+      ROM_C000      = READ_ONLY     0xC000 TO   0xFEFF;
+ /*   VECTORS       = READ_ONLY     0xFF00 TO   0xFFFF; intentionally not defined: used for VECTOR commands below */
+   //OSVECTORS      = READ_ONLY     0xFF8C TO   0xFFFF;   /* OSEK interrupt vectors (use your vector.o) */
+
+/* paged FLASH:                     0x8000 TO   0xBFFF; addressed through PPAGE */
+      PAGE_38       = READ_ONLY   0x388000 TO 0x38BFFF;
+      PAGE_39       = READ_ONLY   0x398000 TO 0x39BFFF;
+      PAGE_3A       = READ_ONLY   0x3A8000 TO 0x3ABFFF;
+      PAGE_3B       = READ_ONLY   0x3B8000 TO 0x3BBFFF;
+      PAGE_3C       = READ_ONLY   0x3C8000 TO 0x3CBFFF;
+      PAGE_3D       = READ_ONLY   0x3D8000 TO 0x3DBFFF;
+/*    PAGE_3E       = READ_ONLY   0x3E8000 TO 0x3EBFFF; not used: equivalent to ROM_4000 */
+/*    PAGE_3F       = READ_ONLY   0x3F8000 TO 0x3FBEFF; not used: equivalent to ROM_C000 */
+END
+
+PLACEMENT /* here all predefined and user segments are placed into the SEGMENTS defined above. */
+      _PRESTART,              /* Used in HIWARE format: jump to _Startup at the code start */
+      STARTUP,                /* startup data structures */
+      ROM_VAR,                /* constant variables */
+      STRINGS,                /* string literals */
+      VIRTUAL_TABLE_SEGMENT,  /* C++ virtual table segment */
+    //.ostext,                /* OSEK */
+      DEFAULT_ROM, NON_BANKED,             /* runtime routines which must not be banked */
+      COPY                    /* copy down information: how to initialize variables */
+                              /* in case you want to use ROM_4000 here as well, make sure
+                                 that all files (incl. library files) are compiled with the
+                                 option: -OnB=b */
+                        INTO  ROM_C000/*, ROM_4000*/;
+
+      OTHER_ROM         INTO  PAGE_38, PAGE_39, PAGE_3A, PAGE_3B, PAGE_3C, PAGE_3D                  ;
+
+    //.stackstart,            /* eventually used for OSEK kernel awareness: Main-Stack Start */
+      SSTACK,                 /* allocate stack first to avoid overwriting variables on overflow */
+    //.stackend,              /* eventually used for OSEK kernel awareness: Main-Stack End */
+    DEFAULT_RAM         INTO  RAM;
+
+  //.vectors            INTO  OSVECTORS; /* OSEK */
+END
+
+ENTRIES /* keep the following unreferenced variables */
+    /* OSEK: always allocate the vector table and all dependent objects */
+  //_vectab OsBuildNumber _OsOrtiStackStart _OsOrtiStart
+END
+
+STACKSIZE 0x100
+
+VECTOR 0 _Startup /* reset vector: this is the default entry point for a C/C++ application. */
+VECTOR 6 IRQ_ISR
+VECTOR 7 RTI_ISR
+//VECTOR 0 Entry  /* reset vector: this is the default entry point for an Assembly application. */
+//INIT Entry      /* for assembly applications: that this is as well the initialization entry point */
+

Final_Project/prm/burner.bbl

@@ -0,0 +1,157 @@
+/* logical s-record file */
+OPENFILE "%ABS_FILE%.s19"
+format=motorola
+busWidth=1
+origin=0
+len=0x1000000
+destination=0
+SRECORD=Sx
+SENDBYTE 1 "%ABS_FILE%"
+CLOSE
+
+
+/* physical s-record file */
+OPENFILE "%ABS_FILE%.phy"
+format = motorola
+busWidth = 1
+len = 0x4000
+
+/* logical non banked flash at $4000 and $C000 to physical */
+origin = 0x004000
+destination = 0x0F8000
+SENDBYTE 1 "%ABS_FILE%"
+
+origin = 0x00C000
+destination = 0x0FC000
+SENDBYTE 1 "%ABS_FILE%"
+
+/* physical FTS512K flash window to physical 
+origin = 0x008000
+destination = 0x080000 
+SENDBYTE 1 "%ABS_FILE%"
+*/
+
+/* physical FTS256K parts flash window to physical 
+origin = 0x008000
+destination = 0x0C0000 
+SENDBYTE 1 "%ABS_FILE%"
+*/
+
+/* physical FTS128K parts flash window to physical 
+origin = 0x008000
+destination = 0x0E0000 
+SENDBYTE 1 "%ABS_FILE%"
+*/
+
+/* physical FTS64K parts flash window to physical 
+origin = 0x008000
+destination = 0x0F0000 
+SENDBYTE 1 "%ABS_FILE%"
+*/
+
+/* physical FTS32K parts flash window to physical 
+origin = 0x008000
+destination = 0x0F8000 
+SENDBYTE 1 "%ABS_FILE%"
+*/
+
+/* logical 512 kB banked flash to physical */
+origin = 0x208000
+destination = 0x080000
+SENDBYTE 1 "%ABS_FILE%"
+origin = 0x218000
+destination = 0x084000
+SENDBYTE 1 "%ABS_FILE%"
+origin = 0x228000
+destination = 0x088000
+SENDBYTE 1 "%ABS_FILE%"
+origin = 0x238000
+destination = 0x08C000
+SENDBYTE 1 "%ABS_FILE%"
+origin = 0x248000
+destination = 0x090000
+SENDBYTE 1 "%ABS_FILE%"
+origin = 0x258000
+destination = 0x094000
+SENDBYTE 1 "%ABS_FILE%"
+origin = 0x268000
+destination = 0x098000
+SENDBYTE 1 "%ABS_FILE%"
+origin = 0x278000
+destination = 0x09C000
+SENDBYTE 1 "%ABS_FILE%"
+origin = 0x288000
+destination = 0x0A0000
+SENDBYTE 1 "%ABS_FILE%"
+origin = 0x298000
+destination = 0x0A4000
+SENDBYTE 1 "%ABS_FILE%"
+origin = 0x2A8000
+destination = 0x0A8000
+SENDBYTE 1 "%ABS_FILE%"
+origin = 0x2B8000
+destination = 0x0AC000
+SENDBYTE 1 "%ABS_FILE%"
+origin = 0x2C8000
+destination = 0x0B0000
+SENDBYTE 1 "%ABS_FILE%"
+origin = 0x2D8000
+destination = 0x0B4000
+SENDBYTE 1 "%ABS_FILE%"
+origin = 0x2E8000
+destination = 0x0B8000
+SENDBYTE 1 "%ABS_FILE%"
+origin = 0x2F8000
+destination = 0x0BC000
+SENDBYTE 1 "%ABS_FILE%"
+origin = 0x308000
+destination = 0x0C0000
+SENDBYTE 1 "%ABS_FILE%"
+origin = 0x318000
+destination = 0x0C4000
+SENDBYTE 1 "%ABS_FILE%"
+origin = 0x328000
+destination = 0x0C8000
+SENDBYTE 1 "%ABS_FILE%"
+origin = 0x338000
+destination = 0x0CC000
+SENDBYTE 1 "%ABS_FILE%"
+origin = 0x348000
+destination = 0x0D0000
+SENDBYTE 1 "%ABS_FILE%"
+origin = 0x358000
+destination = 0x0D4000
+SENDBYTE 1 "%ABS_FILE%"
+origin = 0x368000
+destination = 0x0D8000
+SENDBYTE 1 "%ABS_FILE%"
+origin = 0x378000
+destination = 0x0DC000
+SENDBYTE 1 "%ABS_FILE%"
+origin = 0x388000
+destination = 0x0E0000
+SENDBYTE 1 "%ABS_FILE%"
+origin = 0x398000
+destination = 0x0E4000
+SENDBYTE 1 "%ABS_FILE%"
+origin = 0x3A8000
+destination = 0x0E8000
+SENDBYTE 1 "%ABS_FILE%"
+origin = 0x3B8000
+destination = 0x0EC000
+SENDBYTE 1 "%ABS_FILE%"
+origin = 0x3C8000
+destination = 0x0F0000
+SENDBYTE 1 "%ABS_FILE%"
+origin = 0x3D8000
+destination = 0x0F4000
+SENDBYTE 1 "%ABS_FILE%"
+origin = 0x3E8000
+destination = 0x0F8000
+SENDBYTE 1 "%ABS_FILE%"
+origin = 0x3F8000
+destination = 0x0FC000
+SENDBYTE 1 "%ABS_FILE%"
+
+CLOSE
+